CN105304652A - Array substrate, display, and preparation method of array substrate - Google Patents
Array substrate, display, and preparation method of array substrate Download PDFInfo
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- CN105304652A CN105304652A CN201510833783.6A CN201510833783A CN105304652A CN 105304652 A CN105304652 A CN 105304652A CN 201510833783 A CN201510833783 A CN 201510833783A CN 105304652 A CN105304652 A CN 105304652A
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Abstract
The invention provides an array substrate. The array substrate comprises a substrate, a grid electrode, a grid insulating layer, active layer patterns, a source electrode, a drain electrode, a first covering layer, and a passivation layer, the grid electrode is arranged on a surface of the substrate, the grid insulating layer covers the grid electrode, the active layer patterns cover the grid insulating layer, the source electrode and the drain electrode are arranged on the active layer patterns and respectively positioned at two sides of the grid electrode, the first covering layer is arranged on the active layer patterns and electrically connected with the active layer patterns, the first covering layer is not contacted with the source electrode and the drain electrode, the metal material of the first covering layer is more active than the metal material of the active layer patterns, and the passivation layer covers the first covering layer, the source electrode, the drain electrode, and the active layer patterns. According to the array substrate, the stability of the array substrate is improved, and the device performance of the array substrate is high.
Description
Technical field
The present invention relates to display field, particularly relate to the preparation method of a kind of array base palte, display and array base palte.
Background technology
Metal oxide semiconductor films transistor is with its good device performance, and lower process costs, is considered to the key technology in flat panel display of future generation.But, along with the raising of display performance, comprise high-resolution, narrow frame technology etc., the performance of the thin-film transistor all in array substrate, comprise stability and propose higher requirement.Compare the low-temperature polysilicon silicon technology that current high-end display is conventional, lower stability limits metal oxide semiconductor films transistor application in integrated etc. on glass of drive circuit, have impact on the stability of display.
Summary of the invention
The invention provides a kind of array base palte, the preparation method of display and array base palte, to improve the stability of display.
The invention provides a kind of array base palte, described array base palte comprises the multiple metal oxide semiconductor films transistors in matrix distribution, and described metal oxide semiconductor films transistor comprises:
Substrate;
Grid, described grid is arranged on a surface of described substrate;
Gate insulator, described gate insulator covers on described grid;
Active layer pattern, described active layer pattern covers on described gate insulator;
Source electrode and drain electrode, described source electrode and drain electrode are arranged in described active layer pattern, and lay respectively at the both sides of described grid;
First cover layer, described first cover layer is arranged in described active layer pattern, and is electrically connected with described active layer pattern, described first cover layer not with described source electrode and drain contact; Wherein, described first tectal metal material is more active than the metal material in described active layer pattern;
Passivation layer, described passivation layer covers in described first cover layer, source electrode, drain electrode and active layer pattern.
Wherein, described array base palte also comprises the second cover layer, and described second cover layer is arranged between described first cover layer and described passivation layer, for the protection of the first cover layer.
Wherein, described second cover layer is metal material, and described first tectal metal material is more active than described second tectal metal material.
Wherein, described second cover layer is isolation material.
Wherein, described first tectal metal material is IIA and the IVA race material in the periodic table of elements.
The present invention also provides a kind of display, and described display comprises above-mentioned array base palte.
The present invention also provides a kind of preparation method of array base palte, and the preparation method of described array base palte comprises:
One substrate is provided;
Depositing metal membrane layer on the substrate, to form grid, thus obtains first half one-tenth substrate;
Deposition of gate insulating barrier on described first half one-tenth substrate, thus obtain second half one-tenth substrate;
Described second half one-tenth substrate deposits active layer, to form active layer pattern, thus obtains the 3rd half one-tenth substrate;
Sedimentary cover on described 3rd half one-tenth substrate, thus obtain the 4th half one-tenth substrate, wherein, described cover layer is positioned in described active layer pattern, and described tectal metal material is more active than the metal material of described active layer pattern 40;
Depositing metal membrane layer on described 4th half one-tenth substrate, to form source electrode and drain electrode, to obtain the 5th substrate, wherein, described source electrode and drain electrode are arranged in described active layer pattern, and lay respectively at the both sides of described grid, described cover layer not with described source electrode and drain contact;
Deposit passivation layer on described 5th substrate, to make described passivation layer cover described cover layer, source electrode, drain electrode and active layer pattern, thus obtains described array base palte.
Wherein, described step " on described 3rd half one-tenth substrate sedimentary cover " comprises the following steps:
Described 3rd half one-tenth substrate deposits the first subcovering layer; Wherein, described first cover layer is metal material;
Described first cover layer deposits the second subcovering layer, and for the protection of the first cover layer, wherein, described first cover layer and described second cover layer form described cover layer.
Wherein, described second subcovering layer is metal material, and the metal material of described first subcovering layer is more active than the metal material of described second subcovering layer.
Wherein, the metal material of described first subcovering layer is IIA and the IVA race material in the periodic table of elements.
Array base palte of the present invention comprises substrate, grid, gate insulator, active layer pattern, source electrode, drain electrode, the first cover layer and passivation layer, and described grid is arranged on a surface of described substrate; Described gate insulator covers on described grid; Described active layer pattern covers on described gate insulator; Described source electrode and drain electrode are arranged in described active layer pattern, and lay respectively at the both sides of described grid; Described first cover layer is arranged in described active layer pattern, and is electrically connected with described active layer pattern, described first cover layer not with described source electrode and drain contact; Wherein, described first tectal metal material is more active than the metal material in described active layer pattern; Described passivation layer covers in described first cover layer, source electrode, drain electrode and active layer pattern.Therefore, the material that the metallic atom in relatively described active layer pattern is more active is adopted due to main in described first cover layer, the oxygen atom not forming stable chemical bond in described active layer pattern can be captured on the one hand, Lacking oxygen increases and improves carrier concentration on the one hand, oxygen atom free in described active layer pattern on the other hand reduces, oxygen content change is little, and the stability of described array base palte improves, and namely has higher device performance.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The cross-sectional view of the array base palte that Fig. 1 provides for first aspect of the present invention first preferred embodiment.
The cross-sectional view of the array base palte that Fig. 2 provides for first aspect of the present invention second preferred embodiment.
The structural representation of the display that Fig. 3 provides for second aspect of the present invention preferred embodiment.
Fig. 4 is the flow chart of the preparation method of the array base palte of third aspect of the present invention better embodiment.
Fig. 5 to Figure 11 is the profile of the processing procedure that in the preparation method of array base palte of the present invention, each step is corresponding.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Refer to Fig. 1, first aspect of the present invention preferred embodiment provides a kind of array base palte 100.Described array base palte 100 comprises substrate 10, grid 20, gate insulator 30, active layer pattern 40, source electrode 50, drain electrode the 60, first cover layer 70 and passivation layer 80.
Described grid 20 is arranged on a surface of described substrate 10.
Wherein, described substrate 10 can be glass substrate.Described grid 20 is depositing metal membrane layers on the glass substrate, by coating photoresistance, forms litho pattern after exposure imaging, then after etching, peel off that photoresistance formed.Described metallic diaphragm can adopt AL, the metal materials such as Mo, Cu, Ag.
Described gate insulator 30 covers on described grid 20.
Wherein, gate insulator 30 can adopt SiNx, the materials such as SiOx.
Described active layer pattern 40 covers on described gate insulator 30.
Wherein, described active layer pattern 40 is depositing metal oxide semiconductor active layers on gate insulator 30, through coating photoresistance, forms litho pattern after exposure imaging, is formed at glass photoresistance after etching.Metal-oxide semiconductor (MOS) active layer can be zno-based, In2O3 base, SnO2 sill etc.
Described first cover layer 70 is arranged in described active layer pattern 40, and is electrically connected with described active layer pattern 40.Described first cover layer 70 60 not to contact with described source electrode 50 and draining.Wherein, the metal material of described first cover layer 70 is more active than the metal material in described active layer pattern 40.
Wherein, described first cover layer 70 mainly adopts the material that the metallic atom in relatively described active layer pattern 40 is more active, as II A such as Ba, Si, and IV A race material etc.
Described source electrode 50 and drain electrode 60 are arranged in described active layer pattern 40, and lay respectively at the both sides of described grid 20.
Wherein, described source electrode 50 and drain electrode 60 are by depositing metal membrane layer, through coating photoresistance, form litho pattern after exposure imaging, then after etching, peel off photoresistance formation.Described metallic diaphragm adopts the metal materials such as AL, Mo, Cu, Ag.
Described passivation layer 80 covers in described first cover layer 70, source electrode 50, drain electrode 60 and active layer pattern 40.
Wherein, described passivation layer 80 adopts insulating material, prevents moisture and oxygen from affecting the stability of its lower floor, prevents mechanical damage, guarantees that electrology characteristic is stablized.
It should be noted that, described grid 20, described gate insulator 30, described active layer pattern 40, described source electrode 50, described drain electrode 60, described first cover layer 70 and described passivation layer 80 constitute metal oxide semiconductor films transistor.
In the present embodiment, described array base palte 100 comprises substrate 10, grid 20, gate insulator 30, active layer pattern 40, source electrode 50, drain electrode the 60, first cover layer 70 and passivation layer 80.Described grid 20 is arranged on a surface of described substrate 10.Described gate insulator 30 covers on described grid 20.Described active layer pattern 40 covers on described gate insulator 30.Described first cover layer 70 is arranged in described active layer pattern 40, and is electrically connected with described active layer pattern 40.Described first cover layer 70 60 not to contact with described source electrode 50 and draining.Wherein, the metal material of described first cover layer 70 is more active than the metal material in described active layer pattern 40.Described source electrode 50 and drain electrode 60 are arranged in described active layer pattern 40, and lay respectively at the both sides of described grid 20.Described passivation layer 80 covers in described first cover layer 70, source electrode 50, drain electrode 60 and active layer pattern 40.Therefore, the material that the metallic atom in relatively described active layer pattern 40 is more active is adopted due to main in described first cover layer 70, the oxygen atom not forming stable chemical bond in described active layer pattern 40 can be captured on the one hand, Lacking oxygen increases and improves carrier concentration on the one hand, oxygen atom free in described active layer pattern 40 on the other hand reduces, oxygen content change is little, and the stability of described array base palte 100 improves, and namely has higher device performance.
Refer to Fig. 2, first aspect of the present invention second preferred embodiment provides a kind of array base palte 200.The array base palte 200 that described second preferred embodiment provides is similar to the array base palte 100 that the first preferred embodiment provides, and both differences are: in the second preferred embodiment, and described array base palte 200 also comprises the second cover layer 210.Described second cover layer 210 is arranged between described first cover layer 70 and described passivation layer 80, for the protection of the first cover layer 70.
In the present embodiment, described second cover layer 210 is metal material.The metal material of described first cover layer 70 is more active than the metal material of described second cover layer 210.Wherein, described second cover layer 210 is for preventing described first cover layer 70 oxidized in atmosphere.In other embodiments, described second cover layer 210 also can be isolation material.
Refer to Fig. 3, second aspect of the present invention preferred embodiment provides a kind of display 300.Described display 300 comprises array base palte, colored optical filtering substrates 320 and liquid crystal layer 330.Described array base palte and described colored optical filtering substrates 320 are oppositely arranged, and described liquid crystal layer 330 is arranged between described array base palte and described colored optical filtering substrates 320.Described array base palte is the array base palte 100 of the first preferred embodiment in above-mentioned first scheme.Because described array base palte 100 is described in detail in the preferred embodiment of above-mentioned first scheme first, do not repeat them here.
In other embodiments, described array base palte also can be the array base palte 200 of the second embodiment of above-mentioned first scheme.
In the present embodiment, described display 300 comprises array base palte 100.Described array base palte 100 comprises substrate 10, grid 20, gate insulator 30, active layer pattern 40, source electrode 50, drain electrode the 60, first cover layer 70 and passivation layer 80.Described grid 20 is arranged on a surface of described substrate 10.Described gate insulator 30 covers on described grid 20.Described active layer pattern 40 covers on described gate insulator 30.Described first cover layer 70 is arranged in described active layer pattern 40, and is electrically connected with described active layer pattern 40.Described first cover layer 70 60 not to contact with described source electrode 50 and draining.Wherein, the metal material of described first cover layer 70 is more active than the metal material in described active layer pattern 40.Described source electrode 50 and drain electrode 60 are arranged in described active layer pattern 40, and lay respectively at the both sides of described grid 20.Described passivation layer 80 covers in described first cover layer 70, source electrode 50, drain electrode 60 and active layer pattern 40.Therefore, the material that the metallic atom in relatively described active layer pattern 40 is more active is adopted due to main in described first cover layer 70, the oxygen atom not forming stable chemical bond in described active layer pattern 40 can be captured on the one hand, Lacking oxygen increases and improves carrier concentration on the one hand, oxygen atom free in described active layer pattern 40 on the other hand reduces, oxygen content change is little, and the stability of described array base palte 100 improves, and namely has higher device performance.Therefore, the stability also corresponding raising of described display 300, has higher device performance.
Refer to Fig. 4, third aspect of the present invention preferred embodiment provides a kind of preparation method of array base palte, includes but are not limited to following steps.
Step S101, provides a substrate 10 (referring to Fig. 5).
Wherein, described substrate 101 can be but be not limited only to as glass substrate.
Step S102, depositing metal membrane layer on described substrate 10, to form grid 20, thus obtains first half one-tenth substrate (referring to Fig. 6).
Wherein, described grid 20 is depositing metal membrane layers on the glass substrate, by coating photoresistance, forms litho pattern after exposure imaging, then after etching, peel off that photoresistance formed.Described metallic diaphragm can adopt AL, the metal materials such as Mo, Cu, Ag.
Step S103, deposition of gate insulating barrier 30 on described first half one-tenth substrate, thus obtain second half one-tenth substrate (referring to Fig. 7).
Wherein, gate insulator 30 can adopt SiNx, the materials such as SiOx.
Step S104, described second half one-tenth substrate deposits active layer, to form active layer pattern 40, thus obtains the 3rd half one-tenth substrate (referring to Fig. 8).
Wherein, described active layer pattern 40 is depositing metal oxide semiconductor active layers on gate insulator 30, through coating photoresistance, forms litho pattern after exposure imaging, is formed at glass photoresistance after etching.Metal-oxide semiconductor (MOS) active layer can be zno-based, In2O3 base, SnO2 sill etc.
Step S105, sedimentary cover 70 on described 3rd half one-tenth substrate, thus obtain the 4th half one-tenth substrate, wherein, described cover layer 70 is positioned at described active layer pattern 40, and the metal material of described cover layer 70 is than the metal material active (referring to Fig. 9) of described active layer pattern 40.
Wherein, described first cover layer 70 mainly adopts the material that the metallic atom in relatively described active layer pattern 40 is more active, as II A such as Ba, Si, and IV A race material etc.
Step S106, depositing metal membrane layer on described 4th half one-tenth substrate, to form source electrode 50 and drain electrode 60, to obtain the 5th substrate, wherein, described source electrode 50 and drain electrode 60 are arranged in described active layer pattern 40, and lay respectively at the both sides of described grid 20, and described cover layer 70 60 not to contact (referring to Figure 10) with described source electrode 50 and draining.
Wherein, described source electrode 50 and drain electrode 60 are by depositing metal membrane layer, through coating photoresistance, form litho pattern after exposure imaging, then after etching, peel off photoresistance formation.Described metallic diaphragm adopts the metal materials such as AL, Mo, Cu, Ag.
Step S107, deposit passivation layer 80 on described 5th substrate, to make described passivation layer 80 cover described cover layer 70, source electrode 50, drain electrode 60 and active layer pattern 40, thus obtains described array base palte 100 (referring to Figure 11).
Wherein, described passivation layer 80 adopts insulating material, prevents moisture and oxygen from affecting the stability of its lower floor, prevents mechanical damage, guarantees that electrology characteristic is stablized.
It should be noted that, described grid 20, described gate insulator 30, described active layer pattern 40, described source electrode 50, described drain electrode 60, described first cover layer 70 and described passivation layer 80 constitute metal oxide semiconductor films transistor.
In the present embodiment, the manufacture method of described array base palte comprises provides a substrate 10; Depositing metal membrane layer on described substrate 10, to form grid 20, thus obtains first half one-tenth substrate; Deposition of gate insulating barrier 30 on described first half one-tenth substrate, thus obtain second half one-tenth substrate; Described second half one-tenth substrate deposits active layer, to form active layer pattern 40, thus obtains the 3rd half one-tenth substrate; Sedimentary cover 70 on described 3rd half one-tenth substrate, thus obtain the 4th half one-tenth substrate, wherein, described cover layer 70 is positioned at described active layer pattern 40, and the metal material of described cover layer 70 is more active than the metal material of described active layer pattern 40; Depositing metal membrane layer on described 4th half one-tenth substrate, to form source electrode 50 and drain electrode 60, to obtain the 5th substrate, wherein, described source electrode 50 and drain electrode 60 are arranged in described active layer pattern 40, and laying respectively at the both sides of described grid 20, described cover layer 70 60 not to contact with described source electrode 50 and draining; Deposit passivation layer 80 on described 5th substrate, to make described passivation layer 80 cover described cover layer 70, source electrode 50, drain electrode 60 and active layer pattern 40, thus obtains described array base palte 100.Therefore, the material that the metallic atom in relatively described active layer pattern 40 is more active is adopted due to main in described cover layer 70, the oxygen atom not forming stable chemical bond in described active layer pattern 40 can be captured on the one hand, Lacking oxygen increases and improves carrier concentration on the one hand, oxygen atom free in described active layer pattern 40 on the other hand reduces, oxygen content change is little, the stability of the array base palte 100 made by said method is enhanced, and namely described array base palte 100 has higher device performance.
Further, in described step 105, step " on described 3rd half one-tenth substrate sedimentary cover " comprises the following steps:
Described 3rd half one-tenth substrate deposits the first subcovering layer; Wherein, described first subcovering layer is metal material.
Described first subcovering layer deposits the second subcovering layer, for the protection of the first subcovering layer.Wherein, described first subcovering layer and described second subcovering layer form described cover layer.
It should be noted that, described first subcovering layer mainly adopts the material that the metallic atom in relatively described active layer pattern 40 is more active, as II A such as Ba, Si, and IV A race material etc.
In the present embodiment, described second subcovering layer is metal material.The metal material of described first subcovering layer is more active than the metal material of described second subcovering layer.Wherein, described second subcovering layer is used for preventing described first subcovering layer oxidized in atmosphere.In other embodiments, described second subcovering layer also can be isolation material.In addition, can anneal under vacuum or condition of nitrogen gas after forming the second subcovering layer, thus strengthen stability.
Above disclosedly be only a kind of preferred embodiment of the present invention, certainly the interest field of the present invention can not be limited with this, one of ordinary skill in the art will appreciate that all or part of flow process realizing above-described embodiment, and according to the equivalent variations that the claims in the present invention are done, still belong to the scope that invention is contained.
Claims (10)
1. an array base palte, is characterized in that, described array base palte comprises the multiple metal oxide semiconductor films transistors in matrix distribution, and described metal oxide semiconductor films transistor comprises:
Substrate;
Grid, described grid is arranged on a surface of described substrate;
Gate insulator, described gate insulator covers on described grid;
Active layer pattern, described active layer pattern covers on described gate insulator;
Source electrode and drain electrode, described source electrode and drain electrode are arranged in described active layer pattern, and lay respectively at the both sides of described grid;
First cover layer, described first cover layer is arranged in described active layer pattern, and is electrically connected with described active layer pattern, described first cover layer not with described source electrode and drain contact; Wherein, described first tectal metal material is more active than the metal material in described active layer pattern;
Passivation layer, described passivation layer covers in described first cover layer, source electrode, drain electrode and active layer pattern.
2. array base palte as claimed in claim 1, it is characterized in that, described array base palte also comprises the second cover layer, and described second cover layer is arranged between described first cover layer and described passivation layer, for the protection of the first cover layer.
3. array base palte as claimed in claim 2, it is characterized in that, described second cover layer is metal material, and described first tectal metal material is more active than described second tectal metal material.
4. array base palte as claimed in claim 2, it is characterized in that, described second cover layer is isolation material.
5. array base palte as claimed in claim 1, it is characterized in that, described first tectal metal material is IIA and the IVA race material in the periodic table of elements.
6. a display, is characterized in that, described display comprises the array base palte as described in claim 1-5 any one.
7. a preparation method for array base palte, is characterized in that, the preparation method of described array base palte comprises:
One substrate is provided;
Depositing metal membrane layer on the substrate, to form grid, thus obtains first half one-tenth substrate;
Deposition of gate insulating barrier on described first half one-tenth substrate, thus obtain second half one-tenth substrate;
Described second half one-tenth substrate deposits active layer, to form active layer pattern, thus obtains the 3rd half one-tenth substrate;
Sedimentary cover on described 3rd half one-tenth substrate, thus obtain the 4th half one-tenth substrate, wherein, described cover layer is positioned in described active layer pattern, and described tectal metal material is more active than the metal material of described active layer pattern 40;
Depositing metal membrane layer on described 4th half one-tenth substrate, to form source electrode and drain electrode, to obtain the 5th substrate, wherein, described source electrode and drain electrode are arranged in described active layer pattern, and lay respectively at the both sides of described grid, described cover layer not with described source electrode and drain contact;
Deposit passivation layer on described 5th substrate, to make described passivation layer cover described cover layer, source electrode, drain electrode and active layer pattern, thus obtains described array base palte.
8. the preparation method of array base palte as claimed in claim 7, it is characterized in that, described step " on described 3rd half one-tenth substrate sedimentary cover " comprises the following steps:
Described 3rd half one-tenth substrate deposits the first subcovering layer; Wherein, described first cover layer is metal material;
Described first cover layer deposits the second subcovering layer, and for the protection of the first cover layer, wherein, described first cover layer and described second cover layer form described cover layer.
9. the preparation method of array base palte as claimed in claim 8, it is characterized in that, described second subcovering layer is metal material, and the metal material of described first subcovering layer is more active than the metal material of described second subcovering layer.
10. the preparation method of array base palte as claimed in claim 8, it is characterized in that, the metal material of described first subcovering layer is IIA and the IVA race material in the periodic table of elements.
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| CN103493209A (en) * | 2011-04-22 | 2014-01-01 | 株式会社神户制钢所 | Thin film transistor structure, and thin film transistor and display device provided with said structure |
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| CN103840010A (en) * | 2012-11-21 | 2014-06-04 | 元太科技工业股份有限公司 | Thin film transistor, manufacturing method thereof, array substrate with thin film transistor and display device |
| US20140264320A1 (en) * | 2013-03-13 | 2014-09-18 | Intermolecular, Inc. | Compositional Graded IGZO Thin Film Transistor |
| CN104916701A (en) * | 2014-03-13 | 2015-09-16 | 郑淳护 | Thin film transistor and method of manufacturing the same |
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| CN103493209A (en) * | 2011-04-22 | 2014-01-01 | 株式会社神户制钢所 | Thin film transistor structure, and thin film transistor and display device provided with said structure |
| CN103840010A (en) * | 2012-11-21 | 2014-06-04 | 元太科技工业股份有限公司 | Thin film transistor, manufacturing method thereof, array substrate with thin film transistor and display device |
| US20140264320A1 (en) * | 2013-03-13 | 2014-09-18 | Intermolecular, Inc. | Compositional Graded IGZO Thin Film Transistor |
| CN103500764A (en) * | 2013-10-21 | 2014-01-08 | 京东方科技集团股份有限公司 | Thin-film transistor, and preparation method, array substrate and display thereof |
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