CN105304628A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN105304628A CN105304628A CN201410339800.6A CN201410339800A CN105304628A CN 105304628 A CN105304628 A CN 105304628A CN 201410339800 A CN201410339800 A CN 201410339800A CN 105304628 A CN105304628 A CN 105304628A
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Abstract
The invention provides a semiconductor device. The semiconductor device comprises a device region and a second device region, wherein the first device region comprises a substrate provided with a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer as a first device forming region; the first isolation structures at two sides of the third semiconductor layer and on the substrate; a first insulation layer below a source drain region of the third semiconductor layer and between the first isolation structure and the end part of the second semiconductor layer; the second device region comprises the substrate; a second device on the substrate; the second isolation structure son the substrate at two sides of the second device. The device provided by the invention has the features of being low in cost, small in electric leakage, low in power consumption, fast in speed, simple in process and high in integration level.
Description
Technical field
The present invention relates to field of semiconductor devices, particularly a kind of semiconductor device and manufacture method thereof.
Background technology
Along with constantly reducing of device size, device count on unit are chip gets more and more, this can cause the increase of dynamic power consumption, simultaneously, device size constantly reduce the increase that must cause leakage current, and then cause the increase of quiescent dissipation, and along with the height of semiconductor device integrated, MOSFET channel length constantly shortens, a series of in MOSFET long raceway groove model negligible effect become more remarkable, even become the leading factor affecting device performance, this phenomenon is referred to as short-channel effect.The electric property of short-channel effect meeting deterioration of device, as caused, threshold voltage of the grid declines, power consumption increases and degradation problem under signal to noise ratio.
SOI substrate embedded in silicon dioxide layer in the below of silicon, and relative to body silicon device, the device that SOI substrate is formed can obviously reduce leakage current and power consumption, improves short-channel effect, has obvious performance advantage.But the cost of SOI substrate is higher, and need larger device area to avoid floater effect (FloatingBodyEffect), be difficult to meet the integrated requirement of element height, in addition, owing to embedded in silicon dioxide layer, the heat dispersion of its device is affected.
Summary of the invention
Object of the present invention is intended at least solve one of above-mentioned technological deficiency, provides a kind of semiconductor device and manufacture method thereof.
The invention provides a kind of semiconductor device, comprise the first device area and the second device area; Wherein,
First device area comprises:
Substrate, described substrate has the first semi-conducting material;
Second semiconductor layer, is positioned at substrate;
3rd semiconductor layer, is positioned at the second semiconductor layer, is the first nmosfet formation region;
First isolation structure, is positioned at the 3rd semiconductor layer both sides, substrate;
First insulating barrier, under the source and drain areas of the 3rd semiconductor layer, between the first isolation structure and the second semiconductor layer end;
Second device area comprises:
Substrate;
Second device of substrate;
Second isolation structure, is positioned on the substrate of the second device both sides.
Optionally, also comprise the 3rd device area, described 3rd device area comprises:
Substrate;
The second insulating barrier on substrate;
The 3rd semiconductor layer on second insulating barrier;
The 3rd device on 3rd semiconductor layer;
3rd isolation structure, is positioned on the substrate of the 3rd device both sides.
Optionally, described substrate is body silicon substrate, and the second semiconductor layer is Ge
xsi
1-x, 0<x<1, the 3rd semiconductor layer is silicon.
Optionally, the first insulating barrier and the second insulating barrier are oxide material, are also formed on the sidewall of the first isolation structure, the second isolation structure and the 3rd isolation structure.
Optionally, the second device area also has: be formed at the 3rd semiconductor layer on substrate, and the second device is positioned on the 3rd semiconductor layer on substrate.
In addition, present invention also offers a kind of manufacture method of semiconductor device, comprise step:
There is provided the substrate with the first semi-conducting material, described substrate has first area and second area;
The first area of substrate is formed the second semiconductor layer, and form the 3rd semiconductor layer on the second semiconductor layer;
The second semiconductor layer of part is removed, to form opening from the end of the second semiconductor layer;
Fill up opening, to form insulating barrier;
In the 3rd semiconductor layer both sides of first area, substrate forms the first isolation structure, and the substrate of second area is formed the second isolation structure;
Device is formed respectively in first area and second area.
Optionally, the step first area of substrate forming the second semiconductor layer and the 3rd semiconductor layer is specially:
The second area of substrate is formed the first mask;
At first area Epitaxial growth second semiconductor layer of substrate;
Remove the first mask;
At substrate Epitaxial growth the 3rd semiconductor layer of the second semiconductor layer and second area;
Etch the second semiconductor layer and the 3rd semiconductor layer, to form the second semiconductor layer of patterning and the 3rd semiconductor layer and the first isolated groove in first area, and be formed with source region and the second isolated groove at second area.
Optionally, the step forming opening is specially:
The sidewall of the second semiconductor layer in part first area and the 3rd semiconductor layer forms the 3rd mask;
With the 3rd mask for sheltering, the second semiconductor layer of selective removal part, to form the first opening;
Remove the 3rd mask;
Continue the second semiconductor layer of selective removal part, to form the first opening and the second opening, wherein, the degree of depth of the first opening is greater than the degree of depth of the second opening;
The step forming insulating barrier is specially: carry out oxidation technology, make the second semiconductor layer in the first opening all be oxidized and fill up oxide material in the first opening, the second semiconductor layer part in the second opening is oxidized and fills up oxide material in the second opening.
Optionally, described substrate is body silicon substrate, and the second semiconductor layer is Ge
xsi
1-x, 0<x<1, the 3rd semiconductor layer is silicon.
The semiconductor device that the embodiment of the present invention provides and manufacture method thereof, be integrated with multiple device, wherein, the structure of insulating barrier is formed under the source and drain areas of the 3rd semiconductor layer of the first device, and be semiconductor layer under the channel region of the 3rd semiconductor layer, such device architecture, has the respective advantage of body silicon device and SOI device simultaneously, has low cost, little, low in energy consumption, the speed of leaking electricity is fast, the comparatively simple and feature that integrated level is high of technique.Meanwhile, compared with SOI device, eliminate floater effect and self-heating effect.
In addition, the present invention can also be integrated with the 3rd device further, come by the second insulating barrier and substrate isolation completely in its active area, this device is consistent with the electric property of SOI device, there is identical characteristic, can be formed on body silicon substrate, there is the feature of low cost.In addition, in a manufacturing process, can be realized the adjustment of the second thickness of insulating layer by the thickness of adjustment second semiconductor layer, technique is simple and be easy to integrated.
Accompanying drawing explanation
The present invention above-mentioned and/or additional aspect and advantage will become obvious and easy understand from the following description of the accompanying drawings of embodiments, wherein:
Fig. 1-Figure 13 shows the schematic diagram of each formation stages of the semiconductor device according to the embodiment of the present invention;
Figure 14 shows the flow chart of the manufacture method of the semiconductor device according to the embodiment of the present invention.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
The present invention is intended to propose a kind of semiconductor device, and with reference to shown in Figure 12,13, this semiconductor device comprises the first device area 300 and the second device area 200, wherein:
First device area 300 comprises:
Substrate 10, described substrate has the first semi-conducting material;
Second semiconductor layer 13, is positioned at substrate;
3rd semiconductor layer 14, is positioned on the second semiconductor layer 13, is the forming region of the first device 40;
First isolation structure 26, is positioned on the 3rd semiconductor layer 14 both sides, substrate 10;
First insulating barrier 25, under the source and drain areas of the 3rd semiconductor layer 14, between the first isolation structure 26 and the second semiconductor layer 13 end;
Second device area 200 comprises:
Substrate 10;
Second device 50 of substrate;
Second isolation structure 27, is positioned on the substrate of the second device both sides.
In the present invention, the second semiconductor layer is defined in the substrate of the first device area, this second semiconductor layer has the 3rd semiconductor layer for the formation of the first device, this second semiconductor is only formed in the below of the channel region of the 3rd semiconductor layer, and between the second semiconductor layer and isolation, the below of source and drain areas is formed with the structure of insulating barrier, like this, due to the existence of insulating barrier, substantially reduce leakage current and the power consumption of device, add the integrated level of device.Compared with SOI device, be connected with substrate below channel region, there is better heat dispersion and avoid the generation of floater effect.Meanwhile, because device can adopt body silicon substrate, the restriction of SOI wafer high cost is avoided.
In addition, device of the present invention is applicable to the environment of intense radiation, as strategic arms etc., owing to there is no the insulating barrier of silica under raceway groove, reduce radiation sensitive region area, and can be regulated by backgate, the electron hole pair that release portion irradiation causes, avoids the floater effect that irradiation causes.
Device architecture of the present invention, is easy to integrated with the device of other structures, with the needs of satisfied different circuit performance, as shown in figure 13, is also integrated with the 3rd device area the 400, three device area and comprises:
Substrate 10;
The second insulating barrier 24 on substrate;
The 3rd semiconductor layer 14 on second insulating barrier 24;
The 3rd device 30 on 3rd semiconductor layer 14;
3rd isolation structure 26, is positioned on the substrate of the 3rd device 30 both sides.
The device of the 3rd device area is opened by the second insulating barrier and substrate isolation completely, this kind of device creepage and power consumption less, to meet the requirement of different components performance in circuit.Meanwhile, this device is consistent with the electric property of SOI device, has identical characteristic, can be formed on body silicon substrate, has the feature of low cost.In addition, in a manufacturing process, can be realized the adjustment of the second thickness of insulating layer by the thickness of adjustment second semiconductor layer, technique is simple and be easy to integrated.
In the present invention, can need in a manufacturing process according to device and the demand of device performance, select the material of substrate, the second semiconductor layer, the 3rd semiconductor layer, identical or different semi-conducting material can be adopted, in a preferred embodiment of the invention, described substrate is body silicon substrate, and the second semiconductor layer is Ge
xsi
1-x, 0<x<1, the 3rd semiconductor layer is silicon, and second, third semiconductor layer being formed crystal by epitaxial growth is convenient in the selection of this semi-conducting material, and device has more excellent performance.
In the present invention, second device is formed on substrate, the i.e. part-structure of its device, as doped region can only be formed in the substrate, also can be formed in other semiconductor layers on substrate, in an embodiment of the present invention, as shown in Figure 12,13, second device 40 is formed on second half conductor layer 14 on substrate, the doped region of the second device can be formed in the semiconductor layer on substrate, also can be formed in the semiconductor layer on substrate and substrate, particularly, this semiconductor layer can be the semiconductor layer together formed with the 3rd semiconductor layer of first area.
In embodiments of the present invention, first insulating barrier and the second insulating barrier can be the oxide material of half and half conductor layer material, and the oxide layer 17 on the sidewall of the first isolation structure, the second isolation structure and the 3rd isolation structure can together be formed by self aligned mode with this first and second insulating barrier.
In addition, present invention also offers the manufacture method of above-mentioned semiconductor device, technical scheme for a better understanding of the present invention and technique effect, be described in detail specific embodiment below with reference to flow process Figure 14.
First, in step S01, provide the substrate 10 with the first semi-conducting material, described substrate has first area 100 and second area 200, shown in figure 1.
Described substrate is Semiconductor substrate in the present invention, preferably can for having the body substrate of single semi-conducting material, can be such as Si substrate, Ge substrate, SiGe substrate, it can also be the substrate comprising other elemental semiconductors or compound semiconductor, such as GaAs, InP or SiC etc., in the present embodiment, described substrate is body silicon substrate.
Then, in step S02, the first area 100 of substrate forms the second semiconductor layer 13, and on the second semiconductor layer 13, form the 3rd semiconductor layer 14, shown in figure 6.
In the present embodiment, specifically to comprise the following steps:
First, the second area 200 of substrate forms the first mask 11, shown in figure 2.
As shown in Figure 1, can first deposit first mask material 11 on substrate, as silica, then, smear photosensitive etching agent 12-1 (photoresist) and etch, only forming the first mask layer 11 on the second region, and photosensitive etching agent is removed, as shown in Figure 2.
Then, at first area 100 Epitaxial growth second semiconductor layer 13 of substrate, shown in figure 3.
Epitaxial growth Ge can be carried out
xsi
1-xthe second semi-conducting material 13, wherein, 0<x<1, because second area is covered by the first mask 11, only on the substrate 10 of first area 100, extension defines the second semiconductor layer 13, as shown in Figure 3.
Then, remove this first mask 11, to expose the substrate 10 of second area 200, shown in figure 4.
Then, epitaxial growth the 3rd semiconductor layer 14 is carried out, shown in figure 4.
The 3rd semi-conducting material of epitaxial growth Si can be carried out, the substrate of the second semiconductor layer and second area all defines the 3rd semi-conducting material 14, as shown in Figure 4.
Then, etch the second semiconductor layer and the 3rd semiconductor layer, to form the second semiconductor layer 13 and the 3rd semiconductor layer 14 and first isolated groove 20 of patterning in first area 100, and be formed with source region and the second isolated groove 21, shown in figure 6 at second area 200.
Concrete, first carry out the deposit of the second mask 15, this second mask can be such as silicon nitride, silica or their combination, and on first area 100 and second area 200, smear photosensitive etching agent 12-2 (photoresist), as shown in Figure 5, and etch, form the second mask 15 of patterning, and etch under the covering of this second mask, in first area 100, etch the second semiconductor layer 13 grade of the 3rd semiconductor layer 14, at second area 200, etch the 3rd semiconductor layer 14, to be formed with source region and isolated groove 20 in first area 100 and second area 200 respectively, 21, as shown in Figure 6.
In the present embodiment, adopt the mode of selective epitaxial growth to form the second semiconductor layer, like this, the device of first area can be made consistent with traditional devices, the additional stress avoiding the existence due to the second semiconductor layer to bring and the reduction of device mobility that causes, improve the performance of device.
Certainly, it is only preferred embodiment herein, in other embodiments of the invention, other traditional techniques can also be passed through, form the second semiconductor layer and the 3rd semiconductor layer on the first region, such as, after second, third semiconductor layer of deposit, the method etching away second on second area and the 3rd semiconductor layer is formed.
Then, in step S03, the second semiconductor layer of part is removed from the end of the second semiconductor layer, to form opening 22,23, with reference to shown in Figure 10.
In the present embodiment, will form two kinds of devices on the first region, have insulating barrier completely isolated under a kind of device, another kind of device only has insulator separation under source-drain area, and the step forming opening specifically comprises:
First, the sidewall of the second semiconductor layer in part first area 300 and the 3rd semiconductor layer forms the 3rd mask 16, shown in figure 7.
In the present embodiment, the 3rd mask 16 can be hard mask, as silicon nitride, the step forming the 3rd mask 16 specifically comprises: first, the 3rd mask material of deposit silicon nitride, then, 4th mask of silicon oxide deposition thereon, and photosensitive etching agent is smeared on the 4th mask; Then, with photosensitive etching agent for sheltering, wet etching is adopted, as the solution of HF, patterning the 4th mask; Then, with the 4th mask for sheltering, adopt wet etching, such as phosphoric acid solution, carries out patterning to the 3rd mask, then, remove the 4th mask, so far, second, third semiconductor layer of first area and the sidewall of the second mask and end face define the 3rd mask layer.In other embodiments, as long as the 3rd mask at least covers the sidewall of the second semiconductor layer.
Then, with the 3rd mask for sheltering, the second semiconductor layer of selective removal part, to form the first opening 22, shown in figure 8.
In the present embodiment, can adopt wet etching, optionally remove the second semiconductor layer 13 of the part do not covered by the 3rd mask layer, concrete, solvent can adopt HF, 30%H of 49%
2o
2, 99.8% CH
3cOOH and H
2the mixed solution of O, ratio is 1:18:27:8, by the control time, removes the second semiconductor layer of two end portions.
Then, the 3rd mask 16 is removed, shown in figure 9.
Can wet etching be passed through, optionally remove the 3rd mask layer, as shown in Figure 9.
Then, the second semiconductor layer 13 of selective removal part is continued, to form the first opening 22 and the second opening 23, with reference to shown in Figure 10.
In the present embodiment, above-mentioned wet etching can be adopted optionally to remove the method for the second semiconductor layer, further remove the second semiconductor layer of part, concrete, solvent can adopt HF, 30%H of 49%
2o
2, 99.8% CH
3cOOH and H
2the mixed solution of O, ratio is 1:18:27:8, pass through the control time, further removal second semiconductor layer, for the region forming the first opening, further etching makes the degree of depth of the first opening 22 expand further, etches the second opening 23 that Formation Depth is less than the first opening, as shown in Figure 10 in the region 300 eliminating the 3rd mask.
In other embodiment of the present invention, can only form a kind of device on the first region, this device only has insulator separation under source-drain area, when forming opening, after can forming the second semiconductor layer 13 and the 3rd semiconductor layer 14 on the first region, as shown in Figure 6, directly carry out selective etch, optionally remove portion of material from the end of the second semiconductor layer, thus form opening (scheming not shown).
Then, in step S04, described opening is filled up, to form insulating barrier 24,25, with reference to shown in Figure 11.
In the present embodiment, pass through oxidation technology, as dry oxidation, form insulating barrier, by the time of controlled oxidization, as shown in figure 11, make the second semiconductor layer 13 in the first opening 22 fully oxidized, the 3rd semiconductor layer in this region is made to be full of the second insulating barrier 22 of oxide material for 14 times, this oxide material comprises second, the oxide semiconductor material of the 3rd semiconductor layer and substrate, i.e. silicon germanium oxide and silica, and the second semiconductor layer 13 in the second opening 23 is by the oxidation of part, the first insulating barrier 25 of oxide material is full of under making the two ends of the 3rd semiconductor layer 14 in this region, this oxide material comprises silicon germanium oxide and silica.
While carrying out oxidation technology, the inwall of isolated groove 20,21 also form the insulating barrier 17 of oxide material.
Then, in step S05, in the 3rd semiconductor layer both sides of first area 100, substrate forms the first isolation structure 26, the substrate of second area 200 forms the second isolation structure 27, with reference to shown in Figure 12.
In the present embodiment, this isolation structure 26,27 can be formed by traditional handicraft, first, carry out the deposit of dielectric material, such as silica; Then, carry out planarization, such as carry out cmp (CMP), the method that can be triggered by thickness monitor or terminal, CMP is made to stop at the target thickness place of the second mask, in this CMP step, the second mask of still reserve part thickness in first area and the 3rd region, to make active area injury-free in a cmp process, as shown in figure 12; Then, can selective etch be removed by remaining second mask 15, with reference to shown in Figure 13.Thus, define three device areas, namely the 3rd device area 400 that the first device area 300, second device area 200 formed in first area and second area are formed, as shown in figure 13, the first insulating barrier 25 is formed under the two ends of the 3rd semiconductor layer 14 of the first device area 300,3rd semiconductor layer of the second device area 200 is for 14 times substrate 10, and the 3rd semiconductor layer of the 3rd device area 400 is isolated by the second insulating barrier 24 for 14 times completely.
Finally, in step S06, form device 30,40,50 respectively in first area and second area, with reference to shown in Figure 13.
Technique traditionally device be can form, in the present embodiment, the first device 40, second device 50 and the 3rd device 30 form respectively at the first device area 300, second device area 200 and the 3rd device area 400.As shown in figure 13, at the first device area 300, trap doping 41 is formed in the substrate 10 of the 3rd semiconductor layer 14, second semiconductor layer 13 and part, on the 3rd semiconductor layer 14 of the first device area, define grid structure 42; The sidewall of described grid structure 42 defines side wall 43; In the 3rd semiconductor layer of grid structure 42 both sides, define source-drain area 44, this source-drain area 44 is positioned on the first insulating barrier 25; Metal silicide layer 45 is also formed on source-drain area 44.
At the second device area 200, trap doping 51 is formed in the substrate 10 of the 3rd semiconductor layer 14 and part, on the 3rd semiconductor layer 14 of the second device area, define grid structure 52; The sidewall of described grid structure 52 defines side wall 53; Source-drain area 54 is defined in the 3rd semiconductor layer of grid structure 52 both sides; Metal silicide layer 55 is also formed on source-drain area 54.In other embodiments, second area can not have formation the 3rd semiconductor layer, the second device is formed directly on substrate, and doped region is formed in the substrate, identical with common body silicon device.
At the 3rd device area 400, trap doping 31 is formed in the 3rd semiconductor layer 14, is kept apart by the second insulating barrier 24 completely, on the 3rd semiconductor layer 14 of the second device area, define grid structure 32 between the 3rd device 30 and substrate 10; The sidewall of described grid structure 32 defines side wall 33; Source-drain area 34 is defined in the 3rd semiconductor layer of grid structure 32 both sides; Metal silicide layer 35 is also formed on source-drain area 34.
Afterwards, the miscellaneous part of device can also be formed, as source and drain contact, gate contact and interconnection structure etc.
So far the integrated of three kinds of devices of the embodiment of the present invention is completed, in the present embodiment, the mode that have employed extension forms the second semiconductor layer and the 3rd semiconductor layer, like this, the device area of the first device can be made consistent with traditional device, the existence avoiding the second semiconductor layer may bring additional stress, cause the problem that device mobility reduces, simultaneously, for the device of insulating barrier and traditional body silicon device technique fully combine under the source and drain formed, meet the multifarious requirement of circuit performance, do not affect the electric property of traditional devices simultaneously.Meanwhile, come by the second insulating barrier and substrate isolation completely in the active area of the 3rd device, this device is consistent with the electric property of SOI device, has identical characteristic, can be formed on body silicon substrate, has the feature of low cost.In addition, in a manufacturing process, can be realized the adjustment of the second thickness of insulating layer by the thickness of adjustment second semiconductor layer, technique is simple and be easy to integrated.
The above is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.
Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (9)
1. a semiconductor device, comprises the first device area and the second device area; Wherein,
First device area comprises:
Substrate, described substrate has the first semi-conducting material;
Second semiconductor layer, is positioned at substrate;
3rd semiconductor layer, is positioned at the second semiconductor layer, is the first nmosfet formation region;
First isolation structure, is positioned at the 3rd semiconductor layer both sides, substrate;
First insulating barrier, under the source and drain areas of the 3rd semiconductor layer, between the first isolation structure and the second semiconductor layer end;
Second device area comprises:
Substrate;
Second device of substrate;
Second isolation structure, is positioned on the substrate of the second device both sides.
2. semiconductor device according to claim 1, is characterized in that, also comprises the 3rd device area, and described 3rd device area comprises:
Substrate;
The second insulating barrier on substrate;
The 3rd semiconductor layer on second insulating barrier;
The 3rd device on 3rd semiconductor layer;
3rd isolation structure, is positioned on the substrate of the 3rd device both sides.
3. semiconductor device according to claim 1 and 2, is characterized in that, described substrate is body silicon substrate, and the second semiconductor layer is Ge
xsi
1-x, 0<x<1, the 3rd semiconductor layer is silicon.
4. semiconductor device according to claim 2, is characterized in that, the first insulating barrier and the second insulating barrier are oxide material, is also formed on the sidewall of the first isolation structure, the second isolation structure and the 3rd isolation structure.
5. semiconductor device according to claim 1, is characterized in that, the second device area also has: be formed at the 3rd semiconductor layer on substrate, and the second device is positioned on the 3rd semiconductor layer on substrate.
6. a manufacture method for semiconductor device, is characterized in that, comprises step:
There is provided the substrate with the first semi-conducting material, described substrate has first area and second area;
The first area of substrate is formed the second semiconductor layer, and form the 3rd semiconductor layer on the second semiconductor layer;
The second semiconductor layer of part is removed, to form opening from the end of the second semiconductor layer;
Fill up opening, to form insulating barrier;
In the 3rd semiconductor layer both sides of first area, substrate forms the first isolation structure, and the substrate of second area is formed the second isolation structure;
Device is formed respectively in first area and second area.
7. manufacture method according to claim 6, is characterized in that, the step that the first area of substrate is formed the second semiconductor layer and the 3rd semiconductor layer is specially:
The second area of substrate is formed the first mask;
At first area Epitaxial growth second semiconductor layer of substrate;
Remove the first mask;
At substrate Epitaxial growth the 3rd semiconductor layer of the second semiconductor layer and second area;
Etch the second semiconductor layer and the 3rd semiconductor layer, to form the second semiconductor layer of patterning and the 3rd semiconductor layer and the first isolated groove in first area, and be formed with source region and the second isolated groove at second area.
8. manufacture method according to claim 6, is characterized in that, the step forming opening is specially:
The sidewall of the second semiconductor layer in part first area and the 3rd semiconductor layer forms the 3rd mask;
With the 3rd mask for sheltering, the second semiconductor layer of selective removal part, to form the first opening;
Remove the 3rd mask;
Continue the second semiconductor layer of selective removal part, to form the first opening and the second opening, wherein, the degree of depth of the first opening is greater than the degree of depth of the second opening;
The step forming insulating barrier is specially: carry out oxidation technology, make the second semiconductor layer in the first opening all be oxidized and fill up oxide material in the first opening, the second semiconductor layer part in the second opening is oxidized and fills up oxide material in the second opening.
9. the manufacture method according to claim 7 or 8, is characterized in that, described substrate is body silicon substrate, and the second semiconductor layer is Ge
xsi
1-x, 0<x<1, the 3rd semiconductor layer is silicon.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050189589A1 (en) * | 2004-02-27 | 2005-09-01 | International Business Machines Corporation | Hybrid soi/bulk semiconductor transistors |
| CN1731570A (en) * | 2005-08-31 | 2006-02-08 | 北京大学 | Method for making MOS transistor with source-drain on insulating layer |
| CN101924138A (en) * | 2010-06-25 | 2010-12-22 | 中国科学院上海微系统与信息技术研究所 | MOS (Metal Oxide Semiconductor) device structure for preventing floating-body effect and self-heating effect and preparation method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050189589A1 (en) * | 2004-02-27 | 2005-09-01 | International Business Machines Corporation | Hybrid soi/bulk semiconductor transistors |
| CN1731570A (en) * | 2005-08-31 | 2006-02-08 | 北京大学 | Method for making MOS transistor with source-drain on insulating layer |
| CN101924138A (en) * | 2010-06-25 | 2010-12-22 | 中国科学院上海微系统与信息技术研究所 | MOS (Metal Oxide Semiconductor) device structure for preventing floating-body effect and self-heating effect and preparation method thereof |
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