CN105302746A - Multiprotocol storage controller - Google Patents
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- CN105302746A CN105302746A CN201410317367.6A CN201410317367A CN105302746A CN 105302746 A CN105302746 A CN 105302746A CN 201410317367 A CN201410317367 A CN 201410317367A CN 105302746 A CN105302746 A CN 105302746A
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Abstract
The present invention relates to a multiprotocol storage controller. A system and a method described herein are used for coupling the storage controller (104) to various storage devices (110, 111, and 112). An embodiment of the storage controller comprises an interface(301) operably and communicably coupled to a storage device. The storage controller also comprises a processor (502). The processor (502) can operably choose between storage device hardware protocol detection and storage device firmware protocol detection. When the storage device is communicably coupled to the interface, the processor (502) detects a storage device protocol according to a chosen protocol. The storage controller then selects a protocol according to the detected storage device protocol to process an input/output request from a host (105).
Description
The cross reference of related application
This application claims the right of priority of U.S. Provisional Patent Application No.61/86236l (August 5 2013 applying date, " multi-protocol storage controller (MultiProtocolStorageController) "), this application is incorporated by reference at this.
Technical field
The present invention relates to the field of memory controller.
Background technology
There is numerous storage device interfaces, these storage device interfaces are constantly challenged to storage domain.Such as, the memory device based on quick external component interconnected agreement (PCIe) is combined with serial connecting small computer system interface (SAS) storage domain now.And in some cases, replace SAS memory device, PCIe memory device is by " hot plug (hot-swapped) ".But PCIe is a kind of packet-based Connectionless Transport Protocal, and SAS is end to end based on the agreement connected, and it does not provide without connecting transmission, thus makes interoperability especially have challenge.But more particularly, time in by hot plug to storage domain, adopt a kind of memory controller of agreement can not detect the memory device of another kind of agreement.
Summary of the invention
System and method presented here creates conditions for memory controller is couple to multiple different types of memory device.In one embodiment, memory controller comprises the interface that can be communicatively coupled to memory device.Memory controller also comprises processor, this processor operationally detects at the hardware protocol of memory device and selects between the firmware protocols detection of memory device, and when memory device communication is couple to described interface, according to the protocol detection selected, detect the agreement of memory device.Memory controller is subsequently according to the agreement of the memory device detected, and selection protocol processes the input/output request of from host.
As design alternative, each embodiment disclosed herein can be realized in every way.Such as, embodiment can take the form of computer hardware, software, firmware or their combination.The following describes other Illustrative Embodiments.
Accompanying drawing explanation
With reference now to accompanying drawing, illustrate some embodiments of the present invention.In accompanying drawing, identical Reference numeral represents the element of identical element or identical type.
Fig. 1 is the block scheme of the illustration memory controller that can work together with the equipment of different agreement.
Fig. 2 is the process flow diagram of the illustration process of the memory controller of Fig. 1.
Fig. 3 is the block scheme of another illustration memory controller.
Fig. 4 is the process flow diagram of the illustration process of the memory controller of Fig. 3.
Fig. 5 is the diagram of the illustration hardware protocol detection scheme of the memory controller of Fig. 1 and 3.
Fig. 6 is the process flow diagram of another illustration process of the memory controller of Fig. 3.
Fig. 7 is that wherein computer-readable medium provides the block scheme of the illustration computing system of the instruction of the method for carrying out here.
Embodiment
Accompanying drawing and explanation below illustrate concrete Illustrative Embodiments of the present invention.Thus should be understood that those skilled in the art can design various scheme, although be not here specifically recited or represent, but these scheme imbodies principle of the present invention, thus be included within the scope of the present invention.In addition, any example illustrated here is used to help to understand principle of the present invention, should not be construed as limited to example and the condition of concrete record.Thus the present invention is not limited to specific embodiment described below or example.
Fig. 1 is the block scheme of the illustration memory controller 104 that can work together with the equipment of different agreement.The I/O request of memory controller 104 operationally processing host system 105, and asks respective storage protocol according to these I/O, they is directed to each target device 110,111 and 112.Such as, in the present embodiment, target device 110 is SAS memory devices, target device 111 is PCIe memory devices, target device 112 is the memory devices utilizing certain other agreement (such as, Serial Advanced Technology Attachment (SATA) agreement, fiber channel protocol, business system connection, fiber channel protocol, USB (universal serial bus) (USB) agreement, the Internet serial connecting small computer system interface (ISCSI) agreement etc. based on IP agreement).When one of target device 110,111,112 is couple to memory controller 104, memory controller 104, operationally by hardware and/or firmware, finds the kind of the memory device that it connects.Once find, memory controller 104 just can by target device 110,111,112 respective storage protocols, process and ask from host computer system 105 to the I/O of target device 110,111,112.
Target device 110,111,112 can Direct Attached Storage controller 104, or they are by storage system extension element, and such as extender 103 is coupled.Such as, one or more extender is operationally directly connected to other target device 110,111,112, and other extender, to provide " switching fabric " that I/O request exchanged to the suitable equipment determined by memory controller 104.The example of extender 103 comprises the wide port extender that those agreements (such as SAS, PCIe, USB, SATA etc.) that such as can mention according to various protocols work.
The example of target device 110,111,112 comprises memory device, such as disc driver and solid-state drive (SSD).In this, target device 110,111,112 can represent host computer system 105 provides data to store.Host computer system 105 configurable to about target device 110,111, the read/write requests that operates of 112 one of any I/O (I/O).Host computer system 105 can be any suitable computing equipment or the system that can carry out I/O operation, such as, and server, workstation, personal computer etc.
Memory controller 104 can carry out device discovery, manages the I/O of target device 110,111,112 request and process any equipment, system, software for the I/O order of the data of target device 110,111,112, or their combination.Such as, memory controller 104 can be realized as custom circuit, is embodied as the special or general processor performing the programmed instruction be kept in the program storage of association, or their certain combination.Memory controller 104 can be the host bus adapter (HBA) of independently SAS equipment, main frame or the integrated package of host computer system 105.
Memory controller 104 comprises and is suitable for being couple to host computer system 105, and the front-end interface that the I/O of Receiving Host system 105 asks.Memory controller 104 also comprises and is suitable for being couple to and supports PCIe equipment (such as, the extender of compatible with PCI e, PCIe switch and PCIe target device 111), SAS equipment (such as, SAS target device 110 and SAS expander) and other back end interface (more detailed below represent and illustrate).
Extender 103 be by means of with may being connected of multiple memory device, operationally any equipment, system, the software of extension storage system, or their combination.In this, extender 203, by multiple physics transceiver, is connected to SAS assembly, such as SAS target device 110 and other extender.More particularly, extender 103 can by many different agreements, such as above-mentioned those agreements (such as, SAS, PCIe, USB, SATA etc.), be directly connected to multiple target device, and the protocol detecting method be present in memory controller 104 can be utilized.
Although represent about the extender of some and target device and illustrate, but the present invention is not intended to be confined to the assembly of any given number or their illustration connects.Below with reference to the process flow diagram of Fig. 2, the certain operations details of memory controller 104 is described.
Fig. 2 is the process flow diagram of the illustration process 200 of the memory controller 104 of Fig. 1.When at processing unit 201, when memory controller 104 is communicatively coupled to memory device, start to process 200.Such as, when directly or indirectly (such as, by extender 103) is couple to memory controller 104 to one of target device 110,111,112, the hardware that memory controller 104 starts target device finds and/or firmware discovery.In this, at processing unit 202, memory controller 104 detects at the hardware protocol of memory device and selects between the firmware protocols detection of memory device.
Once have selected detection scheme, at processing unit 203, memory controller just starts the agreement detecting memory device automatically.Such as, when memory device is by hardware signaling and/or time-domain reflector, when being couple to the interface of memory controller, memory controller 104 can adopt hardware detection scheme to determine the agreement of memory device.If memory device is not detected by hardware protocol detection scheme, memory controller 104 can failover to firmware detection scheme, by attempting link establishment, until memory device is reacted by various agreement.But memory controller 104 also can be configured to from firmware protocols detection scheme, and then failover is to hardware protocol detection scheme, or even can be configured to only utilize one or another kind of detection scheme to detect the agreement of the memory device of attachment.
Once have detected the agreement of memory device, at processing unit 204, memory controller 104 just can selection protocol, asks with the I/O processed from host computer system 105.Such as, memory controller 104 may be configured with various protocol stack.Once the agreement of memory device is detected, memory controller 104 is just by suitable protocol stack, and the I/O processed from host computer system 105 asks.
Fig. 3 is the block scheme of the memory controller 104 of another illustration.In the present embodiment, memory controller 104 is configured with system interface 301, and system interface 301 operationally communicates and physically couples the physical interface of memory controller 104 and host computer system 105, and asks according to PCIe and SAS/SATA protocol stack process I/O.PCIe stack comprises PCIe upper strata 302, PCIe link layer and PCIe Physical layer 306.SAS/SATA stack comprises SAS/SATA upper strata 303, SAS/SATA link layer 305 and SAS/SATA Physical layer 307.
Memory controller 104 also comprises when the agreement of memory device being detected, operationally selects the protocol selection logic 308 of suitable protocol stack.Protocol multiplexer 309 and protocol selection logic 308 coupled in communication, to control when the agreement of memory device being detected, will use which protocol stack in protocol stack.
Protocol selection logic 308 works together with relevant protocol multiplexer 309, is connected to PCIe protocol stack or SAS/SATA protocol stack to select the physical interface of memory device.The hardware protocol that serial/deserializer (SerDes) 310 operationally carries out the memory device be attached detects.Transmit the instruction of successful link establishment from PCIe link layer 304 and SAS/SATA link layer 307, to guarantee when succeeding, protocol multiplexer 309 is still fixed on the agreement of current selection.In certain embodiments, when the specific agreement of the current selection of protocol multiplexer 309, the link layer of this agreement and Physical layer are (such as, PCIe link layer 304, PCIe Physical layer 306, SAS/SATA link layer 305, SAS/SATA Physical layer 307) be activated, minimum to make power consumption be down to.Such as, by making not mourning in silence with protocol stack of memory controller 104, and closing the clock in memory controller 104, can electricity consumption be reduced.This prevents mos gate pole from switching back and forth, and due to the switching of the capacitive load of grid, described switching back and forth can become one of reason of the sizable power wastage in semiconductor.
In another embodiment, even if when the current selection PCIe agreement of protocol multiplexer 309, SAS/SATA Physical layer 307 also can directly utilize the dropout from SerDes310 to indicate, when detecting that effective SAS/SATA is with outer (OOB) signal, to be switched to SAS/SATA agreement fast.Such as, protocol selection logic 308 can instruct protocol multiplexer 309 to select the memory device communication of PCIe protocol stack and attachment.But the memory device of attachment may be SAS/SATA memory device.PCIe protocol stack attempt with the communication apparatus communication of attachment while, memory controller 104 can operate the OOB signal with hardware detection SAS/SATA more quickly.In this, in fact the detection of OOB signal can be carried out in SAS/SATA Physical layer 307.SerDes310 is supplied to SAS/SATA Physical layer 307, SAS/SATA Physical layer 307 dropout instruction and finds suitable OOB pattern again.Protocol selection logic 308 selects SAS/SATA protocol stack subsequently, and stops the trial of the memory device communication of PCIe protocol stack and attachment.
Automatic OOB check processing can be provided concurrently with the detection of the progress on PCIe link layer 304.Do not make progress at PCIe, and when SerDes310 receives effective SAS/SATAOOB signal, protocol multiplexer 309 is switched to SAS/SATA and controls (that is, SAS/SATA protocol stack), so that the memory device of attachment can be replied, send OOB signal.Even if it is movable to there is not PCIe or SAS/SATA, protocol multiplexer 309 also can regularly be switched to SAS/SATA protocol stack, send OOB signal, to observe the hot plug timeout requirements of T10SAS standard (T10 sets up the technical committee about the standard of SCSI, SATA and SAS).Represent and describe the example of this detection in the process flow diagram of Fig. 6.
Under any circumstance, be successfully established the instruction of link by protocol selection logic 308, transmit from PCIe link layer 304 to SAS/SATA link layer 305, vice versa, so that protocol selection logic 308 suspends any further trial of handoff protocol (such as, by by interrupting or some other means, successful result is informed the firmware of memory controller 104).
According to number of ways, the mode selecting specific protocol detection scheme in memory controller 104 can be realized.Fig. 4 is the process flow diagram of such illustration process that the protocol detection of memory controller 104 is selected.More specifically, a kind of Programmable protocol system of selection of graphic extension in Fig. 4, described method provides the priori according to system architecture to the firmware of memory controller 104, the ability of selection protocol.Such as, in processing unit 351, memory controller 104 starts firmware protocols and detects, thus firmware was attempted before hardware detection or with hardware detection concurrently, initiate the communication of memory device with attachment.The memory device being attached to memory controller 104 may be known, so that in processing unit 352, the firmware of memory controller 104 is selected by the predetermined firmware of agreement, automatically starts protocol detection.In this, the firmware of memory controller 104 can in processing unit 354, automatic selection PCIe agreement (if equipment known be PCIe memory device), or in processing unit 355, automatically select SAS/SATA agreement (if equipment known be SAS/SATA memory device).
On the other hand, the firmware protocols of processing unit 352 detects and circulation can be provided to select the allowed protocol of memory controller 104 to memory controller 104, until produce with the memory device of attachment the ability be connected.Such as, firmware can make the agreement of searching " PhyReady " SAS/SATA condition or the agreement of searching " LinkUp " PCIe condition replace.In either case, the firmware of memory controller 104 selects PCIe operation or SAS/SATA operation, and protocol multiplexer 309 is configured to suitable agreement, until the firmware of memory controller 104 changes configuration.
If the firmware protocols of processing unit 351 detects and is prohibited, so at processing unit 356, memory controller 104 generally can realize hardware protocol and detect.If the agreement of memory controller 104 firmware to expection is known nothing, thus determine not circulate between agreement, so can the pattern of protocol detection of hardware sensing of start treatment unit 356.Once the protocol detection of hardware sensing is about specific protocol, successfully realizes PhyReady or LinkUp state, so suspend any further protocol switching, until firmware starts protocol switching again.If the protocol detection of the hardware sensing of processing unit 356 is prohibited, protocol multiplexer 309 so can be made to keep idle condition, so that not selection protocol stack.Such as, go up in this respect, the PCIe protocol stack of memory controller 104 and SAS protocol stack all can keep mourning in silence.
If the protocol detection of the hardware sensing of processing unit 356 is activated, so memory controller 104 can be configured to circulation selection protocol stack (processing unit 358), the agreement (processing unit 359) of automatic detection OOB signal, and/or transmission pulse, and by time-domain reflector (" TDR "), analyze reflection wave (processing unit 360).For example, at processing unit 358, protocol multiplexer 309 with the programmable residence time, can make PCIe protocol stack and SAS/SATA protocol stack alternately, until succeed to any agreement.After being successfully established connection by specific protocol, interrupt instruction memory controller 104 starts the agreement according to memory device, process I/O request.Usually, all passages relevant to x2, x4, x8 or x16PCIe structure should replace simultaneously, PCIe link layer 304 during training sequence, automatic detection path turn around condition, so that do not need to circulate and select different path reversion configuration.
In processing unit 359, protocol multiplexer 309 can be configured to be defaulted as PCIe Physical layer 306, but dropout instruction, such as RXLOS signal still can be transmitted to SAS/SATA Physical layer 307, to support OOB Sequence Detection.Subsequently, if memory controller 104 can by PCIe agreement, successfully set up link (such as, " LinkUp "), so protocol multiplexer 309 locks onto the PCIe protocol stack of memory controller 104.But if SAS/SATA Physical layer detects effective COMINITOOB sequence of SAS/SATA agreement, so protocol multiplexer 309 is switched to SAS/SATA Physical layer 307, so that SAS/SATA Physical layer 307 can send COMINIT to the memory device of attachment.If in programmable hot plug time-out period (general 10-500ms), without any agreement success, so by sending COMINIT to memory device in the trial of " brute force " connection memory device, memory controller 104 can select SAS/SATA Physical layer 307 automatically.On the other hand, memory controller 104 can continue monitoring simply or carry out alternative protocol detection scheme.
In processing unit 360, SerDes310 regularly sends pulse, and analyzes reflection wave, couples characteristic to detect different AC, and described AC couples the agreement of the equipment of characteristic instruction attachment.Such as, based on its standardized storage protocol electric requirement, memory device has certain moduli and intends signaling characteristic.The TDR pulse sending memory device to can be reflected back toward SerDes310, and is analyzed by memory controller 104, to determine the kind of the memory device being couple to memory controller 104.Below in Figure 5, represent and the example that this hardware/TDR detects is described.
Fig. 5 is the diagram 370 of the illustration hardware detection scheme of memory controller 104.A special challenge of sensing PCIe and SAS electrical specification is the wide region of the passive channel length adopted in SAS.SAS passage length can from only several centimetres vary to nearly 10 meters, this can cause the delay of the reflection TDR ripple of few tens of nano-seconds (such as, being illustrated as " flight time × 2 ").
SerDes310 can realize sample clock generator (373), to determine when reflection wave sampling, and assessment charging (charge) characteristic.Such timer can be configured to when launching TDR pulse (that is, thick line 371) and start.On the other hand, utilizing for detecting the threshold value (372) returning the reflection TDR pulse arriving SerDes310 from the SAS passage of length the unknown, the accurate measurement of the charge characteristic of the pulse in this SAS passage can be obtained.Another kind of alternatives comprises the dV/dt receiver of the arrival for detection of reflected TDR pulse.Once reflection TDR pulse arrives, sample clock generator will be started (373).When sample clock generator expires, can be sampled (such as, sampled point 380) at the voltage of SerDes310, and compare with each threshold voltage (such as, 372,374,375).Such as, if SAS charges, detection threshold is exceeded, and so TDR pulse can point out that SAS equipment is attached to memory controller 104.Otherwise TDR pulse can point out that PCIe memory device is attached, or be not attached any equipment (375) at all.Such threshold value can be programmed in the firmware of memory controller 104, to be provided in the dirigibility of different realizations and working environment aspect.
In another embodiment, fault secure timer can be utilized determine the kind of the memory device being attached to memory controller 104.Such as, when launching TDR pulse (371), the fault secure timer of 2 times that are set as maximum cable length delay can be started.If reflection TDR pulse detected, so sample clock generator can be triggered, thus the sampling (such as, sampled point 380) of charge value can occur.If do not observe reflection TDR pulse, so when fault secure timer expiration, the sampling of charge value can be there is.Such as, if link is by suitable termination, so there is not reflection, thus fault secure timer can start.If link is not by termination, so 2 times of times to the delay of the maximum length of transmission line, reflect automatic detection trigger.
On the other hand, baseline timer (376) can use together with fault secure timer, with according to sampling, instead of makes assessment completely based on absolute voltage threshold value, assesses charging ramp (such as, 390,391,392).Such as, baseline timer after being used in and receiving TDR pulse at once to reflection TDR impulse sampling.Baseline timer can catch first point determined in charging ramp.Afterwards, sample clock generator can be used to catch second point can determining charging ramp from it.Certainly can utilize multiple sample, with improve precision and improve vulnerability to jamming (that is, determine more accurately which be signal which be noise).
For starting the passage that this reflection TDR impulse detection technique of sample clock generator is various length, comprising and providing dirigibility more than those passages of 10 meters of passive limitation of lengths of SAS.Also can utilize other threshold value, distinguish with various the meticulousr of protocol-dependent charge characteristic to provide.Analog-digital converter can be adopted, to detect when comparatively determining charging level by numeric ratio.By obtaining multiple sample within the duration of charging, and before determining charge characteristic, numerical analysis and curve being carried out to sampled point 380 as a result, extra accuracy can be obtained.
Fig. 6 is the process flow diagram of another illustration process 400 of memory controller 104.Process 400 graphic extensions select agreement in delayed.When link goes offline, memory controller 104 can be attempted re-establishing link by most recently used agreement.For when in fact not installing new equipment, the situation that link is reset because of reinitializing of firmware instructions, this may be useful.Such as, at processing unit 401, firmware resets memory controller 104, thus loses with the connection of memory device.At processing unit 402, after the initialization of memory controller 104, memory controller 104 carries out receiver subsequently and detects sequence, to obtain the PCIe equipment of previously attachment.At processing unit 404, after certain delay (processing unit 403), memory controller 104 repeatedly can carry out this operation, until PCIe equipment detected.Such as, memory controller 104 can be configured to before the protocol detection being switched to another kind of form, and the detection of the memory device of attachment is attempted on pre-determined number ground.
Once PCIe equipment be detected, at processing unit 405, memory controller just selects PCIe protocol stack, to set the PCIe pattern of memory controller 104.Subsequently at processing unit 406, memory controller 104 starts the PCIe link initialization of PCIe link layer 304.Afterwards, at processing unit 407, memory controller 104 judges whether PCIe initialization makes progress.
If PCIe initialization makes progress, so at processing unit 408, memory controller 104 initialization PCIe is in progress timer, then circulates, until at processing unit 409, till establishing link with PCIe equipment.Once establish link, at processing unit 410 and 412, memory controller starts hot plug timer, to judge whether PCIe equipment is ready to communicate with memory controller 104.The object of this circulation is if PCIe link is not ready in arbitrfary point, so before trial SAS/SATA agreement, allows a certain amount of time to re-establish communication with PCIe equipment.If link is not ready, so memory controller 104 detects sequence by the receiver restarting processing unit 402, attempts connecting.But, as long as link is got ready, hot plug timer just can continue to be reset.If link goes offline, so hot plug timer works on, so that attempts by this specific protocol and rebuild link only to so many time.If hot plug timer finally expires (such as, processing unit 413 and 422), so memory controller 104 attempts communication by another kind of agreement.
If PCIe initialization does not make progress, so at processing unit 413, memory controller 104 judges that whether the hot plug timer started in processing unit 410 is expired.If not, so determine whether SASOOB signal to be detected at processing unit 414, SerDes310.If not, so memory controller 104 returns processing unit 407, to judge whether PCIe initialization makes progress.If hot plug timer expiration or SASOOB signal detected, so at processing unit 415, SAS/SATA protocol stack selected by memory controller 104, to set up the SAS/SATA pattern of memory controller 104.In this, at processing unit 416, memory controller 104 starts the SAS/SATA link initialization of SAS/SATA link layer 305, thus determines to abandon PCIe initialization.
Once link layer 305 is activated, at processing unit 417, memory controller 104 just judges whether SAS initialization starts, and makes progress.If so, so at processing unit 418, memory controller 104 starts SAS initialization progress timer, and at processing unit 419, determines whether to establish SAS/SATA link.Such as, SAS initialization progress timer can set up a certain amount of time to be linked to memory device for memory controller 104, assuming that this memory device is SAS memory device.If do not set up link in described time quantum, so memory controller 104 returns processing unit 417, to judge whether SAS initialization makes progress.
If establish SAS/SATA link with SAS/SATA link layer 305, so memory controller 104 is at processing unit 420, starts hot plug timer, and at processing unit 421, judges that whether link is ready.If link is not ready, so memory controller 104 returns processing unit 417, to judge whether SAS initialization makes progress.If so, so while link is got ready, memory controller 104 can continue initialization hot plug timer.Otherwise memory controller 104 can determine that link is not ready, thus at processing unit 416, attempt restarting SAS/SATA link initialization.If SAS initialization does not make progress (that is, processing unit 417), so at processing unit 422, memory controller 104 judges whether hot plug timer expires.If not, so memory controller 104 can continue to wait for SAS initialization, until hot plug timer expiration.When timer expires really, memory controller 104 returns processing unit 402, detects sequence (such as, select another protocol stack, protocol detection scheme, exits detection completely, etc.) to carry out another receiver.
Compared with current protocol detection scheme, above-described embodiment provides several advantage.Such as, above-described embodiment provide can detect various agreement one of any dynamically or static configuration protocol detection.Although exemplified with two kinds of protocol stacks, but the present invention is not limited thereto.Memory controller 104 can be configured to allow memory controller to couple and the various protocol stacks communicated with various target device.Protocol detection scheme comprises circulation and selects to carry out the parallel protocol detection of the OOB signaling of SAS agreement, and the agreement of passive protocol detection by the hardware sensing electrical specification of attached peripheral device.
The present invention can take entirely hardware embodiment, pure software embodiment, or comprises the form of embodiment of hardware and software element.In one embodiment, use software simulating the present invention, described software comprises (but being not limited to) firmware, resident software, microcode etc.Fig. 6 graphic extension wherein computer-readable medium 506 is provided for the computing system 500 of the instruction carrying out any means disclosed herein.
In addition, the present invention can take the form of the computer program that can access from computer-readable medium 506, computer-readable medium 506 provides for computing machine or any instruction execution system, or the program code be combined with computing machine or any instruction execution system.Concerning this explanation, computer-readable medium 506 can be can visibly preserve for instruction execution system, equipment or device (comprising computer system 500), or any equipment of the program be combined with it.
Medium 506 can be any tangible electronics, magnetic, optical, electrical magnetic, infrared or semiconductor system (or equipment or device).The example of computer-readable medium 506 comprises semiconductor or solid-state memory, tape, detachable computing machine reel, random access memory (RAM), ROM (read-only memory) (ROM), hard disk and CD.Some examples of CD comprise compact disk-ROM (read-only memory) (CD-ROM), compact disk-read/write (CD-R/W) and DVD.
The computing system 500 being suitable for preservation and/or executive routine code can comprise the one or more processors 502 directly or being indirectly couple to storer 508 by system bus 510.The local storage that storer 508 adopts the term of execution of can being included in program code actual, mass storage and the interim storage of at least some program code is provided so as to reduce the term of execution to fetch the cache memory of the number of times of code from mass storage.I/O or I/O equipment 504 (including but not limited to keyboard, display, guidance device etc.) directly or by I/O controller between two parties can be couple to system.Network adapter also can be couple to system, makes computing system 500 can be couple to other data handling system, as by host system interface 512, or is couple to remote printer or memory device by special or public network between two parties.Some network adapter in the various network adapter that modulator-demodular unit, cable modem and Ethernet card are just available at present.
Claims (10)
1. a memory controller (104), the feature of described memory controller is to comprise:
Operatively can be couple to memory device (110 communicatedly; 111; 112) interface (301);
Processor (502), operatively can detect at the hardware protocol of memory device and select between the firmware protocols detection of memory device, with when memory device communication be couple to described interface time according to the protocol detection selected to detect the agreement of memory device, and process the input/output request of from host (105) based on the agreement selection protocol of the memory device detected.
2. according to memory controller according to claim 1, wherein:
Processor operatively substantially side by side can also carry out serial connecting small computer system interface protocol and detect and quick external component interconnected protocol detection.
3., according to memory controller according to claim 1, also comprise:
The hardware checker of hardware protocol detection operatively can be carried out by measuring time-domain reflector signal.
4. according to memory controller according to claim 3, wherein:
According to time-domain reflector signal, hardware checker operatively can also determine that memory device disconnects from interface.
5. according to memory controller according to claim 3, wherein:
Processor can also operatively be sampled to time-domain reflector signal, determines the slope of the time-domain reflector signal of sampling, and determines the agreement of memory device according to the slope of the time-domain reflector signal of sampling.
6. the method that can operate in memory controller, the feature of described method is to comprise:
Memory controller is couple to communicatedly memory device (201);
Detect at the hardware protocol of memory device and carry out selecting (202) between the firmware protocols detection of memory device;
When memory device communication be couple to interface time, detect the agreement (203) of memory device according to the protocol detection selected; With
Based on the agreement of the memory device detected, selection protocol processes the input/output request (204) of from host.
7. in accordance with the method for claim 6, also comprise:
Substantially side by side carry out serial connecting small computer system interface protocol to detect and quick external component interconnected protocol detection.
8. in accordance with the method for claim 6, also comprise:
Measure time-domain reflector signal, to carry out hardware protocol detection.
9. in accordance with the method for claim 8, also comprise:
According to time-domain reflector signal, determine that memory device disconnects from interface.
10. in accordance with the method for claim 8, also comprise:
Time-domain reflector signal is sampled;
Determine the slope of the time-domain reflector signal of sampling; With
According to the slope of the time-domain reflector signal of sampling, determine the agreement of memory device.
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| CN111142783A (en) * | 2018-11-05 | 2020-05-12 | 三星电子株式会社 | Storage device for self-adaptive supporting multiple protocols |
| CN111338993A (en) * | 2018-12-19 | 2020-06-26 | 佛山市顺德区顺达电脑厂有限公司 | Hard disk control system |
| WO2022126341A1 (en) * | 2020-12-14 | 2022-06-23 | 华为技术有限公司 | Communication system, link training method, and related device |
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| CN111338993B (en) * | 2018-12-19 | 2022-12-27 | 佛山市顺德区顺达电脑厂有限公司 | Hard disk control system |
| WO2022126341A1 (en) * | 2020-12-14 | 2022-06-23 | 华为技术有限公司 | Communication system, link training method, and related device |
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