CN105301913B - High-resolution photolithography method and structure are carried with the mask of two states - Google Patents
High-resolution photolithography method and structure are carried with the mask of two states Download PDFInfo
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Abstract
Photoetching process in etching system includes loading mask, and the mask includes limiting two kinds of mask states of integrated circuit (IC) pattern.IC patterns include multiple major polygonals, wherein, adjacent major polygonal is distributed to different mask states；And multiple Subresolution polygons in another in the field and two kinds of mask states in a kind of in background, including two kinds of mask states.The photoetching process also includes configuration luminaire to produce lighting pattern on the illumination iris face of etching system；Using the filter pattern determined according to lighting pattern iris filter is configured on the projection pupil face of etching system；And exposure technology is implemented to target using luminaire, mask and iris filter.Diffraction light and non-diffracted light are produced behind mask for exposure technology and iris filter removes most non-diffracted light.The invention further relates to carry high-resolution photolithography method and structure with the mask of two states.
Description
The cross reference of related application
The application is entitled " extreme ultraviolet light carving technology and the mask (Extreme submitted on April 2nd, 2012
Ultraviolet Lithography Process and Mask) " the 13/437th, No. 099 application part continuation application,
Entire contents are hereby expressly incorporated by reference by reference.
Technical field
The present invention relates to carry high-resolution photolithography method and structure with the mask of two states.
Background technology
Semiconductor integrated circuit (IC) industry experienced exponential growth.The technological progress of IC materials and design aspect is produced
Number is for IC, wherein often all having smaller and more complicated circuit than previous generation IC for IC.In IC evolutions, functional density
(that is, the quantity of interconnection devices on per chip area) have generally increased and physical dimension (that is, can be made using manufacturing process
Minimal parts (or line)) but reduce.This scaled technique is generally by improving production efficiency and reduction relevant cost
And bring benefit.This scaled technique also increases the complexity of IC processing and production.In order to realize that these improve, need
Will IC process and production in terms of same development.For example, the increase in demand to implementing higher resolution photoetching process.Various light
Lithography includes phase shifting mask and off-axis illumination.But prior art has the limitation for each needing to overcome, such as shadowing effect.
Therefore, although existing photoetching technique is typically enough for their expected purposes, but they are not
It is entirely satisfactory at each aspect.
The content of the invention
In order to solve the problems of the prior art, the invention provides the photoetching process in a kind of etching system, including：Plus
Mask is carried, the mask includes limiting two kinds of mask states of integrated circuit (IC) pattern, wherein, the IC patterns include：It is many
Individual major polygonal, wherein, adjacent major polygonal is distributed to different mask states；And background, it is included in a variety of cover
A kind of field in mould state and multiple Subresolution polygons in another in described two mask states；Configuration
Luminaire on the illumination iris face of the etching system to produce lighting pattern；Utilize the mistake determined according to the lighting pattern
Filter pattern configures iris filter on the projection pupil face of the etching system；And utilize the luminaire, the mask
With the iris filter to target implement exposure technology, wherein, the exposure technology is produced behind the mask diffraction light with
The major part of non-diffracted light and the iris filter removal non-diffracted light.
In above-mentioned photoetching process, wherein, the lighting pattern, which corresponds on axle, to be illuminated.
In above-mentioned photoetching process, wherein, the lighting pattern corresponds to partial coherence illumination.
In above-mentioned photoetching process, wherein, the lighting pattern has lighting part σim, wherein, the σimLess than 0.3.
In above-mentioned photoetching process, wherein, the filter pattern is substantially complementary with the lighting pattern.
In above-mentioned photoetching process, wherein, the lighting pattern has lighting part σim；And the filter pattern has
Stop portions σpf, wherein, σpf≥σim。
In above-mentioned photoetching process, wherein, the first polygon, the second polygon and the background have each other not respectively
Same transmissivity.
In above-mentioned photoetching process, wherein, the first polygon, the second polygon and the background have each other not respectively
Same transmissivity；Wherein, the first mask state and the second mask state have transmissivity t1 and t2；The background has average saturating
Penetrate rate t3；And t1 is more than t3 and t2 is less than t3.
In above-mentioned photoetching process, wherein, the mask includes：Transparent substrates；And it is square on the transparent substrate
Into layers of absorbent material, wherein, pattern the layers of absorbent material and covered with limiting the first mask state and second different from each other
Mould state.
In above-mentioned photoetching process, wherein, the mask includes：Transparent substrates；And it is square on the transparent substrate
Into layers of absorbent material, wherein, pattern the layers of absorbent material and covered with limiting the first mask state and second different from each other
Mould state；Wherein, the layers of absorbent material includes chromium.
According to another aspect of the present invention there is provided a kind of mask, including：Substrate；And layers of absorbent material, formed
The top of the substrate, wherein, the layers of absorbent material is patterned as including two kinds of mask states, described two mask states
Integrated circuit (IC) pattern with multiple major polygonals and background is defined, adjacent major polygonal is allocated to difference
Mask state, and the background is included in a kind of field in described two mask states and in described two mask shapes
Multiple Subresolution polygons in another in state.
In aforementioned mask, wherein, the Subresolution polygon includes the pattern density after adjustment, so that in photoetching work
The imaging contrast of the major polygonal is improved during skill.
In aforementioned mask, wherein, the Subresolution polygonal design into selected from by rectangle, square and they
Combination composition group in shape.
In aforementioned mask, wherein, the substrate includes transparent material.
In aforementioned mask, wherein, the substrate includes transparent material；Wherein, the substrate includes vitreous silica；And
The layers of absorbent material includes chromium.
In aforementioned mask, wherein, the substrate includes transparent material；Wherein, the layers of absorbent material include be selected from by
Chromium, chromium oxide, chromium nitride, nitrogen oxidation chromium, titanium, titanium oxide, titanium nitride, titanium oxynitrides, tantalum, tantalum oxide, tantalum nitride, nitrogen oxidation
Material in the group that tantalum, Solder for Al-Cu Joint Welding, aluminum oxide, palladium, molybdenum, molybdenum silicon and combinations thereof are constituted.
According to a further aspect of the invention there is provided a kind of method for producing mask, including：Receive with multiple main
Polygon and the integrated circuit of background (IC) pattern；The multiple major polygonal is distributed to corresponding mask state, so that
Adjacent major polygonal is distributed to different mask states；And Subresolution polygon is added into the background.
In the above-mentioned methods, wherein, the Subresolution polygon is distributed to identical mask state and by residue
The background distribute to another mask state, another mask state and distribute it is polygonal to the Subresolution
Mask state is different.
In the above-mentioned methods, wherein, adding the Subresolution polygon and being included in add in the background has pattern
The Subresolution part of density, so as to adjust the average transmittance in the background with the photoetching process phase using the mask
Between improve the imaging contrast of the major polygonal.
In the above-mentioned methods, wherein, by the Subresolution polygonal design into rectangle, square and their group
At least one of conjunction shape.
In the above-mentioned methods, in addition to according to the IC patterns mask is formed, wherein, forming the mask includes：
It is square into layers of absorbent material on a transparent substrate；And pattern the layers of absorbent material to be limited to without the absorption material
The first mask state in the first area of the bed of material and in the second area including the layers of absorbent material and the transparent substrates
In the second mask state.
Brief description of the drawings
When reading in conjunction with the accompanying drawings, each side that the present invention may be better understood according to the following detailed description
Face.It is emphasized that the standard practices in industry, what various parts were not necessarily to scale and were merely illustrative
Purpose.In fact, in order to clearly discuss, the size of various parts can be arbitrarily increased or reduce.
Fig. 1 is the flow chart of the photoetching process constructed according to some embodiments.
Fig. 2 is the frame of the etching system for implementing Fig. 1 method and the mask arrangement according to some embodiments construction
Figure.
Fig. 3 is the top view of the mask constructed according to some embodiments.
Fig. 4 to Fig. 5 is the sectional view of the mask in each fabrication stage constructed according to some embodiments.
Fig. 6 is the perspective schematic view of the part Fig. 2 constructed according to some embodiments etching system.
Fig. 7 shows the schematic diagram for the lighting pattern that the method by Fig. 1 constructed according to some embodiments is implemented.
Fig. 8 shows the schematic diagram for the filter pattern that the method by Fig. 1 constructed according to some embodiments is implemented.
Fig. 9 A are the top views of the mask constructed according to some embodiments.
Fig. 9 B are the schematic diagrames of exposure energy in the gray level distribution related to Fig. 9 A mask.
Fig. 9 C are the schematic diagrames of the exposure energy distribution in the figure related to Fig. 9 A mask.
Figure 10 A are the top views of the mask constructed according to some embodiments.
Figure 10 B are the schematic diagrames of exposure energy in the gray level distribution related to Figure 10 A mask.
Figure 10 C are the schematic diagrames of the exposure energy distribution in the figure related to Figure 10 A mask.
Figure 11 A are the top views of the mask constructed according to some embodiments.
Figure 11 B are the schematic diagrames of exposure energy in the gray level distribution related to Figure 11 A mask.
Figure 11 C are the schematic diagrames of the exposure energy distribution in the figure along the X direction related to Figure 11 A mask.
Figure 11 D are the schematic diagrames of the exposure energy distribution in the figure along the Y direction related to Figure 11 A mask.
Figure 12 A and 12B show the numerical aperture from the mask constructed according to some embodiments and the schematic diagram of diffraction light.
Figure 13 is the flow chart for the method that fabrication mask is configured to according to some embodiments.
Embodiment
In order to implement the different characteristic of the present invention, disclosure below provides many different embodiments or example.With
The particular example of lower description part and arrangement is of the invention to simplify.Certainly these are only that example is not intended to restriction.For example, with
In lower description first component formation above second component or on may include side of wherein the first and second parts directly to contact
The embodiment of formula formation, and wherein extra part formation is may also comprise between the first and second parts so that the first He
The embodiment that second component is not directly contacted with.In addition, the present invention can repeat reference number and/or letter in various embodiments.Should
Repetition is and the pass itself being not specified by between the various embodiments and/or structure for purpose of brevity and clarity
System.
Furthermore it is possible to " following " used herein, " ... under ", " bottom ", " ... on ", " top " etc.
Relative space position term the element or part that are shown in accompanying drawing and another (some) member are described in order to specification
The relation of part or part.In addition to the orientation shown in figure, relative space position term is intended to cover device in use or grasped
Different azimuth in work.If for example, the device in flipchart, be described as in other devices or part " under " or " below "
Element can then be positioned in other elements or part " on ".Therefore, exemplary term " ... under " can cover on
Two kinds of orientation with.Device can orient (be rotated by 90 ° or at other orientations) and sky used herein at other orientations
Between relative descriptors correspondingly can explain in the same way.
Fig. 1 is the flow chart of method 10 to implement according to the integrated of many aspects construction of the invention in each embodiment
Photoetching process in circuit manufacture.Reference picture 1 and other figures describe method 10, the etching system and mask implemented by method 10.
Reference picture 1, method 10 includes the photomask (mask or reticle mask) 36 with two kinds of mask states being loaded onto
The operation 12 of etching system 30.In the present invention, mask 36 is designed to the mask shape each with transmissivity different from each other
State.Etching system 30 and mask 36 described separately below.
According to some embodiments, figure 2 illustrates etching system 30 in schematic form.Etching system 30 is designed
Paired radiation sensitive material layer (for example, photoresist layer or photoresist layer) implements photolithographic exposure technique.Grasped with appropriate exposure mode
Make etching system 30.In certain embodiments, exposure mode is implemented, to cause the image of mask to pass through once irradiating (shot) shape
Into on integrated circuit (IC) substrate.In certain embodiments, stepping and exposure mode are implemented, to cause the image of mask repeatedly
Ground is formed in multiple field areas on IC substrates.In certain embodiments, stepping and scan pattern are implemented, to cause mask volume
Image is repeatedly scanned multiple field areas to IC substrates.
Etching system 30 is using radiation source 32 to produce emittance, such as ultraviolet (UV) light.In various embodiments, spoke
The source of penetrating can include UV sources or depth UV (DUV) source.For example, radiation source 32 can be with 436nm (G- lines) or 365nm (I-
Line) wavelength mercury lamp；KrF (KrF) excimer laser with 248nm wavelength；Argon fluoride with 193nm wavelength
(ArF) excimer laser；Or with the other light sources for expecting wavelength.
In some other embodiments, radiation source 32 includes the fluorine (F with 157nm wavelength2) excimer laser or tool
There is pole UV (EUV) source of the wavelength in the range of about 1nm and about 100nm.In a particular instance, EUV radiation source 32 produces ripple
The long EUV light for concentrating on about 13.5nm.
Etching system 30 also includes optical subsystem, and it receives emittance from radiation source 32, adjusted by the image of mask
Section emittance and the photoresist layer that will be coated on emittance guiding IC substrates.Optical subsystem includes luminaire and projection
Optical box (POB).In certain embodiments, optical subsystem is designed to refraction means.In this case, optics
System includes various refractive components, such as lens.
Emittance comes from F wherein2In some other embodiments of excimer laser or EUV radiation source, by optics
Subsystem is designed to reflecting mechanism.In this case, optical subsystem includes various reflection parts, such as speculum.
Especially, etching system 30 uses luminaire (such as concentrator) 34.Optical subsystem has refraction machine wherein
In some embodiments of structure, luminaire 34 can include single lens or lens module (zone plate) with multiple lens and/
Or other lenticular units.For example, luminaire 34 can include microlens array, shadow mask, and/or be designed to contribute to from spoke
The emittance for penetrating source 32 is directed to other structures on mask (also referred to as mask or reticle mask) 36.
Operable luminaire 32 illuminates (ONI) to provide on the axle for being used for irradiating mask 36, wherein as then further retouched
State, ONI is designed according to various aspects of the invention.In certain embodiments, configuration illumination aperture is illuminated with providing on axle.
In some embodiments, luminaire 34 is including adjustable to reconfigure so that radiant light to be redirected to many of different lighting positions
Individual lens, so as to realize ONI.In some other embodiments, the workbench before luminaire 34 can extraly include controllable
System is with the other lens or other optical components by the different lighting position of light directing is radiated, so as to realize ONI.
In wherein optical subsystem has some other embodiments of reflecting mechanism, for the light guide in autoradiolysis in future source
To mask, luminaire 34 can use single speculum or the mirror system with multiple speculums, so as to realize ONI.
Operable luminaire as to mask by mirror arrangement to provide ONI.In some instances, the speculum of luminaire it is switchable with
EUV light is reflexed to different lighting positions.In another embodiment, the workbench before luminaire 34 extraly includes controllable
Make with together with the reflective mirror with luminaire by other switchable speculums of the different lighting positions of EUV light directings.Therefore, photoetching
System can realize on axle illumination and without sacrificing illumination energy.
Etching system 30 also includes being configured to covering by suitable clamping mechanism (such as vacuum clip or electrostatic chuck) fixation
The mask platform 35 of mould 36.According to some embodiments, mask platform 35 is designed and configured as can be used to translational and rotational movement.
Mask 36 can be transmission mask or reflection mask.In the present embodiment, mask 36 is such as then further detailed
The transmission mask carefully described.Etching system 30 is also using POB38 for the pattern of mask 36 is imaged to being fixed on photoetching system
On target 40 (such as semiconductor crystal wafer or only the IC substrates of wafer) on the substrate table 42 of system 30.Optical subsystem wherein
In some embodiments with refraction means, POB38 has diffractive optical devices.POB38 collects the radiation launched from mask 36
Light.In one embodiment, POB38 can be including the magnifying power less than 1 (so as to reduce the figure for the patterning that radiation includes
Picture).
In optical subsystem has some other embodiments of reflecting mechanism, POB38 has diffractive optical devices.
POB38 collects the radiation (radiation of such as patterning) reflected from mask 36.
Mask 36 is returned, mask 36 includes two kinds of mask states different from each other for transmissivity.Specifically, two
Plant mask state has transmissivity t1 and t2 respectively, and has optical phase (simple phase) respectivelyWith
In certain embodiments, the phase difference of two kinds of mask states is the about 180 degree in particular range.Both mask shapes
State is considered as out-phase.In this description of the certain limit inner evaluation of reasonable selection, such as 15 degree.For example, when phase difference is special
When determining the 180 degree in scope, such as 180 ± 15 degree, both mask states are considered as out-phase.In addition, in some embodiments
In, the first polygon is limited in the first mask state, and restriction is adjacent with the first polygon in the second mask state
Second polygon.Background refers to the region without major polygonal (circuit block or pseudo- part).However, background is limited to two kinds
In the one of which of mask state, merge with the Subresolution part of another mask state.Subresolution part is corresponding
Non- printable part during lithographic patterning.On the contrary, major polygonal can print during lithographic patterning.
As shown in Fig. 3 of the top view as the mask 36 constructed according to some embodiments.Mask 36 is designed as having
Two kinds of mask states S1 and S2 different from each other for transmissivity.In certain embodiments, the first mask state S1 and second
Mask state S2 is different and different from each other with t2 due to transmissivity t1.In another embodiment, the first mask state S1 and second
Mask state S2 is out-phase.
Pattern mask 36 is to limit IC layout patterns (or only IC patterns).IC patterns include multiple major polygonals,
Such as 52 and 54.Mask 36 is patterned with including two kinds of mask states, so as to limit IC patterns on mask 36.In particular,
Adjacent major polygonal is distributed to corresponding mask state.For example, major polygonal 52 is distributed to the first mask state
(being limited in the first mask state) S1 and the major polygonal 54 adjacent with major polygonal 52 is distributed to the second mask
State (is limited in the second mask state) S2.Mask 36 also includes background 56.Background includes the area without major polygonal
Domain.Background 56 includes field 58 and multiple Subresolution subpolygons 60.It is many without major polygonal and Subresolution auxiliary
The region of side shape is referred to as field.In the present embodiment, field 58 is distributed to the first mask state S1, and Subresolution is aided in
Polygon 60 is distributed to the second state S2.In an alternate embodiment of the invention, field 58 is distributed to the second mask state S2, and by Asia
Resolution ratio subpolygon 60 is distributed to the first mask state S1.
Subresolution subpolygon 60 is to be sized to print during photoetching process to target (such as semiconductor
Wafer) on polygon.Therefore, background 56 is imaged to photoresist layer to reach with average transmittance during photoetching process
T3 (being different from t1 and t2) substantially uniform gray level.Subresolution subpolygon 60 can be changed into background 56
In there is specific pattern density so as to according to expecting to adjust corresponding transmissivity t3.In certain embodiments, by Subresolution
Subpolygon 60 is designed to have specific pattern density in background 56 to adjust corresponding transmissivity t3 with photoetching
The imaging contrast of major polygonal is improved during technique.Therefore, mask 36 has two kinds of mask states but realized with regard to transmissivity
Three kinds of area types different from each other for (or average transmittance), therefore referred to as three kinds mask tones (three kinds of tones).Especially
Ground, three kinds of mask tones include the first mask state, the second mask state and background, and background has and the first and second mask shapes
The different average transmittance of the average transmittance of state.Mask 36 has two kinds of mask states but with three kinds of mask tones.One
In a little embodiments, according to identical mechanism, mask 36 can be designed as including two kinds of mask states and the mask more than three kinds
Tone.For example, in the background, Subresolution subpolygon 60 is changed into corresponding local pattern density, so as to realize big
In three kinds of mask tone.
Subresolution subpolygon 60 can include rectangle, square or other suitable geometries.For example, for
Identical rectangular with width W (size of the short side of rectangle) it is regularly arranged, if w<λ/NA, then those subpolygons exist
It will not be printed on target 40 during photoetching process.
When method 10 is used together, having two kinds of mask states but with three kinds of mask tones with etching system 30
Mask 36 be designed as realizing enhanced illumination resolution ratio and the depth of field (DOF).The structure and its manufacture method of mask 36 will be under
Text is further described according to some embodiments.
Mask-making technology includes two steps：Blank mask manufacturing process and mask patterning technique.In blank mask
During manufacturing process, by depositing suitable layer (for example, multiple reflecting layer and absorbed layer) formation blank on a suitable substrate
Mask.By the design of the patterned layer with integrated circuit of blank mask during mask patterning technique.Then using figure
The mask of case is so that circuit pattern (IC patterns) is transferred on semiconductor crystal wafer.Can be anti-by pattern by various photoetching processes
It is transferred to again on multiple wafers.One group of mask (for example, one group of 15 to 30 mask) can be used to construct complete IC.
Fig. 4 to Fig. 5 shows the sectional view of the mask 36 in each fabrication stage constructed according to some embodiments.Fig. 4
In the fabrication mask stage of the mask 36 that shows before patterning be blank.Mask 36 is included by the radiation to radiation source 32
The mask substrate 70 that the transparent material of light is made.In some instances, transparent substrates 70 include vitreous silica or other suitable
Material, such as relatively flawless borosilicate glass and soda-lime glass.
Mask 36 is additionally included in the layers of absorbent material 72 that the top of substrate 70 is formed.Layers of absorbent material 72 is absorbed from radiation source 32
It is projected to the radiant light on mask 36.In certain embodiments, design layers of absorbent material 72, which makes it have, substantially absorbs radiation
The composition and thickness of light.In the present embodiment, layers of absorbent material 72 includes chromium (Cr), or other suitable materials.
In some other embodiments, layers of absorbent material include chromium, chromium oxide, chromium nitride, nitrogen oxidation chromium, titanium, titanium oxide,
Titanium nitride, titanium oxynitrides, tantalum, tantalum oxide, tantalum nitride, nitrogen tantalum oxide, Solder for Al-Cu Joint Welding, aluminum oxide, palladium, molybdenum, molybdenum silicon or their group
Close.
Can be by various methods formation layers of absorbent material 72, including such as evaporate and sunk with the physical vapors of DC magnetron sputterings
Product (PVD) technique, such as depositing process of such as electrodeless plating or plating, atmospheric pressure CVD (APCVD), low pressure chemical vapor deposition
(LPCVD), plasma enhanced CVD (PECVD) or the chemical vapor deposition of high-density plasma CVD (HDP CVD)
(CVD), ion beam depositing, spin coating, metal organic decomposition (MOD) and/or other methods well known in the art.MOD is using non-
The deposition technique of the method based on liquid in vacuum environment.By using MOD, the metallorganic precursors in solvent are dissolved in
It is spin-coated on substrate and evaporates solvent.VUV (VUV) source is used for the metal that metallorganic precursors are changed into composition
Element.
Then, according to including the polygonal IC patterns of Subresolution, patterning layers of absorbent material 72 has three kinds to limit
Two kinds of mask states of mask tone.In particular, three kinds of mask tones limit all parts of the IC patterns on mask 36 respectively.
The patterning of layers of absorbent material 72 can be implemented by the process including photoetching process and etching.Pattern is described referring to Fig. 5
One embodiment of chemical industry sequence.
Reference picture 5, to layers of absorbent material 72 apply patterning step with formed on mask 36 first mask state S1 and
Second mask state S2.Patterning step includes photoetching process and etch process.Photoetching process can also include photoresist coating
(for example, spin coating), soft baking, mask registration, exposure, postexposure bake, lithographic glue, rinsing, drying are (for example, hard dry
It is roasting), other suitable techniques, and/or combinations thereof.In the present embodiment, exposure uses electron beam technology.Alternatively, lead to
Cross other suitable methods and implement or substitute exposure technology, such as maskless lithography or ion beam write-in.Photoetching process formation tool
There is the photoresist layer of the patterning for the opening for limiting the region for the first mask state S1.
Then be etched technique partially absorbs material layer 72 to remove, and is covered so as to form the first mask state S1 and second
Mould state S2.Etch process can include dry (plasma) etching, wet etching, and/or other engraving methods.In some implementations
In example, using plasma etch process optionally to remove layers of absorbent material 72 by chlorine-based gas.The photoetching of patterning
Glue-line is used as etching mask during etch process, so that only remove the photoresist layer for being located at patterning of layers of absorbent material 72
Part in opening.
Therefore, as shown in figure 3, patterning layers of absorbent material 72 to form IC patterns.In particular, mask 36 is patterned to
Including two kinds of mask states and three kinds of mask tones, so that adjacent major polygonal is each defined in the first mask state
In S1 and the second mask state S2.Background 56 is patterned to including field 58 and Subresolution subpolygon 60.Background 58 is limited
It is scheduled in the 3rd mask tone different from the mask tone of the first and second mask states.
Referring now still to Fig. 3, mask 36 includes two kinds of mask states S1 and S2 with respective transmissivity t1 and t2.At some
In embodiment, t1 absolute value is more than t2 absolute value.In the present embodiment, t1 substantially near 1 and t2 substantially near
0.Subresolution subpolygon 60 is non-printable, obtains the background with quasi-homogeneous transmissivity t3, t3 absolute value
Between t1 and t2 absolute value.
Other steps can also be included by referring again to the operation 12 in Fig. 1, method 10, and mask 36 such as is fixed on into mask platform
Alignment after upper.
Referring still to Fig. 1, method 10 also includes operation 14, and target 40 is loaded onto to the substrate table 42 of etching system 30.At this
In embodiment, target 40 is Semiconductor substrate, such as Silicon Wafer.Target 40 is coated with the photoresist layer to radiating photaesthesia.Pass through light
Exposure technology patterning photoresist layer is carved to cause the IC patterns of mask 36 to be transferred to photoresist layer.
Reference picture 1, method 10 includes operation 16, to approach the illumination that light illumination mode on axle (ONI) sets etching system 30
Device 34.Configure light illumination mode to produce diffraction light and non-diffracted light with the partial ocoherence σ less than about 0.1.Reference picture 6, due to
The presence of these mask patterns, incident ray 80 is diffracted into the various orders of diffraction, such as the 0th order of diffraction after 36 reflections are masked
Light 82, the -1st order of diffraction light 84 and the+1st order of diffraction light 86.In the embodiments described, most of non-diffracted light
Line 82 is removed by iris filter 88.- 1st and the+1st order of diffraction light 84 and 86 is collected by POB38 and is directed to make target 40
Exposure.
Light illumination mode on axle can be realized by the mechanism constructed according to some embodiments, as with specific illumination pattern
Aperture (aperture), all CD lighting patterns 90 as shown in Figure 7.Lighting pattern 90 includes lighting part 92 and stop part
Divide 94.It is to realize light illumination mode on axle in illumination iris face by aperture configuration.However, aperture causes radiation loss.
In certain embodiments, luminaire 34 includes various switchable lens or with the other of other suitable mechanisms
Optical component is to adjust the transmissivity of the radiant light from these lens or other suitable optical components.Further, at this
In embodiment, light illumination mode on axle is realized by realizing switchable lens configuration in illumination platform to illuminate on axle.Pass through
The parameter σ assessed relative to NA (numerical aperture)im(it is the radius of lighting part 92) further limits lighting pattern 90.One
In a little embodiments, by parameter σimIt is chosen less than about 0.3.In certain embodiments, lighting pattern can be determined according to IC patterns
90。
Reference picture 1, method 10 can include operation 18, and iris filter is configured in etching system 30.Iris filter
Configuration is in the projection pupil face of etching system 30.Iris filter is placed in projection pupil face comes from mask 36 to filter out
Radiant light specific spatial frequency component.
The pattern for determining to limit in iris filter by light illumination mode.The pattern of design iris filter is come from removing
The non-diffracted light of at least a portion non-diffracted light of mask 36, such as at least about 70% (intensity), it is the 0 from mask 36
Order diffraction light.In certain embodiments, in iris filter pattern and the pattern of light illumination mode is substantially complementary.For example, working as
When lighting pattern 90 is defined to the CD pattern in Figure 12, the corresponding pattern of iris filter is as shown in Figure 8 similar but turned over
The pattern 100 (filter pattern 100) turned.Filter pattern 100 includes stop portions 102 (similar CD) and collects part 104.
Reaching the radiant light of the stop portions 102 in pupil plane will be blocked.The radiant light for reaching the collection part 104 in pupil plane will
Collected by POB38 and be directed to target 40.Filter pattern 100 is further by parameter σpfLimit, it is the half of stop portions 102
Footpath.σ is assessed herein in relation to NApf.In some instances, lighting pattern 90 has partial ocoherence σimCD less than about 0.3
Illumination.Filter pattern 100 is determined according to lighting pattern 90 so that being removed by iris filter 100 most of non-diffraction
Light, such as removes the non-diffracted light more than 70%, so that mainly using being symmetrical arranged (on pupil plane) from two and strong
Spend the diffraction light exposure semiconductor crystal wafer of the -1st and the+1st order of diffraction of balance.In some above-mentioned embodiments, lighting pattern 90
It is complementary with filter pattern 100, it is formulated as σpf=σim.In certain embodiments, filter pattern may be with lighting pattern slightly
Micro- difference, is formulated as σpf>σim.In a word, filter pattern is determined by lighting pattern, is formulated as σpf=>σim.
Wherein σimIn an example less than 0.3, σpf=it is more than 0.3.
Fig. 1 is referred again to, method 10 carries out to operation 20, target 40 is implemented in the light illumination mode and iris filter of configuration
Photolithographic exposure technique.Luminaire 34 adjusts the radiant light from radiation source 32 for the radiant energy distribution illuminated on axle,
The radiant light is oriented from mask 36, and is filtered by iris filter, and radiant light utilizes enhanced energy range (EL) and DOF
The IC patterns of mask 36 are imaged to target 40.
Fig. 1 is referred again to, method 10 can also include other operations.For example, method 10 includes the exposure for making to be coated on target 40
The operation 22 of the photoresist layer development of light, so as to form the photoresist layer of patterning, it has from the IC being limited on mask 36
One or more openings of pattern imaging.
In another example, method 10 also includes operation 24, and manufacture work is implemented to target 40 by the photoresist layer of patterning
Skill.In one embodiment, by the substrate or material layer of the opening etching target of the photoresist layer of patterning, so that by IC patterns
It is transferred to substrate or following material layer.In a further embodiment, material layer below is to set on a semiconductor substrate
Interlayer dielectric (ILD) layer.Etch process will form contact or through hole in corresponding ILD layer.In another embodiment, lead to
The opening for crossing the photoresist layer of patterning applies ion implantation technology to Semiconductor substrate, so as to be served as a contrast according to IC patterns in semiconductor
The part of doping is formed in bottom.In this case, the photoresist layer of patterning is used as ion implanting mask.
Method 10 and each embodiment of mask 36 are described according to the present invention.In the scope without departing substantially from the present invention
In the case of, other alternatives and modification may be present.In one embodiment, the IC patterns limited on mask 36 can also include
Various Fake polygons.In an example, Fake polygon similarly is distributed so that adjacent with the circuit polygons of IC patterns
Major polygonal (circuit polygon and Fake polygon) distribution to different mask states.In various embodiments, it is coated on
With the Other substrate materials for receiving photolithographic exposure technique can be positive-tone photoresist or negative tone photolithography glue on target.
In addition, mask 36 and method 10 can be used for being formed the various IC patterns with enhanced imaging effect.In Fig. 9 A
The first example is shown into Fig. 9 C.Fig. 9 A show the top view of the mask 36 according to some embodiments.Mark first respectively
Mask state S1, the second mask state S2 and the background 56 with the 3rd mask tone (such as the 3rd transmissivity t3).Fig. 9 B
Show that the corresponding exposure energy on the photoresist layer being in gray level is distributed.Fig. 9 C are showing along on photoresist layer in figure
Line AA ' corresponding exposure energy distribution, distance of the horizontal axis repre-sents along line AA ' in figure and vertical axis represents exposure energy.
The IC patterns limited on mask 36 include multiple line parts.Pass through the interval of method 10 clearly between imaging line and line.
The second example is shown in Figure 10 A to Figure 10 C.Figure 10 A show the top of the mask 36 according to some embodiments
View.Mark the first mask state S1, the second mask state S2 and the background 56 with the 3rd mask tone respectively.Figure 10 B
Show that the corresponding exposure energy on the photoresist layer being in gray level is distributed.Figure 10 C are showing along on photoresist layer in figure
Line AA ' the distribution of corresponding exposure energy, distance of the horizontal axis repre-sents along line AA ' in figure and vertical axis represents exposure energy
Amount.The IC patterns limited on mask 36 include the multiple hole portion parts (such as contact hole) being located in array.By method 10 to increase
Strong contrast clearly imaging hole part.
The 3rd example is shown in Figure 11 A to Figure 11 D.Figure 11 A show the top of the mask 36 according to some embodiments
View.Mark the first mask state S1, the second mask state S2 and the background 56 with the 3rd mask tone respectively.Figure 11 B
Show that the corresponding exposure energy on the photoresist layer being in gray level is distributed.Figure 11 C are showing along on photoresist layer in figure
Line AA ' the distribution of corresponding exposure energy and Figure 11 D the corresponding exposure energy of the line BB ' on photoresist layer is showing along in figure
Amount distribution.The IC patterns limited on mask 36 include a plurality of line of arrangement.Line in line/interval and Y-direction in X-direction is first
Tail is connected (end to end) all while realizing highest contrast.
In another embodiment, photoetching process includes forming the mask with two kinds of mask states and three kinds of mask tones,
By different mask state assignment to adjacent polygon and background, pass through the almost axle with the partial ocoherence σ less than 0.3
Upper illumination (ONI), to produce diffraction light and non-diffracted light, removes the non-diffracted light more than 70%, and pass through to make mask exposure
Diffraction light and the non-diffracted light not removed are collected and guided to projection optics case (POB) so that target 40 exposes.
Figure 13 shows the flow chart of the method 110 for producing the mask constructed according to some embodiments.Method 110 is opened
Start from and receive the 112 of IC patterns.IC patterns include circuit layout, and it has multiple circuit polygons by target is transferred to.
Method 110 can include operation 114, increase extra part (such as Fake polygon) to IC patterns.Puppet is polygon
Shape increases to IC patterns for one or more manufacture functions, such as pseudo- for chemically-mechanicapolish polishing the CMP of (CMP) uniformity
Polygon or the hot Fake polygon for thermal annealing uniformity.Circuit polygon and Fake polygon are referred to as major polygonal.
Method 110 includes operation 116, and each polygon is distributed to corresponding mask state.Especially, by adjacent master
Polygon is wanted to distribute to different mask states.For example, the first major polygonal is distributed to the first mask state S1 and will be with
The second adjacent major polygonal of first major polygonal is distributed to the second mask state S2.
Method 110 also includes operation 118, the background of increase Subresolution polygon to IC patterns.Can be by Subresolution
Subpolygon design growth rectangle, square, other suitable geometries or combinations thereof.Especially, by Asia resolution
Rate polygon distributes to identical mask state and distributes field to another mask state, and another mask state is with distributing extremely
The polygonal mask state of Subresolution is different.
In certain embodiments, field is distributed to the first mask state S1, and by Subresolution subpolygon distribute to
Second state S2.In some other embodiments, field is distributed to the second mask state S2, and by Subresolution subpolygon
Distribute to the first mask state S1.Therefore, background is imaged to photoresist layer during photoetching process and reached with different from t1
With t2 average transmittance t3 substantially uniform gray level.Subresolution subpolygon is designed to have in the background
Specific pattern density is so as to adjust corresponding transmissivity t3 to improve the imaging contrast of major polygonal during photoetching process.
Therefore, mask has two kinds of mask states but realizes the different from each other three kind mask tone for transmissivity.At some
Can be to include two kinds of mask states and the mask color more than three kinds by IC designs according to identical mechanism in embodiment
Adjust.For example, in the background, Subresolution subpolygon is changed into corresponding local pattern density, so as to realize more than three
The mask tone planted.
Method 110 can include operation 120, produce the tape-out data for limiting IC patterns.IC patterns include distributing to corresponding
Mask state major polygonal, a kind of distribution to Subresolution polygon of mask state and distribution are to another mask state
Field.
Method 110 can also include operation 122, and mask is formed according to tape-out data.In certain embodiments, the shape of mask
Into including as above in association with the deposition described in Fig. 3 to Fig. 5, e-beam lithography and etching.
According to each embodiment, the invention provides mask arrangement, the photoetching process and method of the mask are produced.Mask is limited
Surely have multiple major polygonals IC patterns and including two kinds of mask states still three kinds of mask tones.Will be adjacent main many
Side shape is distributed to different mask states.It is polygon to multiple Subresolutions of same mask state that the background of IC patterns includes distribution
Shape and distribution to the field of another mask state.Photoetching process uses illumination on mask and axle.Photoetching process using lighting pattern and
The iris filter designed according to lighting pattern.Producing the method for mask includes distributing various major polygonals to covering accordingly
Mould state is so that adjacent major polygonal is distributed to different mask states；And Subresolution polygon is added into the back of the body
Scape.
The embodiment provides relative to prior art advantage, it should be appreciated that, other embodiments can be carried
For different advantages, required for being not required to be discussed all advantages herein and being all embodiments without specific advantage.
Method 10 by off-axis illumination (OAI) can realize identical minimum spacing under the conditions of given NA.When using OAI, due to
The position of the 0th order of diffraction on pupil plane is fixed, once therefore spacing deviates optimal spacing, then DOF starts reduction.For P>
1.5X Pmin, DOF is almost minimum.Due in spacing range 1.5X Pmin~2X PminIn, implement accessory (AF) to increase
DOF is unhelpful.In the presence of forbidding pitch problems.By using method 10, DOF keeps maximum until second order of diffraction enters.Namely
Say, as shown in Figures 12 A and 12 B, in spacing range 1X Pmin~2X PminIn, DOF is maximum.In the absence of forbidding pitch problems.
+ 1st and the -1st order of diffraction strength balance, energy range is maximized.In addition, on pupil plane, due to the+1st and
- 1st order of diffraction is identical from a distance from pupil centre (as shown in Figure 6), therefore DOF is maximized simultaneously.
According to some embodiments, the invention provides the photoetching process in etching system.The photoetching process includes：Loading is covered
Mould, the mask includes limiting two kinds of mask states of integrated circuit (IC) pattern.IC patterns include multiple major polygonals, its
In, adjacent major polygonal is distributed to different mask states；And in one kind in background, including a variety of mask states
Field and two kinds of mask states in it is another in multiple Subresolution polygons.The photoetching process also includes illuminating on axle
Pattern configurations have the luminaire of etching system pattern；Using the filter pattern determined according to lighting pattern etching system throwing
Iris filter is configured on shadow pupil plane；And using mask, with the luminaire postponed and with the iris filter pair postponed
Target implements exposure technology.
According to some embodiments, present invention also offers a kind of mask.The mask includes substrate；And in the top of substrate
The layers of absorbent material of formation.Layers of absorbent material is patterned as including two kinds of mask states, and two kinds of mask states, which are limited, to be had
Multiple major polygonals and the integrated circuit of background (IC) pattern.Adjacent major polygonal is allocated to different mask shapes
State.Background is included in the field in a kind of in two kinds of mask states and multiple Asias in another in two kinds of mask states
Resolution ratio polygon.
According to some embodiments, the present invention also provides a kind of method for producing mask.This method includes receiving with multiple
Major polygonal and the integrated circuit of background (IC) pattern；Multiple major polygonals are distributed to corresponding mask state, so that
Adjacent major polygonal is distributed to different mask states；And Subresolution polygon is added into background.
The feature of some embodiments is discussed above so that the present invention may be better understood in those of ordinary skill in the art
Various aspects.It will be understood by those skilled in the art that they easily can set using based on the present invention
Count or change for implementing identical purpose with embodiments described herein and/or realizing the other techniques and knot of same advantage
Structure.Those of ordinary skill in the art it should also be appreciated that this equivalent constructions are without departing from the spirit and scope of the present invention, and
Without departing from the spirit and scope of the present invention, a variety of changes can be made to the present invention, replaces and changes.
Claims (21)
1. the photoetching process in a kind of etching system, including：
Mask is loaded, the mask includes limiting two kinds of mask states of integrated circuit (IC) pattern, wherein, the integrated circuit
Pattern includes：
Multiple major polygonals, wherein, adjacent major polygonal is distributed to two kinds of different mask tones, it is described two not
Same mask tone is formed by described two mask states respectively；With
Background, is included in many in the field in a kind of in two kinds of mask states and another in described two mask states
Individual Subresolution polygon, so that the background has the three color scheme formed by described two mask combinations of states；
Luminaire is configured to produce lighting pattern on the illumination iris face of the etching system；
Pupil filter is configured on the projection pupil face of the etching system using the filter pattern determined according to the lighting pattern
Ripple device；And
Exposure technology is implemented to target using the luminaire, the mask and the iris filter, wherein, the exposure technology
Diffraction light and non-diffracted light are produced behind the mask and the iris filter removes the major part of the non-diffracted light.
2. the photoetching process in etching system according to claim 1, wherein, the lighting pattern, which corresponds to axle, to be photograph well
It is bright.
3. the photoetching process in etching system according to claim 1, wherein, the lighting pattern corresponds to partially coherent
Illumination.
4. the photoetching process in etching system according to claim 1, wherein, the lighting pattern has lighting part
σim, wherein, the σimLess than 0.3.
5. the photoetching process in etching system according to claim 1, wherein, the filter pattern and the lighting pattern
It is complementary.
6. the photoetching process in etching system according to claim 1, wherein,
The lighting pattern has lighting part σim；And
The filter pattern has stop portions σpf, wherein, σpf≥σim。
7. the photoetching process in etching system according to claim 1, wherein, the first polygon, the second polygon and
The background has transmissivity different from each other respectively.
8. the photoetching process in etching system according to claim 7, wherein,
First mask state and the second mask state have transmissivity t1 and t2；
The background has average transmittance t3；And
T1 is more than t3 and t2 is less than t3.
9. the photoetching process in etching system according to claim 1, wherein, the mask includes：
Transparent substrates；And
On the transparent substrate it is square into layers of absorbent material, wherein, the layers of absorbent material is patterned to limit each other not
Same the first mask state and the second mask state.
10. the photoetching process in etching system according to claim 9, wherein, the layers of absorbent material includes chromium.
11. a kind of mask, including：
Substrate；And
Layers of absorbent material, is formed in the top of the substrate, wherein,
The layers of absorbent material is patterned as including two kinds of mask states, and described two mask states are defined with multiple masters
Polygon and the integrated circuit of background (IC) pattern are wanted,
Adjacent major polygonal is allocated to two kinds of different mask tones, and described two different mask tones are respectively by institute
Two kinds of mask states are stated to be formed, and
The background is included in a kind of field in described two mask states and another in described two mask states
Multiple Subresolution polygons in kind, so that the background has the 3rd color formed by described two mask combinations of states
Adjust.
12. mask according to claim 11, wherein, the Subresolution polygon includes the pattern density after adjustment,
So as to improve the imaging contrast of the major polygonal during photoetching process.
13. mask according to claim 11, wherein, the Subresolution polygonal design into selected from by rectangle,
Shape in the group that square and combinations thereof are constituted.
14. mask according to claim 11, wherein, the substrate includes transparent material.
15. mask according to claim 14, wherein,
The substrate includes vitreous silica；And
The layers of absorbent material includes chromium.
16. mask according to claim 14, wherein, the layers of absorbent material includes being selected from by chromium, chromium oxide, nitridation
Chromium, nitrogen oxidation chromium, titanium, titanium oxide, titanium nitride, titanium oxynitrides, tantalum, tantalum oxide, tantalum nitride, nitrogen tantalum oxide, Solder for Al-Cu Joint Welding, aluminum oxide,
Material in the group that palladium, molybdenum, molybdenum silicon and combinations thereof are constituted.
17. a kind of method for producing mask, including：
Receive integrated circuit (IC) pattern with multiple major polygonals and background；
The corresponding mask state that the multiple major polygonal is distributed into two kinds of mask states, so that will be adjacent main
Polygon is distributed to two kinds of different mask tones, and described two different mask tones are respectively by described two mask state shapes
Into；And
Subresolution polygon is added into the background, formed so that the background has by described two mask combinations of states
Three color scheme.
18. the method according to claim 17 for producing mask, wherein, the Subresolution polygon is distributed to identical
Mask state and the remaining background is distributed to another mask state, another mask state with distribution extremely
The polygonal mask state of Subresolution is different.
19. the method according to claim 17 for producing mask, wherein, add the Subresolution polygon and be included in institute
State and the Subresolution part with pattern density is added in background, so as to adjust the average transmittance in the background utilizing
The imaging contrast of the major polygonal is improved during the photoetching process of the mask.
20. it is according to claim 17 produce mask method, wherein, by the Subresolution polygonal design into
At least one of rectangle, square and combinations thereof shape.
21. the method according to claim 17 for producing mask, in addition to according to forming the integrated circuit patterns
Mask, wherein, forming the mask includes：
It is square into layers of absorbent material on a transparent substrate；And
The first mask shape that the layers of absorbent material is patterned to be limited in the first area for not having the layers of absorbent material
State and the second mask state in the second area including the layers of absorbent material and the transparent substrates.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/298,589 | 2014-06-06 | ||
| US14/298,589 US9417534B2 (en) | 2012-04-02 | 2014-06-06 | Lithography method and structure for resolution enhancement with a two-state mask |
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| CN105301913B true CN105301913B (en) | 2017-11-03 |
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| DE102018201457A1 (en) * | 2018-01-31 | 2019-08-01 | Carl Zeiss Smt Gmbh | Illumination optics for projection lithography |
| CN111045289B (en) * | 2019-12-06 | 2021-07-06 | 中国科学院上海光学精密机械研究所 | Extreme ultraviolet lithography mask shadow effect compensation method |
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| US4947413A (en) * | 1988-07-26 | 1990-08-07 | At&T Bell Laboratories | Resolution doubling lithography technique |
| JPH0764273A (en) * | 1993-08-27 | 1995-03-10 | Sony Corp | Phase shift mask |
| US6519760B2 (en) * | 2001-02-28 | 2003-02-11 | Asml Masktools, B.V. | Method and apparatus for minimizing optical proximity effects |
| US20070121090A1 (en) * | 2005-11-30 | 2007-05-31 | Asml Netherlands B.V. | Lithographic apparatus and device manufacturing method |
| NL2003696A (en) | 2008-11-10 | 2010-05-11 | Brion Tech Inc | Scanner model representation with transmission cross coefficients. |
| US8524423B2 (en) * | 2011-07-11 | 2013-09-03 | United Microelectronics Corp. | Method of forming assist feature patterns |
| US8841047B2 (en) * | 2012-04-02 | 2014-09-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Extreme ultraviolet lithography process and mask |
| TWI463250B (en) * | 2012-07-18 | 2014-12-01 | Unimicron Technology Corp | Gray-tone mask, manufacturing method thereof and method of forming trench on substrate by using the same |
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| KR101788377B1 (en) | 2017-10-19 |
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