CN105262477B - A kind of S4R logic control circuits and its logic control implementation method - Google Patents

A kind of S4R logic control circuits and its logic control implementation method Download PDF

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Publication number
CN105262477B
CN105262477B CN201510820843.0A CN201510820843A CN105262477B CN 105262477 B CN105262477 B CN 105262477B CN 201510820843 A CN201510820843 A CN 201510820843A CN 105262477 B CN105262477 B CN 105262477B
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gate
charging
logic control
signal
drive signal
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CN105262477A (en
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王新征
徐泽锋
丁宁
丁一宁
郑磊
宋楠
瞿诗霞
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Shanghai Institute of Space Power Sources
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Shanghai Institute of Space Power Sources
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Abstract

The present invention relates to a kind of S4R logic control circuits and its logic control implementation method, make the input of logic control circuit adjust bus control signal FG1 and charging control signal FG2 to be connected with complete respectively, after logical operation, realize G1=FG1＆FG2, G2=FG2+（^FG1）, shunting the drive signal G1 and S of the output end output of logic control circuit4R shunting drive circuits are connected, and the charging drive signal G2 of output is connected with charging drive circuit, realizes logic control.The logic control realization principle topology of the present invention is easily understood, and Project Realization is easy, has important engineering application value to satellite sun battle array regulation technology.

Description

A kind of S4R logic control circuits and its logic control implementation method
Technical field
The invention belongs to sun battle array adjustment control technical field, more particularly to a kind of S4R(Series Sequential Switching Shunt Regulator, tandem type sequence switch parallel regulator) logic control circuit and its logic control be real Existing method.
Background technology
On general satellite, the regulation of sun battle array uses S4R controls to adjust circuit.Such as CN201310108239 discloses one Kind S4R type power controls, the device include：Shunting circuit, circuit for generating triangular wave, logic control circuit, charging Control circuit, charge switch pipe, diverting switch pipe etc..It realizes logic control method, this method by comparator, triode etc. The conversion of logic level is carried out by the conducting and shut-off of triode, realizes S4R control logic.But the logic control method needs Want device relatively more, realize multichannel S4Advantage unobvious in R circuits.
The content of the invention
It is an object of the invention to provide a kind of circuit topological structure is simple, it is easy to the S of Project Realization4R logic controls electricity Road and its logic control implementation method.
In order to reach above-mentioned purpose, of the invention technical scheme is to provide a kind of S4R logic control circuits, it is wrapped Contain：
Four nor gates, it each has two inputs and an output end；
Wherein, bus control signal FG1 is adjusted to be connected to two inputs of the first nor gate entirely；
The signal P1 of the output end of first nor gate is respectively connecting to the first input end and the 3rd or non-of the second nor gate The first input end of door；
Charging control signal FG2 is connected to the second input of the 3rd nor gate；
The signal P2 of the output end of 3rd nor gate is respectively connecting to the second input of the second nor gate, four nor gate Two inputs；
The output end output steering drive signal G1 of second nor gate；
The output end output charging drive signal G2 of four nor gate；
Wherein, G1=^ (P1+P2)=(^P1) ＆ (^P2)=(FG1) ＆ (^FG1+FG2)=(FG1) ＆ (FG2)；
G2=^P2=P1+FG2=FG2+^FG1.
Another technical scheme of the present invention is to provide a kind of S4R logic control circuits, it is included：
Three NAND gates, it each has two inputs and an output end；
Wherein, bus control signal FG1 is adjusted to be respectively connecting to the first input end and the 3rd NAND gate of the first NAND gate entirely The second input；
Charging control signal FG2 is connected to the second input of the first NAND gate；
The signal Q1 of the output end of first NAND gate, be respectively connecting to the second NAND gate two inputs and the 3rd with it is non- The first input end of door；
The output end output steering drive signal G1 of second NAND gate；
The output end output charging drive signal G2 of 3rd NAND gate；
Wherein, G1=^ (Q1)=(FG1) ＆ (FG2),
G2=^ (Q1＆FG1)=^ ((^FG1+^FG2) ＆FG1)=FG2+^FG1.
The present invention's also has a technical scheme to be to provide a kind of S4R logic control implementation methods, by above-mentioned any one Kind S4R logic control circuits, full tune bus control signal FG1, charging control signal FG2 progress logical operations are received respectively, is obtained To shunting drive signal G1 and charging drive signal G2；
Wherein, G1=FG1＆FG2, G2=FG2+ (^FG1)；
Shunting drive signal G1 is delivered to S4R shunts drive circuit, and charging drive signal G2 is delivered into charging and driven Dynamic circuit.
Preferably, the full tune bus control signal FG1 is that " 0 " shows to adjust bus to need power entirely, shows to adjust entirely for " 1 " Bus does not need power；
The charging control signal FG2 is that " 0 " shows that batteries need power, shows that batteries need not for " 1 " Power；
The shunting drive signal G1 is that " 1 " shows that sun battle array power falls to Power Groud shunting, shows sun battle array work(for " 0 " Rate does not shunt over the ground；
The charging drive signal G2 is that " 0 " shows that sun battle array to battery charging, shows sun battle array not to storing for " 1 " Battery pack charges.
Compared with prior art, S of the present invention4R logic control circuits and logic control implementation method, the advantage is that：This The logic control method can be achieved by an in-gate circuit of 4 tunnel 2 in invention, uses chip as NAND gate or nor gate, Device only needs one, saves cost.Circuit topology is easily understood simultaneously, and Project Realization is easy, and skill is adjusted with sun battle array to satellite Art has important engineering application value.
Brief description of the drawings
S provided by the invention4R logic control circuits and logic control implementation method are provided by following examples and accompanying drawing.
Fig. 1 is schematic diagram of the logic control circuit in the first example that the present invention inputs nor gate realization using 4 tunnels 2；
Fig. 2 is the schematic diagram that the present invention uses the logic control circuit that the input nand gate of 4 tunnel 2 is realized in the second example；
Fig. 3 is the logic true value table that the present invention realizes.
Embodiment
The logic control circuit and implementation method of the present invention are further described in detail below with reference to Fig. 1~Fig. 3 bright.It should manage Solution, the specific embodiments described herein are merely illustrative of the present invention, is not intended to limit the present invention.
S provided by the invention4In R logic control circuits and implementation method, two inputs of the logic control circuit Bus control signal FG1 and charging control signal FG2 is adjusted to be connected with complete respectively, after logical operation, referring to Fig. 3 logical truth It is worth table, realizes G1=FG1＆FG2, G2=FG2+ (^FG1).Wherein, output end shunting drive signal G1 and S are made4R shunting drivings Circuit is connected, and charging drive signal G2 is connected with charging drive circuit.
The FG1 is that " 0 " shows to adjust bus to need power entirely, shows to adjust bus not need power entirely for " 1 "；The FG2 Show that batteries need power for " 0 ", show that batteries do not need power for " 1 "；The G1 is that " 1 " shows sun battle array work( Rate is fallen to Power Groud shunting, shows that sun battle array power does not shunt over the ground for " 0 "；The G2 is that " 0 " shows sun battle array to battery Group charging, show sun battle array not to battery charging for " 1 ".
After described FG1, FG2 enter logic circuit computing, output signal G1, G2 realizes S4R control logic.
Embodiment one
It is as shown in Figure 1 the logic control circuit realized using 4 tunnels 2 input nor gate, two comprising the first nor gate Input connects FG1 respectively, and the signal P1 of its output end connects the first input end of the second nor gate, and the 3rd nor gate respectively First input end；The connection of the second input FG2, the signal P2 of its output end of 3rd nor gate connect the second nor gate respectively The second input, and two inputs of four nor gate；Second nor gate output signal G1, four nor gate output signal G2。
Wherein, after described FG1, FG2 enter logic circuit：P1=^FG1, P2=^ (P1+FG2),
Therefore, G1=^ (P1+P2)=(^P1) ＆ (^P2)=(FG1) ＆ (^FG1+FG2)=(FG1) ＆ (FG2),
G2=^P2=P1+FG2=FG2+^FG1.
Signal G1, G2 are provided respectively to S4R shunts drive circuit and charging drive circuit, realizes S4R logic control methods.
Embodiment two
Be illustrated in figure 2 using the input nand gate of 4 tunnel 2 realize logic control circuit, two comprising the first NAND gate Input connects FG1, FG2 respectively, the signal Q1 of output end connect respectively the second NAND gate two inputs and the 3rd with it is non- The first input end of door, the second input connection FG1 of the 3rd NAND gate；Second NAND gate exports G1, the output of the 3rd NAND gate G2。
Wherein, after described FG1, FG2 enter logic circuit：Q1=^ (FG1＆FG2),
Therefore, G1=^ (Q1)=(FG1) ＆ (FG2),
G2=^ (Q1＆FG1)=^ ((^FG1+^FG2) ＆FG1)=FG2+^FG1.
Signal G1, G2 are provided respectively to S4R shunts drive circuit and charging drive circuit, realizes S4R logic control methods.

Claims (4)

  1. A kind of 1. S4R logic control circuits, it is characterised in that include：
    Four nor gates, it each has two inputs and an output end；
    Wherein, bus control signal FG1 is adjusted to be connected to two inputs of the first nor gate entirely；
    The signal P1 of the output end of first nor gate is respectively connecting to the first input end and the 3rd nor gate of the second nor gate First input end；
    Charging control signal FG2 is connected to the second input of the 3rd nor gate；
    The signal P2 of the output end of 3rd nor gate is respectively connecting to the second input of the second nor gate, and the two of four nor gate Individual input；
    The output end output steering drive signal G1 of second nor gate；
    The output end output charging drive signal G2 of four nor gate；
    Wherein, G1=^ (P1+P2)=(^P1) ＆ (^P2)=(FG1) ＆ (^FG1+FG2)=(FG1) ＆ (FG2)；
    G2 =^P2=P1+FG2=FG2+^FG1。
  2. A kind of 2. S4R logic control circuits, it is characterised in that include：
    Three NAND gates, it each has two inputs and an output end；
    Wherein, adjust full bus control signal FG1 be respectively connecting to the first NAND gate first input end and the 3rd NAND gate the Two inputs；
    Charging control signal FG2 is connected to the second input of the first NAND gate；
    The signal Q1 of the output end of first NAND gate, it is respectively connecting to two inputs and the 3rd NAND gate of the second NAND gate First input end；
    The output end output steering drive signal G1 of second NAND gate；
    The output end output charging drive signal G2 of 3rd NAND gate；
    Wherein, G1=^ (Q1)=(FG1) ＆ (FG2),
    G2=^(Q1&FG1)=^((^FG1+^FG2)&FG1)=FG2+^FG1。
  3. A kind of 3. S4R logic control implementation methods, it is characterised in that
    Pass through the S of claim 1 or 24R logic control circuits, full tune bus control signal FG1, charging control signal are received respectively FG2 carries out logical operation, obtains shunting drive signal G1 and charging drive signal G2；
    Wherein, G1=FG1＆FG2, G2=FG2+（^FG1）；
    Shunting drive signal G1 is delivered to S4R shunts drive circuit, and charging drive signal G2 is delivered into charging driving electricity Road.
  4. 4. S as claimed in claim 34R logic control implementation methods, it is characterised in that
    The full tune bus control signal FG1 is that " 0 " shows to adjust bus to need power entirely, shows to adjust bus need not entirely for " 1 " Power；
    The charging control signal FG2 is that " 0 " shows that batteries need power, shows that batteries do not need power for " 1 "；
    The shunting drive signal G1 is that " 1 " shows that sun battle array power falls to Power Groud shunting, shows sun battle array power not for " 0 " Shunt over the ground；
    The charging drive signal G2 is that " 0 " shows that sun battle array to battery charging, shows sun battle array not to battery for " 1 " Group charging.
CN201510820843.0A 2015-11-24 2015-11-24 A kind of S4R logic control circuits and its logic control implementation method Active CN105262477B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103116535A (en) * 2011-11-17 2013-05-22 上海航天测控通信研究所 Satellite-bone dual-redundant computer mainframe working condition monitoring and fault autonomous switching device
CN104319838A (en) * 2014-10-20 2015-01-28 上海空间电源研究所 Overcharge protection circuit and method of series sequential switching shunt regulator
CN104410038A (en) * 2014-10-21 2015-03-11 上海空间电源研究所 Overvoltage protection circuit for discharge regulating circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6841983B2 (en) * 2002-11-14 2005-01-11 Fyre Storm, Inc. Digital signal to pulse converter and method of digital signal to pulse conversion

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103116535A (en) * 2011-11-17 2013-05-22 上海航天测控通信研究所 Satellite-bone dual-redundant computer mainframe working condition monitoring and fault autonomous switching device
CN104319838A (en) * 2014-10-20 2015-01-28 上海空间电源研究所 Overcharge protection circuit and method of series sequential switching shunt regulator
CN104410038A (en) * 2014-10-21 2015-03-11 上海空间电源研究所 Overvoltage protection circuit for discharge regulating circuit

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