CN105227543B - The Ethernet UDP/IP processors based on FPGA that parameter can configure - Google Patents
The Ethernet UDP/IP processors based on FPGA that parameter can configure Download PDFInfo
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- CN105227543B CN105227543B CN201510532282.4A CN201510532282A CN105227543B CN 105227543 B CN105227543 B CN 105227543B CN 201510532282 A CN201510532282 A CN 201510532282A CN 105227543 B CN105227543 B CN 105227543B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/0803—Configuration setting
Abstract
The invention discloses the Ethernet UDP/IP processors based on FPGA that a kind of parameter can configure, add configuration control module and PHY configuration modules, then increase frame newly in UDP/IP protocol stack modules and send configuration module, frame reception configuration module, MAC control configuration modules have been increased newly in mac controller；Configuration control module is from user terminal reception system configuration data, including UDP/IP protocol stack arrangements parameter, MAC controls configuration parameter and PHY chip configuration parameter, then configuration module is sent by frame, frame receives configuration module, parameter is respectively configured in corresponding module, while realizes the inquiry to configuring parameter in corresponding module by MAC control configuration modules and PHY configuration modules.The present invention realizes parameter configuration and inquiry of the user to Ethernet UDP/IP processors by configuration control module, processor parameter change is conveniently and efficiently realized, so as to improve the applicability of Ethernet UDP/IP processors.
Description
Technical field
The network protocol stack technical field that the invention belongs to be realized based on FPGA, more specifically, is related to a kind of parameter
The configurable Ethernet UDP/IP processors based on FPGA.
Background technology
Ethernet has and is widely used as common communication mode, and traffic rate is high, and it is excellent that resource sharing capability is strong etc.
Point, is widely used in the interconnected communication field of equipment.Realize equipment room network service, its precondition is integrated with equipment
Network protocol stack, the transport layer protocol of its protocol stack mainly have two kinds of a Transmission Control Protocol and udp protocol, udp protocol as connectionless,
Unreliable, the agreement based on message interaction, is widely used in the application such as audio, video.In the past, protocol stack is all base mostly
Realize that, network transfer speeds are low using CPU serially, and system resource overhead is big in software.For Software Protocol Stack
The deficiency of mode, in big data transmission field, more and more people begin one's study the Ethernet UDP/IP processors based on FPGA.
Ethernet UDP/IP processors based on FPGA illustrate and realization may refer to document " Alachiotis N, Berger
S A,Stamatakis A.Efficient PC-FPGACommunication over Gigabit Ethernet[C]//
Proceedings of the 2010 10th IEEE International Conference on Computer and
Information Technology.IEEE Computer Society,2010:1727-1734.”。
The current Ethernet UDP/IP processors based on FPGA, have the disadvantages that：(1) simply realize transport layer and
The agreement of network layer, and the mac controller in network interface layer all relies on the offer of tripartite, increases cost of implementation；(2) it is right
Mac controller in the transport layers of Ethernet UDP/IP processors, network layer and network interface layer cannot accomplish User Defined
Configuration so that transmission can only communicate with single communication node, and make whole system configuration trouble, and changing system configuration every time all needs
Code and again programming are changed, big using difficulty, the performance that have impact on whole system plays；(3) for networked physics layer core
Piece, needs to configure its register competence exertion maximum efficiency mostly, and the configuration of the Ethernet UDP/IP processors based on FPGA
It is increasingly complex compared with software configuration.
The content of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide the ether based on FPGA that a kind of parameter can configure
UDP/IP processors are netted, user is realized the parameter configuration to the Ethernet UDP/IP processors based on FPGA.
For achieving the above object, the Ethernet UDP/IP processors based on FPGA that parameter of the present invention can configure include
UDP/IP protocol stack modules, mac controller, wherein UDP/IP protocol stack modules include frame and send assembling module, frame reception opening
Die-filling piece and MAC interface module, mac controller include IP interface modules, send buffer module, send controller, receive control
Device, receive buffer module and flow control module, in addition, Ethernet UDP/IP processors further include configuration control module and PHY configurations
Module, UDP/IP protocol stack modules further include frame and send configuration module, frame reception configuration module, and mac controller further includes MAC controls
Device configuration module processed；
Being respectively UDP/IP protocol stack arrangements parameter and MAC control configuration parameter settings in configuration control module, parameter is posted
Storage, parameter setting address register and parameter register are configured for PHY chip；When configuration control module is received from user terminal
UDP/IP protocol stack arrangements parameter or MAC control configuration parameter, write in corresponding register, and to frame send configuration module or
Frame receive configuration module send system configuration signal, when configuration control module from user terminal receive PHY chip configuration parameter and
Corresponding PHY register address, then write corresponding register, and sends system configuration signal to PHY configuration modules；Work as configuration
Control module receives configuration querying signal from user terminal, respectively to frame sends configuration module, frame receives configuration module, MAC is controlled
Device configuration module and PHY configuration modules send configuration querying signal, and the configuration parameter for then feeding back each configuration module is sent
To user terminal；
Frame sends register address and frame of the parameter needed for storage in configuration control module in configuration module and sends assembling
The mapping table of mould storage address in the block, after system configuration signal is received, according to register address from configuration control module
Parameter needed for middle reading, write-in frame send the correspondence storage address of assembling module；The configuration that configuration control module is sent is received to look into
Signal is ask, is sent from frame and configuration parameter feedback is read in assembling module to configuration control module；
Frame receives register address and frame of the parameter needed for storage in configuration control module in configuration module and receives opening
The mapping table of die-filling storage address in the block, after system configuration signal is received, mould is controlled according to register address from configuration
Parameter needed for being read in block, write-in frame receive the correspondence storage address for tearing package module open；Receive matching somebody with somebody for configuration control module transmission
Inquiry signal is put, receives to tear open from frame and configuration parameter feedback is read in package module to configuration control module；
Register address and mac controller of the parameter in configuration control module needed for the storage of mac controller configuration module
The mapping table for sending controller, receiving controller and flow control mould storage address in the block, after system configuration signal is received,
Parameter needed for being read according to register address from configuration control module, is respectively written into and sends controller, receives controller and stream
Control the correspondence storage address of module；The configuration querying signal that configuration control module is sent is received, is controlled from sending controller, receiving
Configuration parameter feedback is read in device and flow control module to configuration control module；
PHY configuration modules after system configuration signal is received, from configuration control module read needed for parameter and corresponding
PHY register address, the corresponding register for the PHY chip that parameter read-in is connected with Ethernet UDP/IP processors；Reception is matched somebody with somebody
The configuration querying signal of control module transmission is put, configuration parameter feedback is read from PHY chip to configuration control module.
The Ethernet UDP/IP processors based on FPGA that parameter of the present invention can configure, add configuration control module and
PHY configuration modules, then increase frame newly in UDP/IP protocol stack modules and send configuration module, frame reception configuration module, controlled in MAC
Device processed has increased mac controller configuration module newly；Configuration control module configures parameter, including UDP/IP associations from user terminal reception system
Stack configuration parameter, MAC controls configuration parameter and PHY chip configuration parameter are discussed, configuration module is then sent by frame, frame is received and matched somebody with somebody
Put module, mac controller configuration module and PHY configuration modules parameter is respectively configured in corresponding module, while realization pair
The inquiry of parameter is configured in corresponding module.The present invention realizes user to Ethernet UDP/IP processors by configuration control module
Parameter configuration and inquiry, conveniently and efficiently realize processor parameter change, so as to improve being applicable in for Ethernet UDP/IP processors
Property.
Brief description of the drawings
Fig. 1 is the overall structure figure for the Ethernet UDP/IP processors based on FPGA that can configure using parameter of the present invention；
Fig. 2 is the structure chart of system configuration module in Fig. 1；
Fig. 3 is the structure chart of UDP/IP protocol stack modules in Fig. 1；
Fig. 4 is the structure chart of mac controller in Fig. 1；
Fig. 5 is the structure chart of MDIO modules；
Fig. 6 is the input/output port figure of MDIO control modules；
Fig. 7 is the structure chart of MDIO interface modules.
Embodiment
The embodiment of the present invention is described below in conjunction with the accompanying drawings, so as to those skilled in the art preferably
Understand the present invention.Requiring particular attention is that in the following description, when known function and the detailed description of design perhaps
When can desalinate the main contents of the present invention, these descriptions will be ignored herein.
Embodiment
Fig. 1 is the overall structure figure for the Ethernet UDP/IP processors based on FPGA that can configure using parameter of the present invention.
As shown in Figure 1, the Ethernet UDP/IP processors based on FPGA that can configure of parameter of the present invention with it is common based on FPGA with
Too net UDP/IP processors are compared, its difference is to add a system configuration module.
Fig. 2 is the structure chart of system configuration module in Fig. 1.As shown in Fig. 2, system configuration module includes configuration control module
With PHY configuration modules.It is respectively UDP/IP protocol stack arrangements parameter or MAC control configuration parameter settings in configuration control module
Parameter register, parameter setting address register and parameter register are configured for PHY (Physical Layer, physical layer) chip
Device.When configuration control module receives UDP/IP protocol stack arrangements parameter or MAC control configuration parameters from user terminal, write-in is accordingly
Register in, and to frame send configuration module or frame and receive configuration module and send system configuration signal, when configuration control module from
User terminal receives PHY chip configuration parameter and corresponding PHY register address, then writes corresponding register, and match somebody with somebody to PHY
Put module and send system configuration signal.In addition, configuration control module also from user terminal receive configuration querying signal, then respectively to
Frame sends configuration module, frame receives configuration module, mac controller configuration module and PHY configuration modules and sends system transmission configuration
Signal is inquired about, the configuration parameter feedback that each configuration module is fed back is to user terminal.The parameter each fed back, which can be first updated to, matches somebody with somebody
Put in the corresponding register of control module, be then read out by user terminal.
Table 1 is the Register Allocation Table of configuration control module in the present embodiment.
Table 1
As shown in table 1, in the present embodiment, the UDP/IP protocol stack arrangements that are configured required for UDP/IP protocol stack modules
Parameter includes target MAC (Media Access Control) address, source mac addresses, source IP address, purpose IP address, UDP source port numbers, UDP destination slogans.
Configuration control module is configured with a register for each parameter of UDP/IP protocol stack modules.
The MAC control configuration parameters being configured required for mac controller are enabled including unicast filtering frames, multicast filtering frames
Enabled, broadcast filtering frames, which enable, suspend filtering frames, which enables, receives all frames enables, sends pause frame enables, this equipment MAC
Location, broadcast MAC address and minimum frame gap time.Similarly, configuration control module configures for each parameter of mac controller
One register.
PHY is the standard module that IEEE802.3 is defined.For PHY chip, usually there are 32 deposits in its inside
Device, wherein, first 16 are provided by 802.3 agreements, and to be necessary, each manufacturer is essentially identical, latter 16 by PHY chip producer from
Definition.The mode of access generally use MDIO buses to PHY chip register, under the synchronization of MDC clocks, is read and write with MDIO
The form of frame, reads it and write operation, in general, including PHY chip address field, PHY chip in the read-write frame of MDIO
Register address domain and data field.In the present embodiment, be PHY chip one address register of configuration parameter setting and one
Parameter register.When carrying out PHY parameter configurations to being configured one by one to parameter.
In order to realize function that parameter can configure, the present invention is in addition to setting system configuration module, it is also necessary in UDP/IP
Corresponding configuration feature module is set in protocol stack module and mac controller, to realize the configuration to corresponding module parameter.
Fig. 3 is the structure chart of UDP/IP protocol stack modules in Fig. 1.As shown in figure 3, the present invention is in UDP/IP protocol stack modules
In, add two modules：Frame sends configuration module and frame receives configuration module, is respectively used to send assembling module and frame to frame
The relevant parameter that package module is torn in reception open is configured.
Frame sends register address and frame of the parameter in configuration control module needed for configuration module storage and sends assembling mould
The mapping table of storage address in the block, after system configuration signal is received, according to register address from configuration control module
Parameter needed for reading, write-in frame send the correspondence storage address of assembling module.For frame send assembling module, it is necessary to parameter be
MAC Address, source mac addresses, source IP address, purpose IP address, UDP source port numbers, the UDP of frame frame originating point information are sent for forming
Destination slogan.In the Ethernet UDP/IP processors based on FPGA, send frame frame originating point information meeting fixed storage and deposited at one
Store up in module, be the RAM of 64x8bit in the present embodiment.In transmission process, UDP/IP protocol stacks can be first the number in RAM
According to sending in order, the frame head for sending frame is formed, particular user data is then retransmited, the envelope of user data is completed with this
Dress.Table 2 is transmission frame frame originating point information table in the present embodiment.
Table 2
In query configuration parameter, the configuration querying signal that configuration control module is sent is received, assembling module is sent from frame
The middle configuration parameter feedback that reads is to configuration control module.
Similarly, frame receives register address and frame of the parameter in configuration control module needed for storage in configuration module and connects
The mapping table for sealing off die-filling storage address in the block is received, after system configuration signal is received, according to register address from configuration
Parameter needed for being read in control module, write-in frame receive the correspondence storage address for tearing package module open.Receive configuration control module hair
The configuration querying signal sent, receives to tear open from frame and configuration parameter feedback is read in package module to configuration control module.Frame is received and torn open
Package module is used for the reception for completing data, and during reception, the purpose IP address of receiving frame can be received with frame seals off dress
The IP address of module storage is matched, if matched, is received user data, is otherwise abandoned.Therefore frame receives Encapsulation Moulds
Parameter needed for block is the IP address of equipment, that is, the source IP address stored in configuration control module.
Fig. 4 is the structure chart of mac controller in Fig. 1.As shown in figure 4, mac controller includes IP interface modules, sends and delay
Die block, send controller, receive controller, receive buffer module and flow control module, and data frame is completed in network interface layer
The functions such as encapsulation, deblocking, transmission, reception, address filtering and flow control.In order to realize the parameter configuration to mac controller,
Need to newly increase a mac controller configuration module, mac controller configuration module is respectively with sending controller, receiving controller
Connected with flow control module.The transmission control of register address and mac controller of the parameter needed for storage in configuration control module
Device, receive controller and the mapping table of flow control mould storage address in the block, after system configuration signal is received, according to register
Address read from configuration control module needed for parameter, pair for be respectively written into and send controller, receiving controller and flow control module
Answer storage address.In inquiry, the configuration querying signal that configuration control module is sent is received, from transmission controller, receives control
Configuration parameter feedback is read in device and flow control module to configuration control module.
In the present embodiment, parameter needed for transmission controller is mcast_addr [47:32] (broadcast address in broadcast frame is sent
It is 16 high) and mcast_addr [31:0] (it is 32 low to send broadcast address in broadcast frame)；Receive controller needed for parameter be
Pass_ucast (allowing to receive unicast frame), pass_mcast (allowing to receive broadcast frame), ucast_addr [47:32] (with connecing
Unicast address is matched 16 high in received unicast frame) and ucast_addr [31:0] (with unicast in the unicast frame that receives
Low 32 of address matching)；Parameter needed for flow control module is pause_thresh [15:0] threshold value of pause frame (send),
pasuse_time[15:0] (transmission of mac flow controls, the time of pause frame) and pause_request_en (permission flow control).
It is an external chip since PHY chip is for the Ethernet UDP/IP processors based on FPGA, it is joined
The realization of number configuration can be more complex for the parameter configuration of UDP/IP protocol stack modules and mac controller, therefore needs
A PHY configuration module is set to configure the parameter of PHY chip.PHY configuration modules are receiving system configuration letter
After number, from parameter and corresponding PHY register address needed for configuration control module reading, by parameter read-in and Ethernet UDP/IP
The correspondence register of the PHY chip of processor connection.In inquiry, the configuration querying signal that configuration control module is sent is received,
The configuration querying signal of PHY chip includes the corresponding PHY register address of wanted query argument, and PHY configuration modules will be from PHY
Configuration parameter feedback is read in chip to configuration control module.
(Management Data Input/Output, management data are defeated using MDIO for PHY configuration modules in the present invention
Enter output) module, to realize the parameter configuration to PHY chip.Fig. 5 is the structure chart of MDIO modules.As shown in figure 5, MIDO moulds
Block includes MDIO clock modules, MDIO control modules and MDIO interface modules, and it is generation MDC clocks that its function, which is respectively, right
MDIO interface modules are generated required control signal and the configuration to PHY registers are completed with MDIO read-write frame formats.
MDIO clock modules are according to default clock division coefficient d ivide [7:0] system clock is divided, produces frequency dividing
MDC clocks in clock, i.e. Fig. 5, its frequency are generally 2.5MHz.At the same time the rising edge mdc_ of MDC is also produced
The upper trailing edge clock mdc_fall of rise and MDC.Frequency dividing MDC clocks are sent to PHY chip, by rising edge mdc_
Rise and trailing edge clock mdc_fall are sent to MDIO control modules, and trailing edge clock mdc_fall then is sent to MDIO
Interface module；
The system configuration signal and configuration querying signal generation interface that MDIO control modules are sent according to configuration control module
Signal, MDIO write frame construction signal in module control signal, including write enable signal, processing procedure, MDIO reads frame analytic signal,
It is sent to MDIO interface modules.Fig. 6 is the input/output port figure of MDIO control modules.As shown in fig. 6, wrctdata, scan,
Writing PHY chip register signal, scanning signal, reading PHY chips of the radata and nopre respectively from REG management modules are posted
Storage signal and MDIO frames do not include frame prefix domain.Wcrtdatastart, scanstart, rdatastart, busy and
Nvaild is to feed back to writing PYH chip registers commencing signal, scanning PHY chip commencing signal, reading for REG management modules respectively
PHY chip register commencing signal, busy signal and disarmed state signal.Wherein, wcrtdatastart, scanstart and
Rdatastart will be used to the miicommand registers of filling configuration control module, and nvalid and busy will be used to fill
Miistatus registers, the content of these registers is all by feedback user end.writeop、inprogress、bytesel[3:
0]、latch_sel[1:0] and bitconter [7:0] all it is the signal that acts on MDIO interface modules, respectively writes enabled letter
Number, signal, MDIO write frame construction signal in processing procedure, MDIO reads frame analytic signal and eight bit register output signal.
In MDIO control modules, the counter of one 8 is maintained, 63 are count down to from 0, each count value corresponds to and 64
Position MDIO data frames in each.For byte_sel [3:0] for, during write operation, when nopre is invalid, meter
7'h20 is counted to, or when nopre is effective, count down to 7'h00, byte_sel [3:0] 0001 will be changed into；When counting down to 7'h28
When, byte_sel [3:0] 0001 will be all changed into；When counting down to 7'h30, byte_sel [3:0] 0100 will be changed into；When counting down to
During 7'h3f, byte_sel [3:0] 1000 will be changed into.byte_sel[3:0] MDIO interface modules are controlled to send the construction of frame.
For latch_sel [1:0], during read operation, when counter counts count to 7'h37, latch_sel [0] set；Work as meter
When counting to 7'h3f, latch_sel [1] set, wherein 7'h37 be MDIO data frames in 16 data high bytes position, 7'
H3f is the position of 16 data low bytes in MDIO data frames.latch_sel[1:0] MDIO interface module data frames are controlled
Parsing.
The control signal that MDIO interface modules are sent according to MDIO control modules carries out parameter write operation and parameter read operation,
When carrying out write operation, configuration parameter and corresponding PHY register address are read from configuration control module according to register address,
Structure MDIO frames are sent to PHY chip, and parameter is stored in corresponding PHY registers；When carrying out read operation, according to register
PHY register address is read in location from configuration control module, reads after corresponding configuration parameter is parsed and sends out from PHY registers
Give configuration control module.
Fig. 7 is the structure chart of MDIO interface modules.As shown in fig. 7, MDIO interface modules include MDIO output controls, displacement
Module and input/output module, wherein shift module are nucleus module, it will assemble read-write frame according to MDIO frame formats.When from
When mdio buses obtain mdio reading frames, the data frame read is parsed, in latch_sel [1:0] under control, read
This data, is then passed through phy_rdx [15 by the data of 16 in frame:0] configuration control module is passed to；As MDIO to be sent
When frame is to PHY chip, pass through crtl_data [15 from REG modules:0] data to be sent are taken, pass through phy_addr [4:0]
The PHY chip address for wanting piece to select is taken, passes through reg_addr [4:0] register address of PHY chip to be accessed is taken,
byte_sel[3:0] under control, then the form them according to MDIO frames, is packaged into them and writes frame, then by bit string
Capable one position of mode is sent to MDIO output controls, control signal of the MDIO output control modules in MDIO control modules
Under, enable MDIO output enable signal MdoEn, selected input output transmission, then output data mdo pass through MDIO bus handles
The data frame is sent to PHY chip.In processing procedure, if sending mistake, produce linkfail signals and feed back to REG controls
Module.
Although the illustrative embodiment of the present invention is described above, in order to the technology of the art
Personnel understand the present invention, it should be apparent that the invention is not restricted to the scope of embodiment, to the common skill of the art
For art personnel, if various change appended claim limit and definite the spirit and scope of the present invention in, these
Change is it will be apparent that all utilize the innovation and creation of present inventive concept in the row of protection.
Claims (3)
1. the Ethernet UDP/IP processors based on FPGA that a kind of parameter can configure, including UDP/IP protocol stack modules, MAC control
Device processed, wherein UDP/IP protocol stack modules include frame transmission assembling module, frame receives and tears package module and MAC interface module, MAC open
Controller includes IP interface modules, sends buffer module, send controller, receive controller, receive buffer module and flow control mould
Block, it is characterised in that Ethernet UDP/IP processors further include configuration control module and PHY configuration modules, UDP/IP protocol stacks
Module further includes frame and sends configuration module, frame reception configuration module, and mac controller further includes mac controller configuration module, its
In,
It is respectively that UDP/IP protocol stack arrangements parameter and MAC controls configure parameter setting parameter register in configuration control module
Device, parameter setting address register and parameter register are configured for PHY chip；When configuration control module is received from user terminal
UDP/IP protocol stack arrangements parameter or MAC control configuration parameter, write in corresponding register, and to frame send configuration module or
Frame receive configuration module send system configuration signal, when configuration control module from user terminal receive PHY chip configuration parameter and
Corresponding PHY register address, then write corresponding register, and sends system configuration signal to PHY configuration modules；Work as configuration
Control module receives configuration querying signal from user terminal, respectively to frame sends configuration module, frame receives configuration module, MAC is controlled
Device configuration module and PHY configuration modules send configuration querying signal, and the configuration parameter for then feeding back each configuration module is sent
To user terminal；
Frame sends register address and frame of the parameter needed for storage in configuration control module in configuration module and sends assembling module
In storage address mapping table, after system configuration signal is received, read according to register address from configuration control module
Required parameter is taken, write-in frame sends the correspondence storage address of assembling module；Receive the configuration querying letter that configuration control module is sent
Number, sent from frame and configuration parameter feedback is read in assembling module to configuration control module；
It is die-filling that frame receives register address and frame reception opening of the parameter needed for storage in configuration control module in configuration module
The mapping table of storage address in the block, after system configuration signal is received, according to register address from configuration control module
Parameter needed for reading, write-in frame receive the correspondence storage address for tearing package module open；The configuration that configuration control module is sent is received to look into
Signal is ask, receives to tear open from frame and configuration parameter feedback is read in package module to configuration control module；
The hair of register address and mac controller of the parameter in configuration control module needed for the storage of mac controller configuration module
Send controller, receive controller and the mapping table of flow control mould storage address in the block, after system configuration signal is received, according to
Register address read from configuration control module needed for parameter, be respectively written into and send controller, receive controller and flow control mould
The correspondence storage address of block；Receive configuration control module send configuration querying signal, from send controller, receive controller and
Configuration parameter feedback is read in flow control module to configuration control module；
PHY configuration modules are posted after system configuration signal is received from parameter and corresponding PHY needed for configuration control module reading
Storage address, the corresponding register for the PHY chip that parameter read-in is connected with Ethernet UDP/IP processors；Receive configuration control
The configuration querying signal that module is sent, reads configuration parameter feedback to configuration control module from PHY chip.
2. Ethernet UDP/IP processors according to claim 1, it is characterised in that the configuration control module and user
End passes through Wishbone bus interaction datas.
3. Ethernet UDP/IP processors according to claim 1, it is characterised in that the PHY configuration modules use
MDIO modules, including MDIO clock modules, MDIO control modules and MDIO interface modules, wherein：
MDIO clock modules divide system clock according to default clock division coefficient, obtain frequency-dividing clock and the frequency dividing
The rising edge and trailing edge clock of clock, PHY chip is sent to by frequency-dividing clock, by rising edge and trailing edge clock
MDIO control modules are sent to, trailing edge clock is then sent to MDIO interface modules；
The system configuration signal and configuration querying signal generation interface module that MDIO control modules are sent according to configuration control module
Signal, MDIO write frame construction signal in control signal, including write enable signal, processing procedure, MDIO reads frame analytic signal, send
Give MDIO interface modules；
The control signal that MDIO interface modules are sent according to MDIO control modules carries out parameter write operation and parameter read operation, into
When row write operates, configuration parameter and corresponding PHY register address, structure are read from configuration control module according to register address
MDIO frames are sent to PHY chip, and parameter is stored in corresponding PHY registers；When carrying out read operation, according to register address from
Configuration control module reads PHY register address, reads after corresponding configuration parameter is parsed and is sent to from PHY registers
Configuration control module.
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| CN106302464B (en) * | 2016-08-17 | 2019-07-26 | 浪潮集团有限公司 | A kind of hardware based adaptive network framework and adaptive network method |
| CN108540982B (en) * | 2017-03-06 | 2021-10-22 | 上海诺基亚贝尔股份有限公司 | Communication method and device for virtual base station |
| CN108737352B (en) * | 2017-04-25 | 2020-07-28 | 北京大学 | Wireless physical layer processing system and method compatible with multi-protocol and nonstandard protocol |
| CN107766283A (en) * | 2017-10-30 | 2018-03-06 | 济南浪潮高新科技投资发展有限公司 | A kind of implementation method and device for quick configuration data processing board |
| CN108462642B (en) * | 2018-03-16 | 2020-06-30 | 西安电子科技大学 | UDP/IP hardware protocol stack based on FPGA and implementation method |
| CN112637075A (en) * | 2020-12-12 | 2021-04-09 | 华中光电技术研究所（中国船舶重工集团公司第七一七研究所） | UDP/IP protocol stack implementation method based on FPGA and FPGA chip |
| CN117749912A (en) * | 2024-02-19 | 2024-03-22 | 浙江双元科技股份有限公司 | Data transmission control method and system based on FPGA module |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203151539U (en) * | 2012-11-09 | 2013-08-21 | 北京航空航天大学 | AFDX terminal system virtual link layer IP core |
| CN103916252A (en) * | 2014-04-18 | 2014-07-09 | 岳阳巅峰电子科技有限责任公司 | High-bandwidth Ethernet IP core based on FPGA |
-
2015
- 2015-08-26 CN CN201510532282.4A patent/CN105227543B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203151539U (en) * | 2012-11-09 | 2013-08-21 | 北京航空航天大学 | AFDX terminal system virtual link layer IP core |
| CN103916252A (en) * | 2014-04-18 | 2014-07-09 | 岳阳巅峰电子科技有限责任公司 | High-bandwidth Ethernet IP core based on FPGA |
Non-Patent Citations (3)
| Title |
|---|
| A Versatile UDP/IP based PC-FPGA Communication Platform;N.Alachiotis,et al.;《2012 International Conference on Reconfiguration Computing and FPGAs》;20130124;第1-6页 * |
| 基于FPGA+MAC+PHY的千兆以太网数传系统设计;侯义合 等;《科学技术与工程》;20140731;第14卷(第19期);第275-279页 * |
| 基于FPGA的UDP/IP硬件协议栈的研究与实现;叶祎恒;《中国优秀硕士学位论文全文数据库 信息科技辑》;20101115(第11期);第I139-23页 * |
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