CN105226050A - Semiconductor structure and manufacture method thereof - Google Patents
Semiconductor structure and manufacture method thereof Download PDFInfo
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- CN105226050A CN105226050A CN201410254140.1A CN201410254140A CN105226050A CN 105226050 A CN105226050 A CN 105226050A CN 201410254140 A CN201410254140 A CN 201410254140A CN 105226050 A CN105226050 A CN 105226050A
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- barrier layer
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- guide hole
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Abstract
The invention relates to a kind of semiconductor structure and manufacture method thereof.The barrier layer that described semiconductor structure comprises a conductive layer, a guide hole and is arranged between conductive layer and guide hole.Wherein barrier layer filling aerobic.The present invention, by with the crystal boundary of oxygen filling barrier layer, has blocked the evolving path of composition material or reactivity/deposition gases, and can compensate the impact that boundary defect brings, and thus can provide more effective barrier layer.
Description
Technical field
The present invention relates to a kind of semiconductor structure and manufacture method thereof, particularly relate to a kind of semiconductor structure and the manufacture method thereof that comprise the barrier layer (barrierlayer) of filling aerobic.
Background technology
In the semiconductor structure, at electronic component as on memory body or transistor, interconnection layer (interconnectionlayer) generally can be formed, to provide electric connection.Interconnection layer is connected to each other by guide hole (via).The diffusion of the reactivity/deposition gases used in composition material or technique, often provides barrier layer between interconnection layer and guide hole.
Summary of the invention
The object of the invention is to, provide a kind of new semiconductor structure and manufacture method thereof, technical problem to be solved makes it comprise more effective barrier layer, thus be more suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.A kind of semiconductor structure proposed according to the present invention comprises: a conductive layer, a guide hole and the barrier layer be arranged between conductive layer and guide hole.Wherein barrier layer filling aerobic.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid semiconductor structure, wherein said conductive layer comprises interconnection line.
Aforesaid semiconductor structure, wherein said barrier layer is made up of the individual layer comprising titanium nitride (TiN).
Aforesaid semiconductor structure, wherein said barrier layer formed both following: one first barrier layer, is arranged on this conductive layer, and this first barrier layer comprises titanium (Ti); And one second barrier layer, be arranged on this first barrier layer, and under being arranged on this guide hole, this second barrier layer comprises titanium nitride (TiN).
Aforesaid semiconductor structure, wherein said oxygen is packed on the crystal boundary of this barrier layer.
Aforesaid semiconductor structure, also comprises: an interlayer dielectric, is arranged on this conductive layer, this interlayer dielectric has an opening, and this opening exposes a part for this conductive layer, wherein, this barrier layer contacts this part that this conductive layer exposes, and this guide hole is arranged in the openings.
Aforesaid semiconductor structure, wherein said conductive layer is made up of copper (Cu), and this guide hole is made up of tungsten (W), and this barrier layer comprises titanium nitride (TiN) layer, the crystal boundary filling aerobic of this titanium nitride layer.
Aforesaid semiconductor structure, wherein said barrier layer also comprises a titanium (Ti) layer, is arranged between this conductive layer and this titanium nitride layer.The object of the invention to solve the technical problems also realizes by the following technical solutions.The manufacture method of a kind of semiconductor structure proposed according to the present invention comprises the following steps.First, a barrier layer is formed on a conductive layer.Then, with oxygen filling barrier layer.Afterwards, a guide hole is formed on the barrier layer of filling aerobic.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The manufacture method of aforesaid semiconductor structure, wherein clogging in the step of this barrier layer with oxygen, pressure controls at 6torr to 10torr, and provide oxygen with the flow velocity of 25sccm to 85sccm, maintains 10 seconds to 60 seconds.
The present invention compared with prior art has obvious advantage and beneficial effect.By technique scheme, semiconductor structure of the present invention and manufacture method thereof at least have following advantages and beneficial effect: the present invention is by the crystal boundary clogging barrier layer with oxygen, block the evolving path of composition material or reactivity/deposition gases, and the impact that boundary defect brings can be compensated, thus can provide more effective barrier layer.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to technological means of the present invention can be better understood, and can be implemented according to the content of specification, and can become apparent to allow above and other object of the present invention, feature and advantage, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of semiconductor structure according to an embodiment of the invention.
Fig. 2 is according to the schematic diagram of semiconductor structure being another embodiment of the present invention.
Fig. 3 is and the source map relevant according to the semiconductor structure of the present invention's embodiment described herein.
Fig. 4 A-Fig. 4 E is the schematic diagram of semiconductor structure manufacture method according to an embodiment of the invention.
100,200: semiconductor structure 102,202,302: conductive layer
102a, 302a: part 104,204,304: guide hole
106,206,306: barrier layer 108,308: the first barrier layer
110,310: the second barrier layers 112,212,312: interlayer dielectric
112o, 212o, 312o: opening 314: rectangular structure
O: oxygen
Embodiment
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take and effect, below in conjunction with accompanying drawing and preferred embodiment, to the semiconductor structure proposed according to the present invention and its embodiment of manufacture method, structure, method, step, feature and effect thereof, be described in detail as follows.
Aforementioned and other technology contents, Characteristic for the present invention, can know and present in the detailed description of following cooperation with reference to graphic preferred embodiment.By the explanation of embodiment, should to the present invention for the technological means reaching predetermined object and take and effect obtain one more deeply and concrete understanding, but institute's accompanying drawings is only to provide with reference to the use with explanation, is not used for being limited the present invention.
Referring to shown in Fig. 1, is the schematic diagram of semiconductor structure 100 according to an embodiment of the invention.The barrier layer 106 that semiconductor structure 100 comprises conductive layer 102, guide hole 104 and is arranged between conductive layer 102 and guide hole 104.Barrier layer 106 clogs aerobic.More particularly, oxygen is packed on the crystal boundary of barrier layer 106.Fig. 1 and other graphic are for explanation, and relative size wherein, quantity and bond situation etc. are drawn according to real situation.
Conductive layer 102 can be interconnection layer, and it comprises interconnection line (interconnectionline), such as copper cash, aluminum steel or albronze line.That is, conductive layer 102 can comprise copper (Cu), aluminium (Al) or aluminium copper (AlCu).Guide hole 104 can comprise tungsten (W) or copper (Cu).Barrier layer 106 can be the single layer structure, double-decker or the sandwich construction that comprise tantalum (Ta), titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN) or tungsten nitride (WN).In this embodiment, barrier layer 106 is made up of one first barrier layer 108 and one second barrier layer 110.First barrier layer 108 is arranged on conductive layer 102.Second barrier layer 110 is arranged on the first barrier layer 108, and be arranged on guide hole 104 times.For example, the first barrier layer 108 can comprise titanium, and the second barrier layer 110 can comprise titanium nitride.
More particularly, conductive layer 102 can be made of copper, and guide hole 104 can be made up of tungsten.Now, barrier layer 106 can comprise titanium nitride layer (that is second barrier layer 110), and its crystal boundary is filling aerobic O.Barrier layer 106 also can comprise a titanium layer (that is first barrier layer 108), is arranged between conductive layer 102 and titanium nitride layer.In some instances, the crystal boundary of titanium layer also can clog aerobic O.
Though be not limited to prior art, semiconductor structure 100 generally also comprises an interlayer dielectric 112, is arranged on conductive layer 102.Interlayer dielectric 112 has an opening 112o, and opening 112o exposes a part of 102a of conductive layer 102.The part 102a that barrier layer 106 contact conductive layer 102 exposes.Guide hole 104 is arranged in opening 112o.
At this, oxygen O clogs the crystal boundary in barrier layer 106, thus blocks the evolving path that leads to conductive layer 102.Further, the oxygen O of filling can compensate the impact that boundary defect brings.Thus, in the process forming guide hole 104, be usually used in the WF of tungsten guide hole deposition
6gas cannot arrive the conductive layer 102 of below via these crystal boundaries.Therefore, do not clog the conventional semiconductor structure of oxygen compared to barrier layer, in the present embodiment, the conductive layer 102 being positioned at below is not vulnerable to WF
6gas pickling, thus can avoid corroding the resistance caused and decline.Especially when conductive layer 102 be formed by copper production time all the more so.
Referring to shown in Fig. 2, is the schematic diagram of semiconductor structure 200 according to another embodiment of the present invention.With the difference part of semiconductor structure 100, semiconductor structure 200 is that barrier layer 206 is made up of an individual layer.This individual layer can comprise titanium nitride.Other elements, as the form of conductive layer 202, guide hole 204 and interlayer dielectric 212, configuration and material etc., are the counter element being similar to semiconductor structure 100.Relevant describing is omitted at this point.
Be similar to semiconductor structure 100, semiconductor structure 200 has the WF avoided for the formation of tungsten guide hole
6the advantage that the conductive layer 202 that gas causes corrodes.Compared to semiconductor structure 100, semiconductor structure 200 has more advantage because eliminating titanium barrier layer.Though be not limited to theory, titanium barrier layer is considered to the Another reason causing conductive layer 202 to corrode.Due to the strong bond knot that titanium layer shortage similarly is titanium nitride layer, the titanium in titanium layer may diffuse to conductive layer 202.Be in the example manufactured by copper at conductive layer 202, the titanium of diffusion may react with copper, forms copper-titanium compound, and causes the hole of copper.The hole of copper may be assembled, and causes the resistance of copper conductive layer 202 to decline.Compared to the semiconductor structure 100 not making it spread to block titanium in the mode of additionally clogging oxygen, as the present embodiment, omit titanium layer is more basic a kind of mode.
Stress migration test is the change for test resistance.Refer to shown in Fig. 3, Δ R is defined as the resistance after toasting 1000 hours at 250 DEG C and the difference between former resistance.If be enough to application, the value of Δ R need be equal to or less than 10%.The result that Fig. 3 demonstrates the semiconductor structure comprising the filling titanium nitride layer of aerobic or the barrier layer of titanium layer is quite good.After 1000 hours, the change of resistance is not almost had 250 DEG C of bakings.In addition, after 1000 hours, hole or the disappearance (photo not being shown in this) of copper is not observed 250 DEG C of bakings.
Referring to now shown in Fig. 4 A-Fig. 4 E, is the schematic diagram of semiconductor structure manufacture method according to an embodiment of the invention.
First, as shown in Figure 4 A, the conductive layer 302 be formed on a rectangular structure 314 is provided.Rectangular structure 314 can comprise substrate and electronic component formed thereon (such as memory body or transistor).Conductive layer 302 can comprise interconnection line, such as copper cash, aluminum steel or albronze line.Conductive layer 302 particularly can be formed by copper production.
One interlayer dielectric 312 is optionally formed on conductive layer 302, as shown in Figure 4 B.Interlayer dielectric 312 has an opening 312o, and opening 312o exposes a part of 302a of conductive layer 302.
As shown in Figure 4 C, a barrier layer 306 is formed on conductive layer 302 and interlayer dielectric 312 (if tangible one-tenth interlayer dielectric 312).The part 302a that the direct contact conductive layer 302 of barrier layer 306 exposes.In this instance, barrier layer 306 is made up of an individual layer.Barrier layer 306 can comprise tantalum, titanium, tantalum nitride, titanium nitride or tungsten nitride.Barrier layer 306 particularly can be formed with the method manufacture of such as metal organic chemical vapor deposition (MetalOrganicChemicalVaporDeposition, MOCVD) by titanium nitride.
Or as shown in Fig. 4 C ', barrier layer 306 can comprise the layer more than one deck.In this instance, barrier layer 306 is made up of one first barrier layer 308 and one second barrier layer 310.Form the step of barrier layer 306 and comprise formation first barrier layer 308 on conductive layer 302 and form the second barrier layer 310 on the first barrier layer 308.First barrier layer 308 can be formed with the method manufacture of such as physical vapour deposition (PVD) (PhysicalVaporDeposition, PVD) by titanium, and the second barrier layer 310 can be formed with the method manufacture of such as metal organic chemical vapor deposition by titanium nitride.
With oxygen molecule (O
2, with O instruction) and filling barrier layer 306, as shown in Figure 4 D.This can by providing oxygen to reach.More particularly, pressure controllable built in 6torr to 10torr, and provides oxygen with the flow velocity of 25sccm to 85sccm, maintains 10 seconds to 60 seconds.
As shown in Figure 4 E, a guide hole 304 is formed on the barrier layer 306 of filling aerobic O.In the example of tangible one-tenth interlayer dielectric 312, guide hole 304 is arranged in opening 312o.Guide hole 304 can comprise tungsten or copper.Guide hole 304 particularly can by WF
6chemical vapour deposition (CVD) (ChemicalVaporDeposition, CVD) manufacture forms.Because oxygen O is packed on the crystal boundary of barrier layer 306, WF
6gas can not arrive the conductive layer 302 of below via crystal boundary and the erosion causing conductive layer 302 even resistance decline.
Generally speaking, by with the crystal boundary of oxygen filling barrier layer, blocked the evolving path of composition material or reactivity/deposition gases, and the impact that boundary defect brings can have been compensated, thus can provide more effective barrier layer.In addition, semiconductor structure can not comprise titanium barrier layer.Now, the copper hole caused because of the titanium atom diffusion in titanium barrier layer can be avoided completely.
The above, it is only preferred embodiment of the present invention, not any pro forma restriction is done to the present invention, although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when the method and technology contents that can utilize above-mentioned announcement are made a little change or be modified to the Equivalent embodiments of equivalent variations, in every case be the content not departing from technical solution of the present invention, according to any simple modification that technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (10)
1. a semiconductor structure, is characterized in that it comprises:
One conductive layer;
One guide hole; And
One barrier layer, is arranged between this conductive layer and this guide hole, this barrier layer filling aerobic.
2. semiconductor structure according to claim 1, is characterized in that wherein said conductive layer comprises interconnection line.
3. semiconductor structure according to claim 1, is characterized in that wherein said barrier layer is made up of the individual layer comprising titanium nitride.
4. semiconductor structure according to claim 1, is characterized in that wherein said barrier layer formed both following:
One first barrier layer, is arranged on this conductive layer, and this first barrier layer comprises titanium; And
One second barrier layer, is arranged on this first barrier layer, and under being arranged on this guide hole, this second barrier layer comprises titanium nitride.
5. semiconductor structure according to claim 1, is characterized in that wherein said oxygen is packed on the crystal boundary of this barrier layer.
6. semiconductor structure according to claim 1, is characterized in that it also comprises:
One interlayer dielectric, be arranged on this conductive layer, this interlayer dielectric has an opening, and this opening exposes a part for this conductive layer,
Wherein, this barrier layer contacts this part that this conductive layer exposes, and this guide hole is arranged in the openings.
7. semiconductor structure according to claim 1, is characterized in that wherein said conductive layer is made of copper, and this guide hole is made up of tungsten, and this barrier layer comprises titanium nitride layer, the crystal boundary filling aerobic of this titanium nitride layer.
8. semiconductor structure according to claim 7, is characterized in that wherein said barrier layer also comprises a titanium layer, is arranged between this conductive layer and this titanium nitride layer.
9. a manufacture method for semiconductor structure, is characterized in that it comprises the following steps:
Form a barrier layer on a conductive layer;
This barrier layer is clogged with oxygen; And
Form a guide hole on this barrier layer of filling aerobic.
10. the manufacture method of semiconductor structure according to claim 9, it is characterized in that wherein clogging in the step of this barrier layer with oxygen, pressure controls at 6torr to 10torr, and provide oxygen with the flow velocity of 25sccm to 85sccm, maintains 10 seconds to 60 seconds.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410254140.1A CN105226050A (en) | 2014-06-09 | 2014-06-09 | Semiconductor structure and manufacture method thereof |
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| CN201410254140.1A CN105226050A (en) | 2014-06-09 | 2014-06-09 | Semiconductor structure and manufacture method thereof |
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| CN1417851A (en) * | 2002-11-25 | 2003-05-14 | 中芯国际集成电路制造(上海)有限公司 | Method of eliminating copper erosion of double-layered embedding structure |
| CN1512552A (en) * | 2002-12-30 | 2004-07-14 | 台湾积体电路制造股份有限公司 | Method for improving covering uniformity of barrier layer and intraconnection line with said barrier layer |
| CN1615538A (en) * | 2002-01-15 | 2005-05-11 | 因芬尼昂技术股份公司 | Barrier stack with improved barrier properties |
| CN1755914A (en) * | 2004-09-30 | 2006-04-05 | 台湾积体电路制造股份有限公司 | Barrier layer and fabrication method thereof |
| CN101944504A (en) * | 2009-07-08 | 2011-01-12 | 南亚科技股份有限公司 | Method for fabricating integrated circuit structures |
| CN102760694A (en) * | 2011-04-27 | 2012-10-31 | 新加坡商格罗方德半导体私人有限公司 | Method of forming oxide encapsulated conductive features |
| US20140084480A1 (en) * | 2012-09-27 | 2014-03-27 | Advanced Semiconductor Engineering, Inc. | Semiconductor package substrates having layered circuit segments and related methods |
| US20140097538A1 (en) * | 2012-10-10 | 2014-04-10 | Globalfoundries Inc. | Semiconductor device having a self-forming barrier layer at via bottom |
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2014
- 2014-06-09 CN CN201410254140.1A patent/CN105226050A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1615538A (en) * | 2002-01-15 | 2005-05-11 | 因芬尼昂技术股份公司 | Barrier stack with improved barrier properties |
| CN1417851A (en) * | 2002-11-25 | 2003-05-14 | 中芯国际集成电路制造(上海)有限公司 | Method of eliminating copper erosion of double-layered embedding structure |
| CN1512552A (en) * | 2002-12-30 | 2004-07-14 | 台湾积体电路制造股份有限公司 | Method for improving covering uniformity of barrier layer and intraconnection line with said barrier layer |
| CN1755914A (en) * | 2004-09-30 | 2006-04-05 | 台湾积体电路制造股份有限公司 | Barrier layer and fabrication method thereof |
| CN101944504A (en) * | 2009-07-08 | 2011-01-12 | 南亚科技股份有限公司 | Method for fabricating integrated circuit structures |
| CN102760694A (en) * | 2011-04-27 | 2012-10-31 | 新加坡商格罗方德半导体私人有限公司 | Method of forming oxide encapsulated conductive features |
| US20140084480A1 (en) * | 2012-09-27 | 2014-03-27 | Advanced Semiconductor Engineering, Inc. | Semiconductor package substrates having layered circuit segments and related methods |
| US20140097538A1 (en) * | 2012-10-10 | 2014-04-10 | Globalfoundries Inc. | Semiconductor device having a self-forming barrier layer at via bottom |
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