CN105224479A - For the POE drive system of POE switch - Google Patents

For the POE drive system of POE switch Download PDF

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Publication number
CN105224479A
CN105224479A CN201510718888.7A CN201510718888A CN105224479A CN 105224479 A CN105224479 A CN 105224479A CN 201510718888 A CN201510718888 A CN 201510718888A CN 105224479 A CN105224479 A CN 105224479A
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China
Prior art keywords
interface
poe
uart
switch
drive system
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CN201510718888.7A
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Chinese (zh)
Inventor
蔡教松
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Shanghai Feixun Data Communication Technology Co Ltd
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Shanghai Feixun Data Communication Technology Co Ltd
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Priority to CN201510718888.7A priority Critical patent/CN105224479A/en
Publication of CN105224479A publication Critical patent/CN105224479A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

The invention provides a kind of POE drive system for POE switch, comprise: command interaction protocol interface is connected to api interface, UART drives interface to be connected to command interaction protocol interface, architecture configuration model calling drives interface in api interface, command interaction protocol interface and UART, and api interface is used for being configured POE system; Command interaction protocol interface carries out mutual messaging protocol by UART mode for realizing between primary processor and POE system; UART drives interface for being realized the communication between primary processor and POE system by UART mode; And architecture configuration module is used for providing configuration control function.POE drive system for POE switch provided by the invention, achieve the communication between switch and POE chip, and provide reset to POE initialization, POE, many kinds of function process that special interrupt processing etc. is relevant, what achieve between switch and POE chip is effectively mutual.

Description

For the POE drive system of POE switch
Technical field
The present invention relates to field of computer technology, and in particular to a kind of POE drive system for POE switch.
Background technology
POE is the abbreviation of PowerOverEthernet (POE), is a kind of technology realizing also can powering to terminal device transmitting network data while.
Switch is as the powerful intermediate equipment of the more complicated in network transmission process, the function of POE can be added thereon, become the switch of band POE function, there is the function can also powered to PD equipment except can carrying out information transmission exchange to PD terminal device.Therefore, the communication how realized between switch and POE chip just becomes a problem that must solve.
Summary of the invention
The object of the present invention is to provide a kind of POE drive system for POE switch.
The embodiment of the present invention provides a kind of POE drive system for POE switch, it is characterized in that, comprise api interface, command interaction protocol interface, UART drive interface, architecture configuration module, wherein, described command interaction protocol interface is connected to described api interface, described UART drives interface to be connected to described command interaction protocol interface, and described architecture configuration model calling drives interface in described api interface, described command interaction protocol interface and described UART
Described api interface is used for being configured POE system;
Described command interaction protocol interface carries out mutual messaging protocol by UART mode for realizing between primary processor and described POE system;
Described UART drives interface for being realized the communication between described primary processor and described POE system by UART mode; And
Described architecture configuration module is used for providing configuration control function.
Preferably, described api interface comprises: acquisition of information interface, POE initialization interface, POE interrupt task Processing Interface, POE system configuration interface, display interface and calling interface.
Preferably, interruption that the interruption that the described POE interrupt task Processing Interface of described api interface performs comprises Port detecting unsuccessfully interrupts, port error interrupts, port is closed due to power management interruption, port is underload, port overload is interrupted and temperature warning is interrupted.
Preferably, described api interface is realized by described call instruction interaction protocol interface.
Preferably, described UART drives interface to comprise the transmission of UART message and receiving interface, reset command transmission of messages interface and POE firmware downloads interface.
Preferably, described command interaction protocol interface drives the described UART message transmission of interface to realize with receiving interface by calling described UART.
Preferably, described architecture configuration module comprises delay function, interrupts initialization function, interrupt processing function, keystroke handling function, UART initialization function.
POE drive system for POE switch provided by the invention, interface, architecture configuration module is driven to achieve communication between switch and POE chip by api interface, command interaction protocol interface, UART, and provide reset to POE initialization, POE, many kinds of function process that special interrupt processing etc. is relevant, what achieve between switch and POE chip is effectively mutual.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structured flowchart of the POE drive system for POE switch that one embodiment of the invention provides.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Fig. 1 is the structural representation of the POE drive system for POE switch that one embodiment of the invention provides.As shown in Figure 1, POE drive system 100 for POE switch comprises: API (ApplicationProgrammingInterface, application programming interface) interface 110, command interaction protocol interface 120, UART (UniversalAsynchronousReceiver/Transmitter, universal asynchronous receiving-transmitting transmitter) drive interface 130 and architecture configuration module 140, wherein, command interaction protocol interface 120 is connected to api interface 110, UART drives interface 130 to be connected to command interaction protocol interface 120, architecture configuration module 140 is connected to api interface 110, command interaction protocol interface 120 and UART drive interface 130.
In an embodiment of the present invention, api interface 110 is for being configured POE system, particularly, api interface 110 is configured for providing to the appointed function of POE system and obtains the interface function of customizing messages, comprise: (1) acquisition of information interface, for obtaining appointed information, system state or system configuration more easily; (2) POE initialization interface; (3) POE interrupt task Processing Interface; (4) POE system configuration interface, only POE default parameters be original factory arrange time perform, for by parameter configuration each in POE system be need state, then saved system configuration, be kept in non-volatile memory medium; (5) display interface, for showing POE relevant information; (6) calling interface that fixedly calls of upper strata.Preferably, api interface 110 is realized by call instruction interaction protocol interface 120.
In an embodiment of the present invention, command interaction protocol interface 120 carries out mutual messaging protocol by UART mode for realizing between primary processor and POE system, be POE system is configured or information state obtain base interface.Preferably, command interaction protocol interface 120 drives the transmission of the UART message of interface 130 to realize with receiving interface by calling UART.
In an embodiment of the present invention, UART drives interface 130 for being realized the communication between primary processor and described POE system by UART mode, mainly comprises UART message and sends and receiving interface, reset command transmission of messages interface and POE firmware downloads interface.
In an embodiment of the present invention, architecture configuration module 140 is for providing configuration control function, particularly, by architecture configuration module 140 can be extracted in POE drive system to operating system platform, content that CPU architecture is relevant, the configuration of POE drive system can also be provided to control.Preferably, architecture configuration module 140 comprises: delay function, interruption initialization function, interrupt processing function, keystroke handling function, UART initialization function.Function in architecture configuration module 140 is driven interface 130 to call by api interface 110, command interaction protocol interface 120 and UART.
pOE system initialization
Preferably, in an embodiment of the present invention, in system starting process, the POE initialization interface in api interface 110 carries out initialization for performing method as follows to POE system:
Step S1: enable POE system, controls the GPIO pin that POE system is connected with primary processor, sends enable signal.
Particularly, in an embodiment of the present invention, the method in step S1 is realized by function poeChipEnable ().
Step S2: first time checks that whether POE system state is normal, and wherein, if POE system state is normal, flow process proceeds to step S3; If POE system state is abnormal, flow process turns back to step S2.
Particularly, in an embodiment of the present invention, the method in step S2 is realized by function getSystemStatus (& sysStat).
Step S3: initialization POE interrupts, and comprises initialization POE interrupt processing task, POE interrupt processing function hooks, the initialization of POE interrupt pin and button initialization.
Particularly, in an embodiment of the present invention, the method in step S3 is realized by function poeIntInit ().
Step S4: carry out POE system setting, particularly, the userbyte byte according to reading judges whether to carry out POE system setting, if userbyte value is 0xFF, then performs POE system and arranges; Otherwise do not perform.
Particularly, in an embodiment of the present invention, the method in step S4 is realized by function poeSystemSetting ().
Step S5: POE is resetted.
Particularly, in an embodiment of the present invention, PD69200MCU chip and PD69208PoE chip are resetted, realized by function poeReset ().
Step S6: second time time checks that whether POE system state is normal, particularly, if POE system state is abnormal, prints corresponding error message, and marks the value of poeOK.
Particularly, in an embodiment of the present invention, the method in step S6 is realized by function getSystemStatus (& sysStat).
If without any mistake, then the printing started most " PoEinitialization.... " print afterwards " OK! ".
pOE system configures
Preferably, in an embodiment of the present invention, the POE system configuration interface in api interface 110 performs configuration as shown in table 1 to POE system.
Table 1
special interrupt processing
Preferably, in an embodiment of the present invention, do not affect other POE port device after being directed to some generation normally to work, but because the continuous cycle detection of POE system causes interrupting continuous generation, information is interrupted in continuous generation, produce interference to Dynamic System interface, the interruption that POE interrupt task Processing Interface therefore in api interface 110 performs comprises: the interruption that Port detecting unsuccessfully interrupts, port error interrupts, port is closed due to power management, port is underload interruption, port overload is interrupted and temperature warning is interrupted.
For above-mentioned interruption, the disposal route of POE interrupt task Processing Interface marks by the position arranging POE interrupt event mark global variable poeIntEventFlag corresponding with interrupt event the interrupt event needing to carry out special processing in the interrupt task function in architecture configuration module 140, the mask of simultaneously also cutting out this interruption arranges and makes this interruption no longer report primary processor, then in the function of 3 display POE relevant informations of bottom layer realization, before display command information, first judge whether poeIntEventFlag variable is 0, if be not 0, then first show the warning information that related interrupts occurs, in the display information of display command itself, finally open interrupt mask corresponding to event having occurred to interrupt.Therefore, for the interruption be specially treated, namely be closed after print an information in system display interface, no longer continue the information printing this interruption, although in fact this interruption is still in continuous generation, only have after the order of an execution POE information displaying, trigger and open this interrupt mask, can print again and once then close.If this interrupt event no longer occurs, then automatically no longer print this information.Such process both can solve the problem of continuous type information EVAC (Evacuation Network Computer Model) display interface, also can avoid solving constantly printing by close port and causing needing the problem of the manually opened port of user.
In addition, owing to having other interruption after partial interruption generation with occurring, therefore other adjoint with it interruption being processed needing during different interrupt processings simultaneously, needing the interruption of adjoint process as follows:
Port error interruption-this interruption powers on along with port and lower electric event, therefore close port simultaneously to occur when this interruption processes also and to power on and lower electricity interrupts, too with opening during unlatching;
Interruption that port device is underload-interrupt identical with port error;
Interruptions-this interruption of port device overload powers on and lower electric event along with port error, port, therefore to occur when this interruption processes also simultaneously close port mistake, port powers on and lower electricity interrupts, too with unlatching during unlatching.
To with interrupt process will make when POE originating port mistake, port is underload, port transships after these 3 kinds of interrupt events, port powers on and under port, electricity interrupts being affected, but disappear when causing producing these 3 kinds reasons of interrupting, after these 3 kinds interruptions no longer produce, port powers on and under port, electricity interrupts automatically recovering normal.
pOE system resets
Preferably, in an embodiment of the present invention, the reset command transmission of messages interface in UART driving interface 130 is for transmitting POE system reset command.Owing to needing a period of time to recover after POE reset, then primary processor just can receive correct response, and therefore data receiver adopts and orders different modes from other.
After sending reset command, received in 1 second and respond, (the response echo value of reset command is fixed as 0xFF to judge the 2nd the byte echo value received whether to equal 0xFF, other all order is responded echo and is equaled to send echo value, but be not equal to 0xFF) and the 7th byte privatelabel (this is masked as the mark occurring to reset, be 0 after reset) whether equal 0, if do not met, then again receive judgement; If met, receive and responds successfully, then time delay 3 seconds, then perform getSystemStatus () function and obtain system state and whether normally see, if normally, exited.
uART drives
Preferably, in an embodiment of the present invention, UART drives the UART message in interface 130 to send with receiving interface for sending and receiving UART message.According to the serial communication protocol of POE system (PD69200), the baud rate of UART is 19200bps, and data bit is 8, no parity position, and position of rest is 1, without Flow Control.Therefore in serial ports initialization function poeUartInit (), reply UART controller performs following operation:
(void)ioctl(poeConsoleFd,FIOBAUDRATE,19200)；
(void)ioctl(poeConsoleFd,FIOSETOPTIONS,OPT_RAW)；
(void)ioctl(poeConsoleFd,FIOFLUSH,0)；
(void)ioctl(poeConsoleFd,SIO_HW_OPTS_SET,CS8|CLOCAL|CREAD)；
PoeUartInit () is by called near the TTY serial equipment registration relevant position of system starting process.
When carrying out the reading or writing of serial ports, first uartSemId semaphore (1 second time-out) is obtained by semTake (), carry out reading or writing of serial ports after getting, after having read or write, semGive () discharges uartSemId semaphore.
Read or write in function at serial ports, 1 second time-out is realized by tickGet (), read or write a byte data by select () function at every turn, serial ports is read or write and is all realized by general purpose functions such as open (), read (), write (), close (), realize the response data reading PD69200, or send order data to PD69200.
Advantageously, POE drive system for POE switch provided by the invention, interface, architecture configuration module is driven to achieve communication between switch and POE chip by api interface, command interaction protocol interface, UART, and provide reset to POE initialization, POE, many kinds of function process that special interrupt processing etc. is relevant, what achieve between switch and POE chip is effectively mutual.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.

Claims (7)

1. the POE drive system for POE switch, it is characterized in that, comprise api interface, command interaction protocol interface, UART drive interface, architecture configuration module, wherein, described command interaction protocol interface is connected to described api interface, described UART drives interface to be connected to described command interaction protocol interface, and described architecture configuration model calling drives interface in described api interface, described command interaction protocol interface and described UART
Described api interface is used for being configured POE system;
Described command interaction protocol interface carries out mutual messaging protocol by UART mode for realizing between primary processor and described POE system;
Described UART drives interface for being realized the communication between described primary processor and described POE system by UART mode; And
Described architecture configuration module is used for providing configuration control function.
2. as claimed in claim 1 for the POE drive system of POE switch, it is characterized in that, described api interface comprises: acquisition of information interface, POE initialization interface, POE interrupt task Processing Interface, POE system configuration interface, display interface and calling interface.
3. as claimed in claim 2 for the POE drive system of POE switch, it is characterized in that, interruption that the interruption that the described POE interrupt task Processing Interface of described api interface performs comprises Port detecting unsuccessfully interrupts, port error interrupts, port is closed due to power management interruption, port is underload, port overload is interrupted and temperature warning is interrupted.
4., as claimed in claim 1 for the POE drive system of POE switch, it is characterized in that, described api interface is realized by described call instruction interaction protocol interface.
5. as claimed in claim 1 for the POE drive system of POE switch, it is characterized in that, described UART drives interface to comprise UART message and sends and receiving interface, reset command transmission of messages interface and POE firmware downloads interface.
6. as claimed in claim 5 for the POE drive system of POE switch, it is characterized in that, described command interaction protocol interface drives the described UART message transmission of interface to realize with receiving interface by calling described UART.
7. as claimed in claim 1 for the POE drive system of POE switch, it is characterized in that, described architecture configuration module comprises delay function, interrupts initialization function, interrupt processing function, keystroke handling function, UART initialization function.
CN201510718888.7A 2015-10-29 2015-10-29 For the POE drive system of POE switch Pending CN105224479A (en)

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Cited By (1)

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Publication number Priority date Publication date Assignee Title
CN115396243A (en) * 2022-10-27 2022-11-25 武汉思创易控科技有限公司 PoE power supply control method, storage medium and terminal

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CN104965700A (en) * 2015-06-09 2015-10-07 航天科工深圳（集团）有限公司 Method and system for implementing driving on SPI equipment under VxWorks operating system

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CN101232384A (en) * 2008-02-25 2008-07-30 福建星网锐捷网络有限公司 Method and device for testing switch with Ethernet power supply function
CN101645780A (en) * 2009-09-02 2010-02-10 杭州华三通信技术有限公司 Method and device for restoring allocation after power off and power on of power over Ethernet (POE) system
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Publication number Priority date Publication date Assignee Title
CN115396243A (en) * 2022-10-27 2022-11-25 武汉思创易控科技有限公司 PoE power supply control method, storage medium and terminal
CN115396243B (en) * 2022-10-27 2023-03-14 武汉思创易控科技有限公司 PoE power supply control method, storage medium and terminal

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