CN105206300A - Memory capable of being programmed many times and operating method thereof - Google Patents
Memory capable of being programmed many times and operating method thereof Download PDFInfo
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Abstract
The invention provides a memory capable of being programmed many times and an operating method thereof. Each storage unit in the memory at least comprises a first MOS tube, a second MOS tube and a third MOS tube, wherein the first MOS tube, the second MOS tube and the third MOS tube are single-layer floating gate transistors, when the first MOS tube and the second MOS tube are MOS tubes of the same type, the first MOS tube and the second MOS tube are source-drain penetrating tubes, when one of the first MOS tube and the second MOS tube is a PMOS tube, and the other of the first MOS tube and the second MOS tube is an NMOS tube, the NMOS tube is a source-drain penetrating tube. As the source-drain penetrating tubes are utilized, the capacitance coupling efficiency of the memory is improved, and the area of each storage unit is reduced by means of the memory structure, which is beneficial for large-capacity storage application.
Description
Technical field
The present invention relates to semiconductor storage unit field, particularly relate to a kind of time-after-time programmable memory and method of operating thereof.
Background technology
In multiple programmable embedded non-volatile memory application, mainly contain based on the eFlash of floating boom technique and eeprom memory and multiple programmable (MTP) storer based on the mono-grid technique of CMOS.
Memory technology based on floating boom technique is ripe, integrated level is high, memory capacity is large, but needs to increase mask plate and processing step compared with standard CMOS process, considerably increases the cost of SOC.
Based on the MTP storer of single grid technique and standard CMOS process completely compatible, do not increase any process costs.But the storage unit in the single grid MTP storer be employed at present is made up of 4 PMOS, and its structural representation as shown in Figure 1.Wherein, the first PMOS P1 is capacitive coupling pipe and the second PMOS P2 is electric capacity tunnelling pipe, and the 3rd PMOS P3 is memory transistor, and the 4th PMOS P4 is for selecting control tube.In order to improve the coupling efficiency of MTP storer, the source electrode of the first PMOS P1 in storage unit, drain electrode and a N trap are connected to same voltage end, make the current potential of the source of the first PMOS P1, drain terminal and a N trap identical, in like manner, the source electrode of the second PMOS P2, drain electrode and the 2nd N trap are connected to another same voltage end, make the current potential of the source of the second PMOS, drain terminal and the 2nd N trap identical.Due to this storer is programmed and erase operation time, a N trap is different with the current potential of the 2nd N trap, so need the field oxygen isolated area arranging larger area between a N trap and the 2nd N trap.This memory cell structure of larger area field oxygen isolated area that needs makes the whole area of storage unit larger, the area of the memory cell array be thus made up of the storage unit of this larger area is also very large, finally cause the area of the storer formed very large, be unfavorable for that massive store is applied.
Summary of the invention
In order under the prerequisite of capacitive coupling efficiency ensureing storage unit, reduce the area of storer as much as possible, a first aspect of the present invention provides a kind of time-after-time programmable memory.
Based on the time-after-time programmable memory that first aspect present invention provides, a second aspect of the present invention additionally provides a kind of method of operating of programmable storage.
In order to realize foregoing invention object, present invention employs following technical scheme:
A kind of time-after-time programmable memory, comprise several storage unit, each described storage unit at least comprises the first metal-oxide-semiconductor, second metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor, described first metal-oxide-semiconductor, described second metal-oxide-semiconductor and described 3rd metal-oxide-semiconductor are individual layer floating transistor, wherein, the grid of described first metal-oxide-semiconductor, the grid of described second metal-oxide-semiconductor and the grid of described 3rd metal-oxide-semiconductor link together, the source-drain electrode of described first metal-oxide-semiconductor is all connected with the first voltage end, the source-drain electrode of described second metal-oxide-semiconductor is all connected with the second voltage end, source electrode or the drain electrode of described 3rd metal-oxide-semiconductor connect tertiary voltage end, the trap holding described first metal-oxide-semiconductor is not connected with described first voltage end, the trap holding described second metal-oxide-semiconductor is not connected with described second voltage end,
When described first metal-oxide-semiconductor and described second metal-oxide-semiconductor are the metal-oxide-semiconductor of identical type, the first metal-oxide-semiconductor and described second metal-oxide-semiconductor are Punchthrough pipe;
When in described first metal-oxide-semiconductor and described second metal-oxide-semiconductor, one is PMOS, during another one NMOS tube, described NMOS tube is Punchthrough pipe.
Preferably, described first metal-oxide-semiconductor and described second metal-oxide-semiconductor are PMOS, and described first metal-oxide-semiconductor and described second metal-oxide-semiconductor are positioned at same trap.
Preferably, described first metal-oxide-semiconductor and described second metal-oxide-semiconductor are NMOS tube.
Preferably, described 3rd metal-oxide-semiconductor is NMOS tube, and described 3rd metal-oxide-semiconductor is positioned at the P trap holding described first metal-oxide-semiconductor and described second metal-oxide-semiconductor.
Preferably, described first metal-oxide-semiconductor is PMOS, and described second metal-oxide-semiconductor is NMOS tube.
Preferably, described first metal-oxide-semiconductor is NMOS tube, and described second metal-oxide-semiconductor is PMOS.
Preferably, the channel length of described Punchthrough pipe is less than or equal to 550nm.
Preferably, the channel length of described Punchthrough pipe is the most short channel length that technique allows.
Preferably, described NMOS tube is easily exhaust to manage with the nativeNMOS of transoid, and described nativeNMOS pipe, compared with standard NMOS tube, makes in the processing procedure of described nativeNMOS pipe the ion implantation process eliminating adjustment threshold voltage.
Preferably, described NMOS tube is for presetting NMOS tube, and described default NMOS tube, compared with standard NMOS tube, makes in the processing procedure of described default NMOS tube and do not carry out LDD injection and/or halo injection.
Preferably, each described storage unit also comprises the 4th metal-oxide-semiconductor, described 4th metal-oxide-semiconductor is single grid metal-oxide-semiconductor, the grid of described 4th metal-oxide-semiconductor connects the 4th voltage end, and the source electrode of described 4th metal-oxide-semiconductor or drain electrode are with the source electrode be not connected with described tertiary voltage end in described 3rd metal-oxide-semiconductor or drain connected.
Preferably, described 4th metal-oxide-semiconductor is NMOS tube or PMOS.
A kind of time-after-time programmable memory, comprise several storage unit, each described storage unit comprises a PMOS and a NMOS tube, described NMOS tube is Punchthrough pipe, the grid of described PMOS and the grid of described NMOS tube link together, and the source-drain electrode of described NMOS tube all connects the first voltage end, and the source electrode of described PMOS connects the second voltage end, the drain electrode of described PMOS connects tertiary voltage end, and the trap holding described NMOS tube is not connected with described first voltage end.
Preferably, the channel length of described Punchthrough pipe is less than or equal to 550nm.
Preferably, the channel length of described Punchthrough pipe is the most short channel length that technique allows.
Preferably, described NMOS tube is easily exhaust to manage with the nativeNMOS of transoid, and described nativeNMOS pipe, compared with standard NMOS tube, makes in the processing procedure of described nativeNMOS pipe the ion implantation process eliminating adjustment threshold voltage.
Preferably, described NMOS tube is for presetting NMOS tube, and described default NMOS tube, compared with standard NMOS tube, makes in the processing procedure of described default NMOS tube and do not carry out LDD injection and/or halo injection.
Preferably, each described storage unit also comprises selection control tube, and described selection control tube is single grid metal-oxide-semiconductor, and the grid of described selection control tube connects the 4th voltage end, and source electrode or the drain electrode of described selection control tube are connected with the drain electrode of described PMOS.
A method of operating for storer, when programming operation is performed, described method of operating comprises:
The first voltage is applied at described first voltage end, the second voltage is applied at described second voltage end, under the effect of described first voltage and described second voltage, the electronics in the source-drain electrode of described second metal-oxide-semiconductor, then through on floating boom, makes the threshold voltage of described 3rd metal-oxide-semiconductor increase;
When performing erase operation, described method of operating comprises:
Apply tertiary voltage at described first voltage end, apply the 4th voltage at described second voltage end, under the effect of described tertiary voltage and described 4th voltage, the electronics be stored on floating boom is drawn out, and the threshold voltage of described 3rd metal-oxide-semiconductor is reduced;
When performing read operation, be connected with sense amplifier in the source/drain of described 3rd metal-oxide-semiconductor be not connected with described tertiary voltage end;
Described method of operating comprises:
Cut-in voltage is applied, to control the unlatching of described 3rd metal-oxide-semiconductor at described first voltage end; Described second voltage end ground connection; Apply to read voltage at described tertiary voltage end, under the effect of described reading voltage, the information be stored in described 3rd metal-oxide-semiconductor exports described sense amplifier to, and the amplification through described sense amplifier reads the information be stored in described 3rd metal-oxide-semiconductor.
Preferably, described first metal-oxide-semiconductor, described second metal-oxide-semiconductor are NMOS tube,
When programming operation is performed, described first voltage is 5 ~ 20V, and described second voltage is 0V;
When performing erase operation, described tertiary voltage is 0V, and described 4th voltage is 5 ~ 20V.
Preferably, described storage unit also comprises the 4th metal-oxide-semiconductor, described 4th metal-oxide-semiconductor is single grid metal-oxide-semiconductor, the grid of described 4th metal-oxide-semiconductor connects the 4th voltage end, the source/drain of described 4th metal-oxide-semiconductor connects sense amplifier, and the source/drain be not connected with described sense amplifier in described 4th metal-oxide-semiconductor is connected with the source/drain be not connected with described tertiary voltage end in described 3rd metal-oxide-semiconductor;
When performing read operation, described method of operating also comprises: apply control voltage, with the storage unit described in gating belonging to the 4th metal-oxide-semiconductor at the 4th voltage end.
A method of operating for storer, when programming operation is performed, described method of operating comprises:
The first voltage is applied at described first voltage end, the second voltage is applied at described second voltage end and described tertiary voltage end, under the effect of described first voltage and described second voltage, when described NMOS tube is greater than described PMOS, electronics in the source-drain electrode of described PMOS, then through on floating boom, makes the threshold voltage of described PMOS increase; When described NMOS tube is less than described PMOS, the electronics in the source-drain electrode of described NMOS tube, then through on floating boom, makes the threshold voltage of described PMOS increase;
When performing erase operation, described method of operating comprises:
Tertiary voltage is applied at described first voltage end, the 4th voltage is applied at described second voltage end and described tertiary voltage end, under the effect of described tertiary voltage and described 4th voltage, the electronics be stored on floating boom is drawn out, and the threshold voltage of described PMOS is reduced;
When performing read operation, be connected with sense amplifier in the drain electrode of described PMOS;
Described method of operating comprises:
Apply cut-in voltage at described first voltage end, open to control described PMOS; Apply to read high voltage at described second voltage end; Under the high-tension effect of described reading, the information be stored in described PMOS exports described sense amplifier to, and the amplification through described sense amplifier reads the information be stored in described PMOS.
Preferably, each described storage unit also comprises selection control tube, described selection control tube is single grid metal-oxide-semiconductor, the grid of described selection control tube connects the 4th voltage end, source electrode or the drain electrode of described selection control tube are connected with the drain electrode of described PMOS, when performing read operation, also comprise: apply to select control voltage, to select the storage unit belonging to control tube described in gating at described 4th voltage end.
Compared to prior art, the present invention has following beneficial effect:
Time-after-time programmable memory provided by the invention, it comprises the first metal-oxide-semiconductor and the second metal-oxide-semiconductor, and the first metal-oxide-semiconductor is capacitive coupling pipe, and the second metal-oxide-semiconductor is that electric capacity satisfies poling.When the first metal-oxide-semiconductor and the second metal-oxide-semiconductor are the metal-oxide-semiconductor of identical type, this two pipe is Punchthrough pipe.When in the first metal-oxide-semiconductor and the second metal-oxide-semiconductor, one is PMOS, during another one NMOS tube, described NMOS tube is Punchthrough pipe.After source-drain electrode break-through, below metal-oxide-semiconductor grid oxygen, channel potential and source and drain current potential are consistent, and source-drain electrode freely for lower capacitor plate provides electric charge, can effectively improve the voltage couples efficiency of source and drain to floating boom as one end of mos capacitance.
And, because the trap holding the first metal-oxide-semiconductor is not connected with the first voltage end, the trap holding the second metal-oxide-semiconductor is not connected with the second voltage end, namely the trap potential holding the first metal-oxide-semiconductor is different from the current potential of the source-drain electrode of described first metal-oxide-semiconductor, the trap potential holding the second metal-oxide-semiconductor is different from the current potential of the source-drain electrode of described second metal-oxide-semiconductor, thus, when the first metal-oxide-semiconductor and the second metal-oxide-semiconductor are the transistor of same type, same trap can be adopted to hold the first metal-oxide-semiconductor and the second metal-oxide-semiconductor simultaneously, and without the need to adopting two traps to hold the first metal-oxide-semiconductor and the second metal-oxide-semiconductor respectively.Owing to adopting same trap, save the field oxygen isolated area between trap, so, such a configuration reduce the area of storage unit, and then decrease the whole area of storer.Even if when the first metal-oxide-semiconductor and the second metal-oxide-semiconductor are dissimilar transistor, the trap holding the first metal-oxide-semiconductor and the trap holding the second metal-oxide-semiconductor neither same types, namely one is N trap one is P trap, and without the need to field oxygen isolated area between N trap and P trap, thus, this structure also can reduce the area of storage unit, and then can reduce the whole area of storer.Thus, time-after-time programmable memory provided by the invention, can reduce the area of storer, is conducive to massive store application.
Accompanying drawing explanation
In order to be expressly understood prior art and the specific embodiment of the present invention, be briefly described describing the accompanying drawing needed in prior art and the specific embodiment of the invention below.Apparently, these accompanying drawings are only a part of accompanying drawings of the present invention, and those of ordinary skill in the art can also obtain other accompanying drawing under the prerequisite not paying creative work.
Fig. 1 is the structural representation of the storage unit in prior art in time-after-time programmable memory;
Fig. 2 is the structural representation of the storage unit in the time-after-time programmable memory of the embodiment of the present invention one;
Fig. 3 is the structural representation of the metal-oxide-semiconductor of Punchthrough;
Annexation schematic diagram when Fig. 4 is the time-after-time programmable memory execution programming operation in the embodiment of the present invention one;
Annexation schematic diagram when Fig. 5 is the time-after-time programmable memory execution erase operation in the embodiment of the present invention one;
Annexation schematic diagram when Fig. 6 is the time-after-time programmable memory execution read operation in the embodiment of the present invention one;
Fig. 7 is the structural representation of the storage unit in the time-after-time programmable memory of the embodiment of the present invention two;
Annexation schematic diagram when Fig. 8 is the time-after-time programmable memory execution read operation in the embodiment of the present invention two;
Fig. 9 is the structural representation of the storage unit in the time-after-time programmable memory of the embodiment of the present invention three;
Annexation schematic diagram when Figure 10 is the time-after-time programmable memory execution programming operation in the embodiment of the present invention three;
Annexation schematic diagram when Figure 11 is the time-after-time programmable memory execution erase operation in the embodiment of the present invention three;
Annexation schematic diagram when Figure 12 is the time-after-time programmable memory execution read operation in the embodiment of the present invention three;
Figure 13 be in the embodiment of the present invention four time-after-time programmable memory in the structural representation of storage unit;
Annexation schematic diagram when Figure 14 is the time-after-time programmable memory execution read operation in the embodiment of the present invention four.
Embodiment
Describe in detail below in conjunction with the specific implementation of accompanying drawing to time-after-time programmable memory provided by the invention and method of operating thereof.
It should be noted that, multiple programmable (hereinafter referred to as the MTP) storer described in the embodiment of the present invention, is the MTP storer based on single grid technique.Due to based on the MTP storer of single grid technique and standard CMOS process completely compatible, do not increase any process costs.
In addition, as everyone knows, the core component in MTP storer is memory cell array, and memory cell array is made up of several storage unit, and each storage unit is made up of multiple transistor.In embodiments of the present invention, each storage unit can be made up of, specifically see embodiment one three transistors.
Embodiment one
See Fig. 2, Fig. 2 is the memory cell structure schematic diagram in the embodiment of the present invention one, as shown in Figure 2, this storage unit comprises the first metal-oxide-semiconductor M1, second metal-oxide-semiconductor M2 and the 3rd metal-oxide-semiconductor M3, wherein, the first metal-oxide-semiconductor M1 is capacitive coupling pipe, second metal-oxide-semiconductor M2 is that electric capacity satisfies poling, and the 3rd metal-oxide-semiconductor M3 is memory transistor.It should be noted that, the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2 and the 3rd metal-oxide-semiconductor M3 are individual layer floating transistor, and the grid of the grid of the grid of the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2 and described 3rd metal-oxide-semiconductor M3 is linked together by polysilicon.Also can be understood as, these three transistor M1 to M3 share a polysilicon gate.
The source electrode of the first metal-oxide-semiconductor M1 and drain electrode connection first voltage end WLC, the source electrode of the second metal-oxide-semiconductor M2 is all connected the second voltage end BLT with drain electrode, the source electrode of the 3rd metal-oxide-semiconductor M3 or drain electrode connect tertiary voltage end BLD, and the source electrode of the 3rd metal-oxide-semiconductor M3 be not connected with tertiary voltage end BLD or drain is connected with sense amplifier.
In embodiments of the present invention, when the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 is the metal-oxide-semiconductor of identical type, this first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 is Punchthrough pipe.When in the first metal-oxide-semiconductor and the second metal-oxide-semiconductor, one is PMOS, during another one NMOS tube, described NMOS tube is Punchthrough pipe.
So-called Punchthrough pipe as shown in Figure 3.In Punchthrough pipe, the raceway groove of depletion layer below grid 305 of the depletion layer and drain region 303 that are positioned at substrate 301 source area 302 is communicated with, and forms Punchthrough effect.Thus, the channel potential of this Punchthrough pipe is identical with source-drain electrode current potential.And when Punchthrough pipe is used as coupling condenser, the source-drain electrode of this Punchthrough pipe can freely for the bottom crown of coupling condenser provides electric charge, therefore, compared to non-source and drain perforating canal, the Punchthrough pipe that the embodiment of the present invention provides can improve the voltage couples efficiency be coupled on grid effectively.Wherein, 304 represent gate oxide.Therefore, adopt Punchthrough pipe to satisfy poling as capacitive coupling pipe and electric capacity in the embodiment of the present invention, voltage couples efficiency can be improved.
In order to realize Punchthrough, the embodiment of the present invention can be realized by following several method:
The first: when selecting Punchthrough pipe, select the metal-oxide-semiconductor that channel length is shorter.Because compared with the metal-oxide-semiconductor of short channel length compared to the depletion layer of the source area of the metal-oxide-semiconductor of longer channel length and the depletion layer of drain region under the effect of high pressure, the depletion layer extended in opposite directions is easy to be communicated with, and is thus easier to produce Punchthrough effect.As a preferred embodiment of the present invention, channel length is selected to be not more than the metal-oxide-semiconductor of 550nm as Punchthrough pipe.
Further, for concrete process node generally preferred most short channel length, such as process node is the CMOS technology of 0.13 μm, and the channel length preferably adopted is 130nm.
More particularly, the embodiment of the present invention is in order to realize the Punchthrough of Punchthrough pipe, when selecting metal-oxide-semiconductor, break through the conventional practice of this area, select the channel length of predetermined model metal-oxide-semiconductor to be less than it usually adopts most short channel length, such as, for the metal-oxide-semiconductor of 3.3V, its common most short channel length is 300nm, if when the present invention selects the metal-oxide-semiconductor of 3.3V, its channel length can be the most short channel length that 0.13 μm of technique can reach for 130nm (0.13um technique is example), described 130nm.In fact, as the expansion of the embodiment of the present invention, no matter select the metal-oxide-semiconductor of what model, the most short channel length of its channel length for selecting technique to reach.
Furthermore, in order to realize Punchthrough, the channel length selected is preferably the most short channel length that CMOS technology can reach, and need not consider the model of the metal-oxide-semiconductor selected.
The second: under the prerequisite not changing standard process flows, by performing the computing of predetermined Boolean logic to layout design file, does not carry out LDD injection and/or halo injection to metal-oxide-semiconductor.
In order to be expressly understood the method, for 0.13umCMOS standard technology, in layout file, increasing MTP_mark label layer, covering metal-oxide-semiconductor (as the first metal-oxide-semiconductor M1) region needing Punchthrough.When performing boolean calculation to each level of layout file, the region that NthickLDD mask plate exposes to the open air is thick grating oxide layer metal-oxide-semiconductor LDD district and not by region that MTP_mark floor covers.Concrete Boolean calculation formula is as shown in table 1.Like this, when LDD and/or halo injects, can be stopped by mask plate by the metal-oxide-semiconductor that MTP_mark layer covers, not carry out LDD and/halo injection.
" NOTMTP-mark " in A shown in table 1 is the amendment done on standard Boolean logic basis.
Table 1
The third: when Punchthrough pipe is NMOS tube, the NMOS tube that the present embodiment is selected is preferably nativeNMOS pipe.
Described nativeNMOS pipe, compared with standard NMOS tube, makes the ion implantation process eliminating the threshold voltage that adjusts in the processing procedure of nativeNMOS pipe.
It should be noted that, the manufacture craft of described standard NMOS tube can with reference to following technological process:-->P trap injects, and--> place isolates, and----> forms grid, and----> forms side wall, and--> source and drain injection--> forms silicide--> formation first layer metal contacts and line >NMOS adjusting thresholds ion implantation in >NMOSLDD injections to select lightly doped p-type silicon chip (crystal orientation is <100>).
Because nativeNMOS manages the ion implantation process of the threshold voltage that do not adjust, so the ion concentration of the substrate surface of metal-oxide-semiconductor is very low, and the grid of metal-oxide-semiconductor applies less voltage, namely metal-oxide-semiconductor can produce and exhaust and transoid, is easy to produce Punchthrough.
It should be noted that, the type of the embodiment of the present invention to each transistor in storage unit is not construed as limiting.In the structure of the storage unit shown in Fig. 2, each transistor is NMOS tube, and this structure is only the example of the embodiment of the storage unit that the embodiment of the present invention provides, and should not be construed as the restriction to inventive embodiments.
When the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 is PMOS, now, in order to reduce the area of storage unit, the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 is positioned at same N trap.Adopt same N trap to hold the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2, without the need to arranging the field oxygen isolated area between N trap, so compared to prior art, the embodiment of the present invention reduces the area of storage unit, and then reduces reducing of whole memory area.Further, because the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 is Punchthrough pipe, its capacitive coupling efficiency is also higher, can reach the coupling efficiency of the storage unit shown in Fig. 1.
When the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 is NMOS tube, now, in order to reduce the area of storage unit, the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 is preferably placed in same P trap.And because the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 is Punchthrough pipe, its capacitive coupling efficiency is also higher, can reach the coupling efficiency of the storage unit shown in Fig. 1.
When the first metal-oxide-semiconductor M1 is PMOS, when second metal-oxide-semiconductor M2 is NMOS tube, now, first metal-oxide-semiconductor M1 is positioned at N trap, second metal-oxide-semiconductor M2 is positioned at P trap, due to different conduction-types trap between without the need to arranging an oxygen isolated area, so the area of this storage unit also can be less than the area of the storage unit shown in Fig. 1.
Equally, when the first metal-oxide-semiconductor M1 is NMOS tube, when the second metal-oxide-semiconductor M2 is PMOS, due to different conduction-types trap between without the need to arranging an oxygen isolated area, so the area of this storage unit also can be less than the area of the storage unit shown in Fig. 1, be conducive to massive store application.Further, now to the second metal-oxide-semiconductor M2, whether Punchthrough is not construed as limiting, and preferably, the second metal-oxide-semiconductor M2 is also Punchthrough pipe.
In addition, the storer that the embodiment of the present invention provides, because type capacitive coupling pipe (the first metal-oxide-semiconductor M1) and electric capacity being satisfied to poling (the second metal-oxide-semiconductor M2) does not limit, breach in prior art and PMOS can only be adopted to satisfy the restriction of poling as capacitive coupling pipe and electric capacity, can only adopt the storer of PMOS in prior art, the present invention has selectivity widely.
It should be noted that, the type of the present embodiment to the 3rd metal-oxide-semiconductor M3 does not also limit, so the 3rd described metal-oxide-semiconductor M3 can be PMOS also can be NMOS tube.
When the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2 and the 3rd metal-oxide-semiconductor are NMOS tube, from the angle reducing memory cell area, these three metal-oxide-semiconductors are all positioned at same P trap.
When the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2 and the 3rd metal-oxide-semiconductor are PMOS, from the angle reducing memory cell area, these three metal-oxide-semiconductors are all positioned at same N trap.But, in this case, also can be with and serve secondary effect.
The structure of the time-after-time programmable memory provided for the embodiment of the present invention above.
When performing programming operation to the storage unit described in embodiment one, it connects the mode of voltage as shown in Figure 4.
As shown in Figure 4, when programming operation is performed, first voltage end WLC applies the first voltage, second voltage end BLT applies the second voltage, and when the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 is NMOS tube, the first voltage is the high voltage of 5 ~ 20V, second voltage is low-voltage, further, the second voltage can be 0V voltage, for hold the first metal-oxide-semiconductor M1 a P trap W1, for holding the 2nd P trap W2 of the second metal-oxide-semiconductor M2 and the trap potential ground connection for the 3rd P trap W3 that holds the 3rd metal-oxide-semiconductor M3.It should be noted that, when programming operation is performed, tertiary voltage end BLD does not connect voltage.
In embodiments of the present invention, the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 is equivalent to the capacitor of two series connection.For convenience, the first metal-oxide-semiconductor M1 etc. is all the first capacitor, the second metal-oxide-semiconductor M2 etc. is all the second capacitor.Wherein, the source-drain electrode of the first metal-oxide-semiconductor M1 is equivalent to one end of the first capacitor, the grid of the first metal-oxide-semiconductor M1 is equivalent to the other end of the first capacitor, and the source-drain electrode of the second metal-oxide-semiconductor M2 is equivalent to one end of the second capacitor, and the grid of the second metal-oxide-semiconductor M2 is equivalent to the other end of the second capacitor.Form pressure reduction between the first voltage end WLC and the second voltage end BLT after, area due to the first metal-oxide-semiconductor M1 is greater than the area of the second metal-oxide-semiconductor M2, so, the electric capacity of the first metal-oxide-semiconductor M1 is greater than the electric capacity of the second metal-oxide-semiconductor M2, and correspondingly, the voltage difference at the first capacitor two ends is less than the voltage difference at the second capacitor two ends.
Under the effect of coupling capacitance, be coupled to the magnitude of voltage (0V) of the magnitude of voltage on floating boom higher than the second metal-oxide-semiconductor M2 source-drain electrode, and, under the effect of the first voltage and the second voltage, pressure reduction between second metal-oxide-semiconductor M2 floating boom and source-drain electrode can make the electronics generation high pressure Flowler-Nordheim of the source-drain electrode in the second metal-oxide-semiconductor M2 then wear, because electronics is worn then to high pressure place, so the gate oxide that the electronics of source-drain electrode passes the second metal-oxide-semiconductor M2 is injected on the higher floating boom of voltage.Be electronically injected to after on floating boom, the threshold voltage of the 3rd metal-oxide-semiconductor M3 raised, represents a kind of state.This completes process MTP storer being performed to programming operation.
When performing erase operation to the storage unit described in embodiment one, it connects the mode of voltage as shown in Figure 5.Annexation schematic diagram when Fig. 5 is the execution of the storage unit shown in Fig. 2 erase operation of the embodiment of the present invention one.
As shown in Figure 5, when performing erase operation, first voltage termination tertiary voltage, second voltage termination the 4th voltage, when the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 is NMOS tube, tertiary voltage is low-voltage (being preferably 0V voltage), and the 4th voltage is high voltage, the trap potential ground connection of a P trap W1, the 2nd P trap W2 and the 3rd P trap W3.Under the effect of tertiary voltage and the 4th voltage, be coupling in the voltage of the voltage on the second metal-oxide-semiconductor M2 floating boom lower than source-drain electrode place, and, voltage difference between the floating boom of the second metal-oxide-semiconductor M2 and source-drain electrode can make electronics generation high pressure Flowler-Nordheim then wear, because electronics is worn then to high pressure place, so the electronics on floating boom is injected on the higher source-drain electrode of voltage through the gate oxide of the second metal-oxide-semiconductor M2.Because the electronics on floating boom is drawn out, so the electron concentration on floating boom reduces, the threshold voltage on the 3rd metal-oxide-semiconductor M3 is reduced, represents another state, thus realize the erase operation to MTP storer.
It should be noted that, the tertiary voltage connected when performing erase operation can for the second voltage connected when performing programming operation, and the 4th voltage connected when performing erase operation can for the first voltage connected when performing programming operation.In addition, when performing erase operation, tertiary voltage end BLD does not connect voltage.
When performing read operation to the storage unit described in embodiment one, it connects the mode of voltage as shown in Figure 6.
Annexation figure when Fig. 6 is the storage unit execution read operation shown in the Fig. 2 in the embodiment of the present invention one.As shown in Figure 6, the first voltage end WLC meets DC level VDC, the second voltage termination 0V voltage, and tertiary voltage end BLD connects reading voltage, is generally supply voltage VDD, and the source terminal of the 3rd metal-oxide-semiconductor M3 connects sense amplifier.
It should be noted that, DC level VDC is for opening the 3rd metal-oxide-semiconductor M3.Its open theory is as follows: under the effect of the pressure reduction between the voltage VDC and the second voltage end BLT of the first voltage end WLC connection, floating boom can be coupled to certain voltage, and under the effect of this coupled voltages, the 3rd metal-oxide-semiconductor M3 opens.
It should be noted that, this DC level VDC can be supply voltage.Under the effect of the reading voltage of tertiary voltage end BLD connection, read current flows to sense amplifier from tertiary voltage end BLD, due to when storing different information, the threshold voltage of the 3rd metal-oxide-semiconductor M3 is different, therefore the varying in size of read current, by the amplification of sense amplifier BLS, form the signal meeting high low logic level and export, thus read the information stored in this MTP storer.
Be more than the structure of storage unit containing 3 transistors and the specific implementation of method of operating thereof.In fact, the conveniently gating of storage unit, the storage unit that the embodiment of the present invention provides can also be made up of four metal-oxide-semiconductors.Specifically see embodiment two.
Embodiment two
Storage unit described in embodiment two is on the basis of the storage unit described in embodiment one, add the 4th metal-oxide-semiconductor M4.4th metal-oxide-semiconductor M4 act as selection control tube.Its concrete structure refers to Fig. 7.
As shown in Figure 7, described storage unit comprises the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, the 3rd metal-oxide-semiconductor M3 and the 4th metal-oxide-semiconductor M4.Wherein, the effect of the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2 and the 3rd metal-oxide-semiconductor M3 is substantially identical with annexation with the effect described in embodiment one with annexation, for the sake of brevity, is not described in detail at this, specifically see the description of embodiment one.The present embodiment only carries out describing emphatically to its difference.
In embodiments of the present invention, the 4th metal-oxide-semiconductor M4 is single grid metal-oxide-semiconductor, and the grid of described 4th metal-oxide-semiconductor M4 connects the 4th voltage end WLR.
In embodiments of the present invention, the source electrode of the 3rd metal-oxide-semiconductor M3 be not connected with tertiary voltage end WLD or drain is connected with the source electrode of the 4th metal-oxide-semiconductor M4 or drain, but not is connected with sense amplifier.The source electrode that 4th metal-oxide-semiconductor M4 is not connected with the source electrode of the 3rd metal-oxide-semiconductor or drain or drain and be connected sense amplifier BLS.
It should be noted that, the type of the embodiment of the present invention to the 4th metal-oxide-semiconductor M4 does not also limit, when the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, the 3rd metal-oxide-semiconductor M3 and the 4th metal-oxide-semiconductor are NMOS tube, these four NMOS tube M1 to M4 are preferably placed in same P trap, the area of storage unit can be reduced so to greatest extent, and then reduce the area of storer.
When the structure of storage unit is for structure shown in Fig. 7, namely when storage unit also comprises the 4th metal-oxide-semiconductor M4, when performing read operation to this storage unit, as shown in Figure 8,4th voltage end WLR meets supply voltage VDD, control the 4th metal-oxide-semiconductor M4 to open, thus realize the gating to the storage unit belonging to the 4th metal-oxide-semiconductor.In this case, the voltage of the first voltage end WLC, the second voltage end BLT and tertiary voltage end BLD connection is not with identical containing connection voltage during the 4th metal-oxide-semiconductor M4.For the sake of brevity, at this, be not described in detail, specifically see Fig. 6 and corresponding text description.
It should be noted that, when to described in embodiment two MTP storer perform programming or erase operation time, its voltage annexation and the MTP in embodiment one store perform programme or erase operation time identical, for the sake of brevity, be not described in detail at this.
In above embodiment one and embodiment two, electric capacity satisfies poling and memory transistor is respectively different transistors, in fact, as another embodiment of the present invention, when to satisfy poling be not Punchthrough pipe to electric capacity, and when to satisfy poling be PMOS to this electric capacity, now, electric capacity satisfies poling and memory transistor can be same transistor.Specifically see embodiment three.
Embodiment three
Fig. 9 is the memory cell structure schematic diagram in the embodiment of the present invention three, and as shown in Figure 9, storage unit comprises NMOS tube N1 and PMOS P1, and described NMOS tube N1 and described PMOS P1 is individual layer floating transistor, and described NMOS tube N1 is Punchthrough pipe.Wherein, the grid of described NMOS tube N1 and the grid of described PMOS P1 can be linked together by polysilicon gate, the source-drain electrode of described NMOS tube N1 is all connected with the first voltage end V1, the source electrode of described PMOS P1 connects the second voltage end V2, the drain electrode of described PMOS P1 connects tertiary voltage end V3, and the drain electrode of described PMOS P1 also connects sense amplifier.Wherein, the trap holding described NMOS tube N1 is not connected with described first voltage end V1.
In embodiments of the present invention, because NMOS tube N1 is the pipe that type is different with PMOS P1, so the trap one holding these two pipes is N trap for P trap one, so without the need to arranging an oxygen isolated area between two traps, reduce the area of storage unit.Meanwhile, because a pipe is Punchthrough pipe, also capacitive coupling efficiency can be improved.
It should be noted that, the method that the present embodiment realizes Punchthrough with describe in embodiment one identical, for the sake of brevity, be not described in detail at this, specifically see the description of embodiment one.
In the embodiment of the present invention three, cause on tubule because generation FN wears then.So when the area of NMOS tube N1 is greater than PMOS P1, NMOS tube is capacitive coupling pipe, PMOS P1 is that electric capacity satisfies poling, is also memory transistor simultaneously.When the area of NMOS tube N1 is less than PMOS P1, NMOS tube is that electric capacity satisfies poling, and PMOS P1 is capacitive coupling pipe, is also memory transistor simultaneously.
When performing programming operation to the storer shown in Fig. 9, its voltage annexation as shown in Figure 10, applies the first voltage at the first voltage end V1, all applies the second voltage at described second voltage end V2 and described tertiary voltage end V3.Further, the N trap potential holding PMOS P1 is identical with the second voltage.
When the area of NMOS tube N1 is greater than the area of PMOS P1, first voltage is higher than the second voltage, and under the effect of the first voltage and the second voltage, the electronics of PMOS P1 source-drain electrode is then through on floating boom, cause the increase of PMOS P1 threshold voltage, represent a kind of state.
When the area of NMOS tube N1 is less than the area of PMOS P1, first voltage is lower than the second voltage, and under the effect of the first voltage and the second voltage, the electronics of NMOS tube N1 source-drain electrode is then through on floating boom, cause the increase of PMOS P1 threshold voltage, represent a kind of state.
When performing erase operation to the storer shown in Fig. 9, its voltage annexation as shown in figure 11, applies tertiary voltage at the first voltage end V1, all applies the 4th voltage at described second voltage end V2 and described tertiary voltage end V3.Further, the N trap potential holding PMOS P1 is identical with the 4th voltage.
When the area of NMOS tube N1 is greater than the area of PMOS P1, tertiary voltage is lower than the 4th voltage, and under the effect of tertiary voltage and the 4th voltage, the electronics on floating boom is drawn out, and causes the reduction of PMOS P1 threshold voltage, represents a kind of state.
When the area of NMOS tube N1 is less than the area of PMOS P1, tertiary voltage is higher than the 4th voltage, and under the effect of tertiary voltage and the 4th voltage, the electronics on floating boom is drawn out, and causes the reduction of PMOS P1 threshold voltage, represents a kind of state.
It should be noted that, the tertiary voltage applied when performing erase operation can for the second voltage applied when performing programming operation, and the 4th voltage applied when performing erase operation can for the first voltage applied when performing programming operation.
When performing read operation to the storer shown in Fig. 9, its voltage annexation as shown in figure 12, is connected with sense amplifier in the drain side of PMOS P1, applies cut-in voltage at the first voltage end V1, to control the unlatching of PMOS P1, apply to read high voltage at the second voltage end V2.At the cut-in voltage that the first voltage end V1 applies, by capacitive coupling effect, can be coupled certain voltage on floating boom, under the effect of this coupled voltages, PMOS P1 opens, under the high-tension effect of reading applied, the information be stored in PMOS P1 exports sense amplifier to, thus reads the storage information in this PMOS P1.It should be noted that, when performing read operation, the current potential that the substrate of this storage unit connects is equal with reading high voltage.It should be noted that, when performing read operation, what voltage tertiary voltage end V3 does not take over.
Be more than the structure of storage unit described in the embodiment of the present invention three and the embodiment of method of operating.
In order to control the unlatching of PMOS P1 better, the basis of the storage unit described in above-described embodiment three can also comprise selection control tube, opening memory transistor PMOS P1 for gating storage unit.Specifically see embodiment four.
Embodiment four
Storage unit described in embodiment four adds to select control tube M3 on the basis of the storage unit described in embodiment three.Its concrete structure refers to Figure 13.
As shown in figure 13, described storage unit comprises NMOS tube N1, PMOS P1 and selects control tube M3.Wherein, NMOS tube N1 is substantially identical with annexation with the effect described in embodiment three with annexation with the effect of PMOS P1, for the sake of brevity, is not described in detail at this, specifically see the description of embodiment three.The present embodiment only carries out describing emphatically to its difference.
In embodiments of the present invention, described selection control tube M3 is single grid metal-oxide-semiconductor, the grid of described selection control tube M3 connects the 4th voltage end V4, the source electrode of described selection control tube or drain electrode are connected with the drain electrode of described PMOS P1, the source electrode be not connected with PMOS P1 of described selection control tube or drain and be connected sense amplifier.
It should be noted that, the embodiment of the present invention does not also limit selecting the type of control tube M3, so selecting control tube M3 can be PMOS, also can be NMOS tube.
When the structure of storage unit is for structure shown in Figure 13, when performing read operation to this storage unit, as shown in figure 14, the 4th voltage end V4 applies control voltage, to control the unlatching selecting control tube M3, thus realize the gating to the storage unit belonging to this selection control tube M3.In this case, the first voltage end V1, the second voltage end V2 and tertiary voltage end V3 connect voltage with not contain select connection voltage during control tube M3 identical.For the sake of brevity, at this, be not described in detail, specifically see Figure 12 and corresponding text description.
It should be noted that, when to described in embodiment four MTP storer perform programming or erase operation time, its voltage annexation and the MTP in embodiment three store perform programme or erase operation time identical, for the sake of brevity, be not described in detail at this.
The above is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (23)
1. a time-after-time programmable memory, comprise several storage unit, it is characterized in that, each described storage unit at least comprises the first metal-oxide-semiconductor, second metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor, described first metal-oxide-semiconductor, described second metal-oxide-semiconductor and described 3rd metal-oxide-semiconductor are individual layer floating transistor, wherein, the grid of described first metal-oxide-semiconductor, the grid of described second metal-oxide-semiconductor and the grid of described 3rd metal-oxide-semiconductor link together, the source-drain electrode of described first metal-oxide-semiconductor is all connected with the first voltage end, the source-drain electrode of described second metal-oxide-semiconductor is all connected with the second voltage end, source electrode or the drain electrode of described 3rd metal-oxide-semiconductor connect tertiary voltage end, the trap holding described first metal-oxide-semiconductor is not connected with described first voltage end, the trap holding described second metal-oxide-semiconductor is not connected with described second voltage end,
When described first metal-oxide-semiconductor and described second metal-oxide-semiconductor are the metal-oxide-semiconductor of identical type, the first metal-oxide-semiconductor and described second metal-oxide-semiconductor are Punchthrough pipe;
When in described first metal-oxide-semiconductor and described second metal-oxide-semiconductor, one is PMOS, during another one NMOS tube, described NMOS tube is Punchthrough pipe.
2. storer according to claim 1, is characterized in that, described first metal-oxide-semiconductor and described second metal-oxide-semiconductor are PMOS, and described first metal-oxide-semiconductor and described second metal-oxide-semiconductor are positioned at same trap.
3. storer according to claim 1, is characterized in that, described first metal-oxide-semiconductor and described second metal-oxide-semiconductor are NMOS tube.
4. storer according to claim 3, is characterized in that, described 3rd metal-oxide-semiconductor is NMOS tube, and described 3rd metal-oxide-semiconductor is positioned at the P trap holding described first metal-oxide-semiconductor and described second metal-oxide-semiconductor.
5. storer according to claim 1, is characterized in that, described first metal-oxide-semiconductor is PMOS, and described second metal-oxide-semiconductor is NMOS tube.
6. storer according to claim 1, is characterized in that, described first metal-oxide-semiconductor is NMOS tube, and described second metal-oxide-semiconductor is PMOS.
7. the storer according to any one of claim 1-6, is characterized in that, the channel length of described Punchthrough pipe is less than or equal to 550nm.
8. the storer according to any one of claim 1-6, is characterized in that, the channel length of described Punchthrough pipe is the most short channel length that technique allows.
9. the storer according to any one of claim 1-6, it is characterized in that, described NMOS tube is easily exhaust to manage with the nativeNMOS of transoid, described nativeNMOS pipe, compared with standard NMOS tube, makes in the processing procedure of described nativeNMOS pipe the ion implantation process eliminating adjustment threshold voltage.
10. the storer according to any one of claim 1-6, is characterized in that, described NMOS tube is for presetting NMOS tube, and described default NMOS tube, compared with standard NMOS tube, makes in the processing procedure of described default NMOS tube and do not carry out LDD injection and/or halo injection.
11. storeies according to any one of claim 1-6, it is characterized in that, each described storage unit also comprises the 4th metal-oxide-semiconductor, described 4th metal-oxide-semiconductor is single grid metal-oxide-semiconductor, the grid of described 4th metal-oxide-semiconductor connects the 4th voltage end, and the source electrode of described 4th metal-oxide-semiconductor or drain electrode are with the source electrode be not connected with described tertiary voltage end in described 3rd metal-oxide-semiconductor or drain connected.
12. storeies according to claim 11, is characterized in that, described 4th metal-oxide-semiconductor is NMOS tube or PMOS.
13. 1 kinds of time-after-time programmable memories, comprise several storage unit, it is characterized in that, each described storage unit comprises a PMOS and a NMOS tube, described NMOS tube is Punchthrough pipe, the grid of described PMOS and the grid of described NMOS tube link together, the source-drain electrode of described NMOS tube all connects the first voltage end, the source electrode of described PMOS connects the second voltage end, the drain electrode of described PMOS connects tertiary voltage end, and the trap holding described NMOS tube is not connected with described first voltage end.
14. storeies according to claim 13, is characterized in that, the channel length of described Punchthrough pipe is less than or equal to 550nm.
15. storeies according to claim 13, is characterized in that, the channel length of described Punchthrough pipe is the most short channel length that technique allows.
16. storeies according to claim 13, it is characterized in that, described NMOS tube is easily exhaust to manage with the nativeNMOS of transoid, described nativeNMOS pipe, compared with standard NMOS tube, makes in the processing procedure of described nativeNMOS pipe the ion implantation process eliminating adjustment threshold voltage.
17. storeies according to claim 13, is characterized in that, described NMOS tube is for presetting NMOS tube, and described default NMOS tube, compared with standard NMOS tube, makes in the processing procedure of described default NMOS tube and do not carry out LDD injection and/or halo injection.
18. storeies according to any one of claim 13-17, it is characterized in that, each described storage unit also comprises selection control tube, described selection control tube is single grid metal-oxide-semiconductor, the grid of described selection control tube connects the 4th voltage end, and source electrode or the drain electrode of described selection control tube are connected with the drain electrode of described PMOS.
The method of operating of 19. 1 kinds of storeies as described in any one of claim 1-12, is characterized in that, when programming operation is performed, described method of operating comprises:
The first voltage is applied at described first voltage end, the second voltage is applied at described second voltage end, under the effect of described first voltage and described second voltage, the electronics in the source-drain electrode of described second metal-oxide-semiconductor, then through on floating boom, makes the threshold voltage of described 3rd metal-oxide-semiconductor increase;
When performing erase operation, described method of operating comprises:
Apply tertiary voltage at described first voltage end, apply the 4th voltage at described second voltage end, under the effect of described tertiary voltage and described 4th voltage, the electronics be stored on floating boom is drawn out, and the threshold voltage of described 3rd metal-oxide-semiconductor is reduced;
When performing read operation, be connected with sense amplifier in the source/drain of described 3rd metal-oxide-semiconductor be not connected with described tertiary voltage end;
Described method of operating comprises:
Cut-in voltage is applied, to control the unlatching of described 3rd metal-oxide-semiconductor at described first voltage end; Described second voltage end ground connection; Apply to read voltage at described tertiary voltage end, under the effect of described reading voltage, the information be stored in described 3rd metal-oxide-semiconductor exports described sense amplifier to, and the amplification through described sense amplifier reads the information be stored in described 3rd metal-oxide-semiconductor.
The method of operating of 20. time-after-time programmable memories according to claim 19, is characterized in that, described first metal-oxide-semiconductor, described second metal-oxide-semiconductor are NMOS tube,
When programming operation is performed, described first voltage is 5 ~ 20V, and described second voltage is 0V;
When performing erase operation, described tertiary voltage is 0V, and described 4th voltage is 5 ~ 20V.
The method of operating of 21. time-after-time programmable memories according to claim 19, it is characterized in that, described storage unit also comprises the 4th metal-oxide-semiconductor, described 4th metal-oxide-semiconductor is single grid metal-oxide-semiconductor, the grid of described 4th metal-oxide-semiconductor connects the 4th voltage end, the source/drain of described 4th metal-oxide-semiconductor connects sense amplifier, and the source/drain be not connected with described sense amplifier in described 4th metal-oxide-semiconductor is connected with the source/drain be not connected with described tertiary voltage end in described 3rd metal-oxide-semiconductor;
When performing read operation, described method of operating also comprises: apply control voltage, with the storage unit described in gating belonging to the 4th metal-oxide-semiconductor at the 4th voltage end.
The method of operating of 22. 1 kinds of storeies as described in any one of claim 13-18, is characterized in that, when programming operation is performed, described method of operating comprises:
The first voltage is applied at described first voltage end, the second voltage is applied at described second voltage end and described tertiary voltage end, under the effect of described first voltage and described second voltage, when described NMOS tube is greater than described PMOS, electronics in the source-drain electrode of described PMOS, then through on floating boom, makes the threshold voltage of described PMOS increase; When described NMOS tube is less than described PMOS, the electronics in the source-drain electrode of described NMOS tube, then through on floating boom, makes the threshold voltage of described PMOS increase;
When performing erase operation, described method of operating comprises:
Tertiary voltage is applied at described first voltage end, the 4th voltage is applied at described second voltage end and described tertiary voltage end, under the effect of described tertiary voltage and described 4th voltage, the electronics be stored on floating boom is drawn out, and the threshold voltage of described PMOS is reduced;
When performing read operation, be connected with sense amplifier in the drain electrode of described PMOS;
Described method of operating comprises:
Apply cut-in voltage at described first voltage end, open to control described PMOS; Apply to read high voltage at described second voltage end; Under the high-tension effect of described reading, the information be stored in described PMOS exports described sense amplifier to, and the amplification through described sense amplifier reads the information be stored in described PMOS.
23. methods of operating according to claim 22, it is characterized in that, each described storage unit also comprises selection control tube, described selection control tube is single grid metal-oxide-semiconductor, the grid of described selection control tube connects the 4th voltage end, and source electrode or the drain electrode of described selection control tube are connected with the drain electrode of described PMOS, when performing read operation, also comprise: apply to select control voltage, to select the storage unit belonging to control tube described in gating at described 4th voltage end.
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| US7483310B1 (en) * | 2006-11-02 | 2009-01-27 | National Semiconductor Corporation | System and method for providing high endurance low cost CMOS compatible EEPROM devices |
| CN101329913A (en) * | 2007-06-18 | 2008-12-24 | 隆智半导体公司 | CMOS compatible single-layer polysilicon non-volatile memory |
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