CN105204248A - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN105204248A CN105204248A CN201510653969.3A CN201510653969A CN105204248A CN 105204248 A CN105204248 A CN 105204248A CN 201510653969 A CN201510653969 A CN 201510653969A CN 105204248 A CN105204248 A CN 105204248A
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- fan
- capacitance compensation
- array base
- base palte
- layer
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13458—Terminal pads
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
Abstract
The invention discloses an array substrate and a display device. A capacitance compensation film layer is arranged in a non-display region of the array substrate, wherein the capacitance compensation film layer and fanout wires are arranged on different layers. Direct-facing areas between the capacitance compensation film layer and all the fanout wires are gradually increased according to the sequence of length, from big to small, of the fanout wires, the direct-facing areas between the long fanout wires and the capacitance compensation film layer are relatively small, the direct-facing areas between the short fanout wires and the capacitance compensation film layer are relatively big, and then the products of resistance of the long fanout wires and corresponding compensation capacitance are approximately equal to those of resistance of the short fanout wires and corresponding compensation capacitance. Resistance difference can be reduced by means of the design scheme, it is ensured that the products of resistance of all the fanout wires and the corresponding compensation capacitance are approximately equal, the phenomenon that signals of the fanout wires are not uniform is improved, and the uniformity of picture display is promoted. It can be avoided that extra wiring space is additionally arranged, and the narrow-bezel requirement is guaranteed.
Description
Technical field
The present invention relates to display technique field, particularly relate to a kind of array base palte and display device.
Background technology
Current fanout area (fanout) span that connects up is larger, when being connected up to both sides by drive IC, because the position of pixel cell is different, in causing fanout to connect up, every bar fan-out track lengths may be different, form resistance difference, thus cause the signal delay difference on each fan-out cabling and make inequality signal one, and then affect the homogeneity of picture display; Can be equal for being close to by the length adjustment of all fan-out cablings by the mode increasing fan-out track lengths in prior art, thus reduce resistance difference, but need larger wiring space, affect the design of narrow frame.
Summary of the invention
The embodiment of the present invention provides a kind of array base palte and display device, in order to solve the problem that on the fan-out cabling that exists in prior art, signal lag there are differences on the basis ensureing narrow frame.
The embodiment of the present invention is by the following technical solutions:
A kind of array base palte, comprise viewing area and non-display area, wherein, the non-display area of described array base palte is provided with the fan-out cabling of many different lengths, and the non-display area of described array base palte also comprises:
The capacitance compensation rete arranged with the different layer of described fan-out cabling, wherein, the right opposite of described capacitance compensation rete and every bar fan-out cabling amasss and increases gradually according to the length order from large to small of described fan-out cabling.
This programme utilizes the right opposite between capacitance compensation rete from every bar fan-out cabling to amass and forms different building-out capacitors, for the fan-out cabling that length is longer, long-pending relatively little with the right opposite of capacitance compensation rete, namely building-out capacitor is less, for the fan-out cabling that length is shorter, amass relatively large with the right opposite of capacitance compensation rete, namely building-out capacitor is larger, like this, the resistance of the fan-out cabling that the product of the less building-out capacitor that the resistance of the fan-out cabling that guarantee length is longer is corresponding with it is shorter with length is close to equal with the product of its corresponding larger building-out capacitor, reduce resistance difference, thus, the product of the resistance of each fan-out cabling building-out capacitor corresponding with it is made to be close to equal, namely ensure that RC value is close to equal, improve the inhomogenous problem of fan-out trace signal, and then improve picture display homogeneity.
Preferably, described capacitance compensation rete amasss with the length of corresponding fan-out cabling to the right opposite of every bar fan-out cabling is inversely prroportional relationship.
The program can make the resistance of each fan-out cabling equal with corresponding capacitance product.
Preferably, the fan-out cabling that in described many fan-out cablings, length is the longest is with reference to fan-out cabling, and the span that the right opposite of the fan-out cabling that described capacitance compensation rete is the longest with length in described many fan-out cablings amasss is: 8 μm
2-12 μm
2.
In this scenario, amass with the right opposite of the longest fan-out cabling the scale-up factor determined in inversely prroportional relationship, the area coverage of capacitance compensation rete can be reduced as far as possible, and then, reduce building-out capacitor, ensure less signal delay.
Preferably, the part edge of described capacitance compensation rete has saw-tooth like pattern.
Capacitance compensation rete in the program has saw-tooth like pattern, thus ensures that the building-out capacitor formed is more stable.
Preferably, the orthogonal projection of described capacitance compensation rete on described array base palte only covers described fan-out cabling, and pattern is continuous.
The shape of the capacitance compensation rete in the program can ensure that the building-out capacitor formed is more accurate.
Preferably, the material of described capacitance compensation rete is transparent conductive oxide.
In this scenario, transparent conductive oxide is conventional material in array base palte, better can form building-out capacitor.
Preferably, the viewing area of described array base palte is provided with common electrode layer; Described capacitance compensation rete and described common electrode layer are arranged with layer, are formed with one-time process; Or
The viewing area of described array base palte is provided with pixel electrode layer, and described capacitance compensation rete and described pixel electrode layer are arranged with layer, are formed with one-time process.
In this scenario, capacitance compensation rete and common electrode layer or pixel electrode layer are arranged with layer, thus, avoid and additionally prepare the operation of rete as capacitance compensation rete.
Preferably, the material of described capacitance compensation rete is metal or alloy.
In this scenario, Metal and Alloy is conventional material in array base palte, better can form building-out capacitor.
Preferably, the different layer in the viewing area of described array base palte is provided with source-drain layer and grid line; Wherein, described fan-out cabling and source-drain layer are arranged with layer, are formed with one-time process; Described capacitance compensation rete and grid line are arranged with layer, are formed with one-time process; Or
Described fan-out cabling and described grid line are arranged with layer, are formed with one-time process; Described capacitance compensation rete and source-drain layer are arranged with layer, are formed with one-time process.
In this scenario, capacitance compensation rete and source, drain electrode or grid line are arranged with layer, thus, avoid and additionally prepare the operation of rete as capacitance compensation rete.
A kind of display device, comprises described array base palte.
Because this display device comprises above-mentioned array base palte, therefore, it is possible to well improve the problem of inequality signal one, and then improve picture display homogeneity.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly introduced, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The structural representation of a kind of array base palte that Fig. 1 provides for the embodiment of the present invention;
Fig. 2 (a) is for going out the enlarged drawing of cabling 11 region with Fig. 1 middle fan;
Fig. 2 (b) is the n bar circuit diagram equivalence of fan-out cabling 111-fan-out cabling 11n difference being become each circuit component;
Fig. 3 is one of film layer structure schematic diagram of capacitance compensation rete;
Fig. 4 is the film layer structure schematic diagram two of capacitance compensation rete;
One of diagrammatic cross-section that Fig. 5 (a) is rete position, capacitance compensation rete place;
Fig. 5 (b) is the diagrammatic cross-section two of rete position, capacitance compensation rete place;
Fig. 6 (a) is the diagrammatic cross-section three of rete position, capacitance compensation rete place;
Fig. 6 (b) is the diagrammatic cross-section four of rete position, capacitance compensation rete place.
Embodiment
In order to make the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the present invention is described in further detail, and obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making other embodiments all obtained under creative work prerequisite, belong to the scope of protection of the invention.
Below by specific embodiment, technical scheme involved in the present invention is described in detail, the present invention includes but be not limited to following examples.
As shown in Figure 1, for the structural representation of a kind of array base palte that the embodiment of the present invention provides, this array base palte 10 is restricted to the viewing area A (zone line of array base palte, slanted bar line is filled) and non-display area B (fringe region of array base palte), wherein, the non-display area B of this array base palte 10 is provided with the fan-out cabling 11 of many different lengths, one end of every bar fan-out cabling 11 connects drive IC or control IC, and the other end connects the circuit being positioned at the viewing area A of array base palte.The non-display area B of this array base palte 10 also comprises: the capacitance compensation rete 12 arranged with the different layer of fan-out cabling 11, wherein, capacitance compensation rete 12 amasss S with the right opposite of every bar fan-out cabling 11 and increases gradually according to the length order from large to small of fan-out cabling 11.In embodiments of the present invention, capacitance compensation rete is positioned at the orthogonal projection scope of color membrane substrates at array base palte of follow-up covering.
Particularly, with reference to the partial enlarged drawing going out cabling 11 region with Fig. 1 middle fan shown in Fig. 2 (a), part fan-out cabling 11 is only shown in Fig. 2 (a).In FIG, fan-out cabling 11 is symmetrically arranged, and the length of every bar fan-out cabling 11 is different according to the distance of its distance circuit, generally, all can be arranged to by fan-out cabling 11 bend font near drive IC or control IC.Capacitance compensation rete 12 can be positioned at above or below the rete of fan-out cabling 11 place, to be positioned at top in Fig. 2 (a).The length of fan-out cabling 111 is greater than the length of fan-out cabling 112, and capacitance compensation rete 12 and the right opposite of fan-out cabling 111 amass S1 and be less than capacitance compensation rete 12 and amass S2 with the right opposite of fan-out cabling 112.The right opposite that other fan-out cabling 11 and electric capacity supplement rete 12 amasss and also increases gradually according to the length order from large to small of fan-out cabling 11.Wherein, for different fan-out cabling, the difference that the right opposite that itself and electric capacity supplement rete 12 amasss can equally also can not wait.
For the ease of understanding, as Fig. 2 (b) illustrates n bar circuit diagram fan-out cabling 111-fan-out cabling 11n being converted respectively to each circuit component, wherein, fan-out cabling 111 equivalence becomes resistance R1, and the building-out capacitor that capacitance compensation rete and its right opposite amass formation is C1; Fan-out cabling 112 equivalence becomes resistance R2, and the building-out capacitor that capacitance compensation rete and its right opposite amass formation is C2; The like, fan-out cabling 11n equivalence becomes resistance Rn, the building-out capacitor that capacitance compensation rete and its right opposite amass formation is Cn, thus, (i.e. building-out capacitor size) is amassed by the right opposite of adjustment capacitance compensation rete and every bar fan-out cabling, ensure R1*C1=R2*C2 ...=Rn*Cn, thus, improve the problem of the signal homogeneity of every bar fan-out cabling.
By arranging capacitance compensation rete at the non-display area of above-mentioned array base palte, form the right opposite differed in size respectively to amass with every bar fan-out cabling, due to fan-out cabling electrical connection data line or grid line, therefore, can utilize the voltage of fan-out cabling side that the right opposite between corresponding fan-out cabling and capacitance compensation rete is amassed to locate to form building-out capacitor, this right opposite long-pending (i.e. building-out capacitor) increases gradually according to the length order from large to small of fan-out cabling, thus, building-out capacitor corresponding to every bar fan-out cabling is made to be close to equal with the product of the resistance of this fan-out cabling, i.e. RC value approximately equal, improve the problem of the inequality signal one brought due to the resistance difference that causes of fan-out track lengths difference, the further homogeneity improving picture display.
Preferably, considering to ensure the building-out capacitor that every bar fan-out cabling is corresponding equal as far as possible with the product RC of the resistance of this fan-out cabling, namely jointly can equal a constant K, R*C=K.Due to R=ρ * L/s, C=ε * S/d, wherein, for every bar fan-out cabling, the cross-sectional area s of impedance ρ, fan-out cabling, DIELECTRIC CONSTANT ε and the spacing d between fan-out cabling with capacitance compensation rete are all equal, and therefore, it is relevant that final every RC value of bar fan-out cabling and the length L of fan-out cabling and right opposite amass S, thus, L*S=K.Namely the length L that capacitance compensation rete 12 and the right opposite of every bar fan-out cabling 11 amass S and corresponding fan-out cabling is inversely prroportional relationship.
Preferably, in embodiments of the present invention, the capacitance compensation rete set up is to form building-out capacitor with corresponding fan-out cabling, thus improve the problem of signal homogeneity between different fan-out cabling, but, in fact increasing building-out capacitor can cause the signal delay of every bar fan-out cabling to become large, in order to while improving signal homogeneity, also less signal delay to be ensured, the value of building-out capacitor is the smaller the better, generally be not more than 0.001pf, therefore, need the right opposite of capacitance compensation rete and every bar fan-out cabling to amass the little as far as possible of setting.In actual design process, the general building-out capacitor C determining this fan-out cabling with the fan-out cabling that length is the longest, this building-out capacitor is building-out capacitor minimum in the building-out capacitor that all fan-out cablings are corresponding, and therefore, the right opposite of the building-out capacitor that the fan-out cabling that this length is the longest is corresponding amasss minimum.Wherein, the span that in capacitance compensation rete and many fan-out cablings, the right opposite of the fan-out cabling that length is the longest amasss S is: 8 μm
2-12 μm
2.The right opposite of other fan-out cabling and capacitance compensation rete is long-pending to be calculated accordingly.Preferably, the value that in capacitance compensation rete and many fan-out cablings, the right opposite of the fan-out cabling that length is the longest amasss S can be 10 μm
2.
One is capacitance compensation film layer structure preferably, and as shown in Figure 3, the part edge of capacitance compensation rete 12 has saw-tooth like pattern, thus, the stability of the building-out capacitor formed can be ensured, and easily realize.
Another kind is capacitance compensation film layer structure preferably, and as shown in Figure 4, the orthogonal projection of capacitance compensation rete 12 on array base palte 10 only covers fan-out cabling 11, and pattern is continuous.Thus, ensure that the building-out capacitor formed is comparatively accurate.
Preferably, the material of capacitance compensation rete 12 is transparent conductive oxide.Particularly, this transparent conductive oxide can be indium tin oxide ITO.
Preferably, for the material of capacitance compensation rete 12 for transparent conductive oxide, as shown in Fig. 5 (a), for one of the diagrammatic cross-section of rete position, capacitance compensation rete 12 place, the viewing area of array base palte 10 is provided with common electrode layer 13, capacitance compensation rete 12 and common electrode layer 13 are arranged with layer, form building-out capacitor, between capacitance compensation rete 12 and fan-out cabling 11, have insulation course with the fan-out cabling 11 arranged with layer with source-drain layer 15 or grid line 16 being positioned at lower floor.Particularly, the capacitance compensation rete 12 shown in Fig. 5 (a) can be formed with common electrode layer 13 simultaneously, namely carries out patterning at the non-display area of array base palte 10 to transparent conductive oxide film layer, the capacitance compensation rete 12 needed for formation.In addition, can be continuous print between this capacitance compensation rete 12 and common electrode layer 13, thus utilize the electric potential signal of fan-out cabling and the electric potential signal of common electrode layer to form building-out capacitor; Also can be discontinuous, the electric potential signal and the zero potential signal of self that only rely on fan-out cabling form building-out capacitor.The continuity of following capacitance compensation rete 12 and the rete arranged with layer in like manner, repeats no more.
Or, as shown in 5 (b), for the diagrammatic cross-section two of rete position, capacitance compensation rete 12 place, the viewing area of array base palte 10 is provided with pixel electrode layer 14, capacitance compensation rete 12 and pixel electrode layer 14 are arranged with layer, form building-out capacitor with the fan-out cabling 11 arranged with layer with source-drain layer 15 or grid line 16 being positioned at lower floor, between capacitance compensation rete 12 and fan-out cabling 11, have insulation course.Particularly, the capacitance compensation rete 12 shown in Fig. 5 (b) can be formed with pixel electrode layer 14 simultaneously, namely carries out patterning at the non-display area of array base palte 10 to transparent conductive oxide film layer, the capacitance compensation rete 12 needed for formation.It should be noted that, when capacitance compensation rete 12 is arranged with layer with pixel electrode layer 14, this capacitance compensation rete 12 cannot be electrically connected with pixel electrode layer 14, and this capacitance compensation rete 12 can be directly unsettled or be connected to common electrode layer by via hole.
Preferably, the material of capacitance compensation rete 12 is metal or alloy.It should be noted that, consider that metal is lighttight, therefore, in order to ensure the transmitance of substrate, when the material of capacitance compensation rete 12 is metal or alloy, this capacitance compensation rete 12 can be only the structure shown in Fig. 4.
Preferably, the material of capacitance compensation rete 12 is metal is example, as shown in Fig. 6 (a), for the diagrammatic cross-section three of rete position, capacitance compensation rete 12 place, the different layer in viewing area of array base palte 10 is provided with source-drain layer 15 and grid line 16, fan-out cabling 11 and source-drain layer 15 are arranged with layer, and capacitance compensation rete 12 and grid line 16 are arranged with layer, between capacitance compensation rete 12 and fan-out cabling 11, have insulation course.Particularly, the capacitance compensation rete 12 shown in Fig. 6 (a) can be formed with grid line 16 simultaneously, namely carries out patterning at the non-display area of array base palte 10 to the first metallic diaphragm for the formation of grid line, the capacitance compensation rete 12 needed for formation.
Or, as shown in Fig. 6 (b), for the diagrammatic cross-section four of rete position, capacitance compensation rete 12 place, the different layer in viewing area of array base palte 10 is provided with source-drain layer 15 and grid line 16, fan-out cabling 11 and grid line 16 are arranged with layer, capacitance compensation rete 12 and source-drain layer 15 are arranged with layer, between capacitance compensation rete 12 and fan-out cabling 11, have insulation course.Particularly, capacitance compensation rete 12 shown in Fig. 6 (b) can be formed with source-drain layer 15 simultaneously, namely at the non-display area of array base palte 10, patterning is carried out, the capacitance compensation rete 12 needed for formation to the second metallic diaphragm for the formation of data line and source, drain electrode.
In addition, in embodiments of the present invention, the capacitance compensation rete 12 of setting is on the not impact of existing fan-out cabling 11, and fan-out cabling 11 still can be arranged according to existing wire laying mode.
In the above-described embodiment, by laying the capacitance compensation rete arranged with the different layer of fan-out cabling, be embodied as every bar fan-out cabling and set up corresponding building-out capacitor, and, the building-out capacitor formed increases gradually according to the length order from large to small of fan-out cabling, thus, ensure that the building-out capacitor that every bar fan-out cabling is corresponding is close to equal with the product of the resistance of this fan-out cabling as far as possible, ensure the homogeneity of the signal of every bar fan-out cabling, and then, improve the homogeneity of the display effect of fan-out cabling place array base palte.Secondly, by technical scheme of the present invention, resistance difference out-phase etc. need not be ensured by the mode of the length of adjustment fan-out cabling, avoid increase wiring space, ensure that the demand of narrow frame.
In addition, the embodiment of the present invention additionally provides a kind of display device, comprise the array base palte involved by above-described embodiment, wherein, this display device can be any product or parts with Presentation Function such as liquid crystal panel, mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), wearable device, Medical Devices, navigating instrument.Other requisite ingredient for this display device is and will be understood by those skilled in the art that to have, and does not repeat at this, also should as limitation of the present invention.
Although describe the preferred embodiments of the present invention, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of the scope of the invention.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. an array base palte, comprises viewing area and non-display area, and wherein, the non-display area of described array base palte is provided with the fan-out cabling of many different lengths, and it is characterized in that, the non-display area of described array base palte also comprises:
The capacitance compensation rete arranged with the different layer of described fan-out cabling, wherein, the right opposite of described capacitance compensation rete and every bar fan-out cabling amasss and increases gradually according to the length order from large to small of described fan-out cabling.
2. array base palte as claimed in claim 1, it is characterized in that, it is inversely prroportional relationship that described capacitance compensation rete amasss with the length of corresponding fan-out cabling to the right opposite of every bar fan-out cabling.
3. array base palte as claimed in claim 2, is characterized in that, the span that the right opposite of the fan-out cabling that described capacitance compensation rete is the longest with length in described many fan-out cablings amasss is: 8 μm
2-12 μm
2.
4. the array base palte as described in any one of claim 1-3, is characterized in that, the part edge of described capacitance compensation rete has saw-tooth like pattern.
5. the array base palte as described in any one of claim 1-3, is characterized in that, the orthogonal projection of described capacitance compensation rete on described array base palte only covers described fan-out cabling, and pattern is continuous.
6. array base palte as claimed in claim 1, it is characterized in that, the material of described capacitance compensation rete is transparent conductive oxide.
7. array base palte as claimed in claim 6, it is characterized in that, the viewing area of described array base palte is provided with common electrode layer, and described capacitance compensation rete and described common electrode layer are arranged with layer, are formed with one-time process; Or
The viewing area of described array base palte is provided with pixel electrode layer, and described capacitance compensation rete and described pixel electrode layer are arranged with layer, are formed with one-time process.
8. array base palte as claimed in claim 1, it is characterized in that, the material of described capacitance compensation rete is metal or alloy.
9. array base palte as claimed in claim 8, it is characterized in that, the different layer in viewing area of described array base palte is provided with source-drain layer and grid line;
Wherein, described fan-out cabling and described source-drain layer are arranged with layer, are formed with one-time process; Described capacitance compensation rete and grid line are arranged with layer, are formed with one-time process; Or
Described fan-out cabling and described grid line are arranged with layer, are formed with one-time process; Described capacitance compensation rete and source-drain layer are arranged with layer, are formed with one-time process.
10. a display device, is characterized in that, comprises the arbitrary described array base palte of claim 1-9.
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| CN201510653969.3A CN105204248A (en) | 2015-10-10 | 2015-10-10 | Array substrate and display device |
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| CN201510653969.3A CN105204248A (en) | 2015-10-10 | 2015-10-10 | Array substrate and display device |
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| CN107092146A (en) * | 2017-05-03 | 2017-08-25 | 友达光电股份有限公司 | Array substrate |
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| CN107633812A (en) * | 2017-10-30 | 2018-01-26 | 武汉天马微电子有限公司 | A kind of display panel and display device |
| WO2018036141A1 (en) * | 2016-08-22 | 2018-03-01 | 京东方科技集团股份有限公司 | Fan-out wire structure, display device comprising same, and fan-out wiring method |
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