CN105202372A - Signal conditioner - Google Patents
Signal conditioner Download PDFInfo
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- CN105202372A CN105202372A CN201510566739.3A CN201510566739A CN105202372A CN 105202372 A CN105202372 A CN 105202372A CN 201510566739 A CN201510566739 A CN 201510566739A CN 105202372 A CN105202372 A CN 105202372A
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Abstract
The invention discloses a signal conditioner. The signal conditioner comprises a current loop receiving circuit, a temperature compensation unit, a signal amplification circuit and a low-pass filter circuit, wherein the current loop receiving circuit is used for receiving monitoring signals for monitoring whether a pipeline leaks or not; the temperature compensation unit is used for determining the signal amplification gain required at the real-time environment temperature; the signal amplification circuit is connected with the current loop receiving circuit and the temperature compensation unit and used for amplifying the monitoring signals according to the signal amplification gain; the low-pass filter circuit is connected with the signal amplification circuit and used for filtering signals higher than preset frequency out of the monitoring signals. Thus, a photoelectric coupling manner is adopted for current loop receiving of the signal conditioner, on the basis that current signals output by a pressure transmitter are received and converted into voltage signals, high-reliability signal transmission and effective electric isolation of the pressure transmitter and the signal conditioner are provided, and the probability of circuit damage caused by mutual interference is greatly decreased.
Description
Technical field
The present invention relates to electronic technology field, particularly relate to a kind of signal conditioner.
Background technique
The safe operation of oil and gas pipes becomes focus just gradually, and the safe operation of pipeline in the leakage serious threat caused by reasons such as burn into damage from third-parties.Line leakage system is the automatic system for monitoring pipeline fluid leakage situation.Leakage monitoring system needs the pressure being gathered fluid in pipeline by pressure transmitter, judges whether pipeline leaks according to the situation of change of pressure.
In leakage monitoring system, the output signal of site pressure transmitter is adulterated more noise usually, and is not suitable for directly being used as data analysis and process, needs the pretreatment through signal conditioner could input signal collection terminal.The performance of signal conditioner has material impact to the stability of line leakage system, accuracy.Along with applying of leakage monitoring system, under system often operates in outdoor rugged environment, signal conditioner does not consider the impact of ambient temperature on monitor signal, thus causes the monitor signal after processing inaccurate, then causes monitoring result inaccurate.
Therefore, signal conditioner of the prior art exists because not considering that ambient temperature causes the inaccurate technical problem of monitor signal after processing to the impact of monitor signal.
Summary of the invention
The embodiment of the present invention by providing a kind of signal conditioner, in order to solve that signal conditioner in prior art exists because not considering that ambient temperature causes the inaccurate technical problem of monitor signal after processing to the impact of monitor signal.
Embodiments provide a kind of signal conditioner, it is characterized in that, comprising:
Electric current loop receiving circuit, for receiving the current signal that pressure transmitter sends, and is converted to voltage signal by described current signal; Described electric current loop receiving circuit comprises:
Positive input;
First operational amplifier, there is the first positive input pin, the first negative input pin, the first power pins, second source pin and the first output pin, described first power pins is connected with described positive input, and described second source pin is by the first resistance eutral grounding;
First electric capacity, the first end of described first electric capacity is connected with described negative input pin, and the second end of described first electric capacity is connected with described first output pin;
First linear optical coupling, the negative pole of described first linear optical coupling is connected by described first resistance eutral grounding and by the second resistance with described first negative input pin, and the positive pole of described first linear optical coupling is by the 3rd resistance eutral grounding and be connected with described first positive input pin;
Second linear optical coupling, the positive pole of described second linear optical coupling is connected with described positive input;
First triode, the emitter of described first triode is connected by the negative pole of the 4th resistance with described second linear optical coupling, and the base stage of described first triode is connected with described first output pin;
First reference diode, the positive pole of described first reference diode is connected with the collector electrode of described first triode, and the negative pole of described first reference diode is connected with the positive pole of described second linear optical coupling;
Second electric capacity, the first end of described second electric capacity is connected with the positive pole of described first reference diode, and the second end of described second electric capacity is connected with the negative pole of described first reference diode;
Temperature-compensation circuit, for according to real time environment temperature, determines the signal gain amplifier of described voltage signal at described real time environment temperature;
Signal amplification circuit, is connected with described temperature-compensation circuit with described electric current loop receiving circuit, for carrying out amplification process according to described signal gain amplifier to described voltage signal; Described signal amplification circuit comprises:
3rd electric capacity, the first end of described 3rd electric capacity is connected with the second end of described second electric capacity;
5th resistance, the first end of described 5th resistance is connected with the second end of described 3rd electric capacity;
Second operational amplifier, has the second positive input pin, the second negative input pin, the 3rd power pins, the 4th power pins and the second output pin, and described second negative input pin is connected with the second end of described 5th resistance;
6th resistance, the first end of described 6th resistance is connected with described second negative input pin, and the second end of described 6th resistance is connected with described second output pin;
4th electric capacity, the first end of described 4th electric capacity is connected with described second negative input pin, and the second end of described 4th electric capacity is connected with described second output pin;
5th electric capacity, the first termination first positive voltage of described 5th electric capacity and being connected with described 3rd power pins, the second end ground connection of described 5th electric capacity;
6th electric capacity, the first termination first negative voltage of described 6th electric capacity and being connected with described 4th power pins, the second end ground connection of described 6th electric capacity;
7th resistance, the first end of described 7th resistance is connected with described second positive input pin, the second end ground connection of described 7th resistance;
Low-pass filter circuit, for the signal of filtering higher than predeterminated frequency, obtains the signal in range of target frequencies; Described low-pass filter circuit comprises:
8th resistance, the first end of described 8th resistance is connected with described second output pin;
9th resistance, the first end of described 9th resistance is connected with the second end of described 8th resistance;
7th electric capacity, the first end of described 7th electric capacity is connected with the second end of described 8th resistance;
Tenth resistance, the first end of described tenth resistance is connected with the second end of described 8th resistance, the second end ground connection of described tenth resistance;
8th electric capacity, the first end of described 8th electric capacity is connected with the second end of described 9th resistance, the second end ground connection of described 8th electric capacity;
3rd operational amplifier, there is the 3rd positive input pin, the 3rd negative input pin, the 5th power pins, the 6th power pins and the 3rd output pin, described 3rd positive input pin is connected with the second end of described 9th resistance, and described 3rd negative input pin is connected with the second end of described 7th electric capacity and is connected with described 3rd output pin;
9th electric capacity, the first termination second positive voltage of described 9th electric capacity and being connected with described 5th power pins, the second end ground connection of described 9th electric capacity;
Tenth electric capacity, the first termination second negative voltage of described tenth electric capacity and being connected with described 6th power pins, the second end ground connection of described tenth electric capacity.
Alternatively, described temperature-compensation circuit comprises:
Thermistor, the first end of described thermistor connects reference voltage;
11 resistance, the described first end of the 11 resistance is connected with the second end of described thermistor, the second end ground connection of described 11 resistance;
11 electric capacity, the first end of described 11 electric capacity is connected with the first end of described 11 resistance, and the second end of described 11 electric capacity is connected with the second end of described 11 electronics;
12 resistance, reference voltage described in the first termination of described 12 resistance;
12 electric capacity, the first end of described 12 electric capacity is connected with the first principal voltage, the second end ground connection of described 12 electric capacity;
Microcontroller, there is microcontroller power pins, first clock pins, second clock pin, microcontroller reset pin, SPI clock pins, digital regulation resistance reset pin, SPI input pin, 3.3V power supply AD gathers pin, 5V power supply AD gathers pin, SPI output pin, temperature acquisition pin, ISP clock pins, ISP data pin, microcontroller is pin digitally, described microcontroller power pins is connected with the first end of described 12 electric capacity, described first clock pins is connected with the output terminal of crystal oscillator, described second clock pin is connected with the input end of described crystal oscillator, described microcontroller reset pin and MCLR debug to hold and are connected, described 3.3V power supply AD gathers pin and is connected with interim 3.3 volts of voltages, described 5V power supply AD gathers pin and is connected with interim 5 volts of voltages, described ISP clock pins is connected with the second end of described 12 resistance, described microcontroller digitally pin is connected and ground connection with the second end of described 11 resistance,
Digital regulation resistance, has substrate bias pin, the high-end pin of first potentiometer, first potentiometer low side pin, first potentiometer sliding end pin, serial line interface the RESET input pin, serial interface clock input end pin, grounding pin, serial interface data input end pin, cascade system data output pins, second potentiometer low side pin, the high-end pin of potentiometer, potentiometer sliding end pin, tandem data output pins, digital regulation resistance power pins, described substrate bias pin, described first potentiometer low side pin is connected and ground connection with described grounding pin, the high-end pin of described first potentiometer is connected with the first end of described 5th resistance by the 13 resistance, described first potentiometer sliding end pin is connected with described second negative input pin by the 14 resistance, described serial line interface the RESET input pin is connected with described digital regulation resistance reset pin, described serial interface clock input end is connected with described SPI clock pins, described serial interface data input end pin is connected with SPI output pin, described cascade system data output pins is connected with described SPI input pin, and described digital regulation resistance power pins is connected with 5V voltage and passes through the 13 capacity earth.
1, photoelectric coupling mode is adopted because the electric current loop in embodiment of the present invention signal conditioner receives, receive at current signal pressure being become output and be converted on the basis of voltage signal, provide pressure to become and the high reliability Signal transmissions of signal conditioner and effective electrical isolation, so greatly reduce the possibility of interference so that circuit damage mutually.
2, because the temperature-compensation circuit in embodiment of the present invention signal conditioner has automatic temperature compensation function.Temperature compensation unit take microcontroller as core, Real-time Collection ambient temperature, by regulating digital regulation resistance to adjust gain amplifier, this temperature correction mode fast response time, compensation precision are high, to conform the ability of factors vary so significantly can strengthen signal conditioner.
Accompanying drawing explanation
The hardware block diagram of the signal conditioner that Fig. 1 provides for the embodiment of the present invention;
The circuit diagram of the electric current loop receiving circuit that Fig. 2 provides for the embodiment of the present invention;
The circuit diagram of the signal amplification circuit that Fig. 3 provides for the embodiment of the present invention;
The circuit diagram of the low-pass filter circuit that Fig. 4 provides for the embodiment of the present invention;
The circuit diagram of the microcontroller that Fig. 5 provides for the embodiment of the present invention and peripheral circuit;
The circuit diagram of the digital regulation resistance that Fig. 6 provides for the embodiment of the present invention and peripheral circuit.
Embodiment
The embodiment of the present invention by providing a kind of signal conditioner, in order to solve that signal conditioner in prior art exists because not considering that ambient temperature causes the inaccurate technical problem of monitor signal after processing to the impact of monitor signal.
The embodiment of the present invention provides a kind of signal conditioner, comprising:
Electric current loop receiving circuit, for receiving the current signal that pressure transmitter sends, and is converted to voltage signal by current signal; Electric current loop receiving circuit comprises:
Positive input;
First operational amplifier, have the first positive input pin, the first negative input pin, the first power pins, second source pin and the first output pin, the first power pins is connected with positive input, and second source pin is by the first resistance eutral grounding;
First electric capacity, the first end of the first electric capacity is connected with negative input pin, and the second end of the first electric capacity is connected with the first output pin;
First linear optical coupling, the negative pole of the first linear optical coupling is connected by the first resistance eutral grounding and by the second resistance with the first negative input pin, and the positive pole of the first linear optical coupling is by the 3rd resistance eutral grounding and be connected with the first positive input pin;
Second linear optical coupling, the positive pole of the second linear optical coupling is connected with positive input;
First triode, the emitter of the first triode is connected with the negative pole of the second linear optical coupling by the 4th resistance, and the base stage of the first triode is connected with the first output pin;
First reference diode, the positive pole of the first reference diode is connected with the collector electrode of the first triode, and the negative pole of the first reference diode is connected with the positive pole of the second linear optical coupling;
Second electric capacity, the first end of the second electric capacity is connected with the positive pole of the first reference diode, and the second end of the second electric capacity is connected with the negative pole of the first reference diode;
Temperature-compensation circuit, for according to real time environment temperature, determines the signal gain amplifier of voltage signal at real time environment temperature;
Signal amplification circuit, is connected with temperature-compensation circuit with electric current loop receiving circuit, for carrying out amplification process according to signal gain amplifier to voltage signal; Signal amplification circuit comprises:
3rd electric capacity, the first end of the 3rd electric capacity is connected with the second end of the second electric capacity;
5th resistance, the first end of the 5th resistance is connected with the second end of the 3rd electric capacity;
Second operational amplifier, have the second positive input pin, the second negative input pin, the 3rd power pins, the 4th power pins and the second output pin, the second negative input pin is connected with the second end of the 5th resistance;
6th resistance, the first end of the 6th resistance is connected with the second negative input pin, and the second end of the 6th resistance is connected with the second output pin;
4th electric capacity, the first end of the 4th electric capacity is connected with the second negative input pin, and the second end of the 4th electric capacity is connected with the second output pin;
5th electric capacity, the first termination first positive voltage of the 5th electric capacity and being connected with the 3rd power pins, the second end ground connection of the 5th electric capacity;
6th electric capacity, the first termination first negative voltage of the 6th electric capacity and being connected with the 4th power pins, the second end ground connection of the 6th electric capacity;
7th resistance, the first end of the 7th resistance is connected with the second positive input pin, the second end ground connection of the 7th resistance;
Low-pass filter circuit, for the signal of filtering higher than predeterminated frequency, obtains the signal in range of target frequencies; Low-pass filter circuit comprises:
8th resistance, the first end of the 8th resistance is connected with the second output pin;
9th resistance, the first end of the 9th resistance is connected with the second end of the 8th resistance;
7th electric capacity, the first end of the 7th electric capacity is connected with the second end of the 8th resistance;
Tenth resistance, the first end of the tenth resistance is connected with the second end of the 8th resistance, the second end ground connection of the tenth resistance;
8th electric capacity, the first end of the 8th electric capacity is connected with the second end of the 9th resistance, the second end ground connection of the 8th electric capacity;
3rd operational amplifier, there is the 3rd positive input pin, the 3rd negative input pin, the 5th power pins, the 6th power pins and the 3rd output pin, 3rd positive input pin is connected with the second end of the 9th resistance, and the 3rd negative input pin is connected with the second end of the 7th electric capacity and is connected with the 3rd output pin;
9th electric capacity, the first termination second positive voltage of the 9th electric capacity and being connected with the 5th power pins, the second end ground connection of the 9th electric capacity;
Tenth electric capacity, the first termination second negative voltage of the tenth electric capacity and being connected with the 6th power pins, the second end ground connection of the tenth electric capacity.
In specific implementation process, temperature-compensation circuit comprises:
Thermistor, the first end of thermistor connects reference voltage;
11 resistance, the first end of the 11 resistance is connected with the second end of thermistor, the second end ground connection of the 11 resistance;
11 electric capacity, the first end of the 11 electric capacity is connected with the first end of the 11 resistance, and the second end of the 11 electric capacity is connected with the second end of the 11 electronics;
12 resistance, the first termination reference voltage of the 12 resistance;
12 electric capacity, the first end of the 12 electric capacity is connected with the first principal voltage, the second end ground connection of the 12 electric capacity;
Microcontroller, there is microcontroller power pins, first clock pins, second clock pin, microcontroller reset pin, SPI clock pins, digital regulation resistance reset pin, SPI input pin, 3.3V power supply AD gathers pin, 5V power supply AD gathers pin, SPI output pin, temperature acquisition pin, ISP clock pins, ISP data pin, microcontroller is pin digitally, microcontroller power pins is connected with the first end of the 12 electric capacity, first clock pins is connected with the output terminal of crystal oscillator, second clock pin is connected with the input end of crystal oscillator, microcontroller reset pin and MCLR debug to hold and are connected, 3.3V power supply AD gathers pin and is connected with interim 3.3 volts of voltages, 5V power supply AD gathers pin and is connected with interim 5 volts of voltages, ISP clock pins is connected with the second end of the 12 resistance, microcontroller digitally pin is connected and ground connection with the second end of the 11 resistance,
Digital regulation resistance, has substrate bias pin, the high-end pin of first potentiometer, first potentiometer low side pin, first potentiometer sliding end pin, serial line interface the RESET input pin, serial interface clock input end pin, grounding pin, serial interface data input end pin, cascade system data output pins, second potentiometer low side pin, the high-end pin of potentiometer, potentiometer sliding end pin, tandem data output pins, digital regulation resistance power pins, substrate bias pin, first potentiometer low side pin is connected and ground connection with grounding pin, the high-end pin of first potentiometer is connected with the first end of the 5th resistance by the 13 resistance, first potentiometer sliding end pin is connected with the second negative input pin by the 14 resistance, serial line interface the RESET input pin is connected with digital regulation resistance reset pin, serial interface clock input end is connected with SPI clock pins, serial interface data input end pin is connected with SPI output pin, cascade system data output pins is connected with SPI input pin, and digital regulation resistance power pins is connected with 5V voltage and passes through the 13 capacity earth.
In ensuing part, will by reference to the accompanying drawings, introduce technique scheme in detail.
Please refer to Fig. 1, the hardware block diagram of the dynamic pressure transmitter that Fig. 1 provides for example of the present invention, as shown in Figure 1, this signal conditioner comprises electric current loop receiving circuit 10, signal amplification circuit 20, temperature-compensation circuit 30, low-pass filter circuit 40.The 4-20mA current signal that electric current loop receiving circuit 10 is exported by photoelectric coupling receiving front-end pressure transmitter, also be monitor signal, and this monitor signal is converted to voltage signal, simultaneously, microcontroller is according to the ambient temperature of Real-time Collection, by the gain regulating the resistance of digital regulation resistance to change signal amplification circuit, thus realize temperature correction to reduce the impact of environmental factor on waveform, by the further amplification of signal amplification circuit, again through the part of low-pass filter circuit filtering higher than characteristic frequency, finally signal is exported.
Please refer to Fig. 2, the circuit diagram of the electric current loop receiving circuit that Fig. 2 provides for the embodiment of the present invention, as shown in Figure 2, electric current loop receiving circuit forms primarily of the first operational amplifier U23A.It is also 3 pin that first operational amplifier U23A has the first positive input pin, first negative input pin is also 2 pin, , first power pins is also 4 pin, also namely 8 pin and the first output pin are also 1 pin to second source pin, it is (English: InterruptReQues) that 4 pin meet electric current loop positive input IRx, 8 pin are by the first resistance R39 ground connection, amplifier 2 pin is connected by the first electric capacity C45 with 1 pin, 3 pin of the first linear optical coupling U20B are connected to 2 pin of the first operational amplifier U23A by the second resistance R28, 4 pin of the first linear optical coupling U20B are connected to 3 pin of the first operation amplifier U23, 4 pin of the first linear optical coupling U20B are again by the 3rd resistance R23 ground connection, 3 pin that 1 pin of the second linear optical coupling U23A is connected to the first triode Q1 also i.e. base stage, 2 pin of the one or three pole Q1 are also 8 pin that collector electrode is connected to U23A, 1 pin of Q1 is also emitter is connected to the second linear optical coupling U20A 1 pin by the 4th resistance R26, namely 4 pin that 2 pin of the second linear optical coupling U20A are connected to U23A are also connected with IRx, the positive pole of the first reference diode Z1 also i.e. 1 pin 2 pin also i.e. collector electrode that is connected to Q1, the negative pole of Z1 is also 2 pin that 2 pin are connected to U20A, 1 pin of the second electric capacity C46 is connected to 1 pin of the first reference diode Z1, 2 pin of the second electric capacity C46 are connected to 2 pin of Z1, voltage signal is exported by C46 two ends, 1 pin of C46 is voltage signal negative sense output terminal, can ground connection.
Please refer to Fig. 3, the circuit diagram of the signal amplification circuit that Fig. 3 provides for the embodiment of the present invention, as shown in Figure 3, signal amplification circuit forms primarily of the second operational amplifier U17, it is also 3 pin that second operational amplifier U17 has the second positive input pin, second negative input pin also i.e. 4 pin, the 3rd power pins also i.e. 2 pin, the 4th power pins also i.e. 5 pin and the second output pin also i.e. 1 pin.The signal of the 2 pin outputs of C46 is after capacitance is also the 3rd electric capacity C61, 4 pin of the second operational amplifier U17 are connected to by the 5th resistance R33, the P_W1 of digital regulation resistance is connected to 3 pin of U17 by the 14 resistance R29, P_H1 is by being connected to 4 pin of U17 after being connected in series of the 13 resistance R34 and the 5th resistance R33, it is also+15V power supply that 2 pin of U17 are connected to the first electric malleation, it is also-15V power supply that 5 pin of U17 are connected to the first electric malleation, + 15V power supply is by the 5th electric capacity C56 ground connection,-15V power supply is by the 6th electric capacity C55 ground connection, 3 pin of U17 are by the 7th resistance R26 ground connection, 4 pin of U17 are connected by the 6th resistance R25 with 1 pin, 4th electric capacity C40 is connected in parallel on the two ends of R25, the 1 pin output signal of U17.
Please refer to Fig. 4, the circuit diagram of the low-pass filter circuit that Fig. 4 provides for the embodiment of the present invention, as shown in Figure 4, low-pass filter circuit forms primarily of the 3rd operational amplifier U22, it is also 3 pin that second operational amplifier U17 has the 3rd positive input pin, 3rd negative input pin also i.e. 4 pin, the 5th power pins also i.e. 2 pin, the 6th power pins also i.e. 5 pin and the 3rd output pin also i.e. 1 pin.The signal that 1 pin of U17 exports is by being connected to 3 pin of the 3rd operational amplifier U22 after being connected in series of the 8th resistance R30 and the 9th resistance R27,4 pin of U22 directly connect with 1 pin, 2 pin of the 7th electric capacity C45 are first connected to the phase pin of the 8th resistance R30 and the 9th resistance R27, again by the tenth resistance R34 ground connection, 3 pin of U22 are by the 8th electric capacity C57 ground connection, second negative voltage-15V power supply is first by the 10th electric capacity C60 ground connection, be connected to 5 pin of U22 again, second positive voltage+15V power supply is first by the 9th electric capacity C61 ground connection, be connected to 2 pin of U22 again, the 1 pin output signal of U22.
Please continue to refer to Fig. 5 and Fig. 6, the temperature-compensation circuit that the embodiment of the present invention provides comprises microcontroller as shown in Figure 5 and peripheral circuit, and digital regulation resistance as shown in Figure 6 and peripheral circuit.
Please refer to Fig. 5, the circuit diagram of the microcontroller that Fig. 5 provides for the embodiment of the present invention and peripheral circuit, as shown in Figure 5, microcontroller U41 has microcontroller power pins also i.e. 1 pin, first clock pins is also 2 pin, second clock pin is also 3 pin, microcontroller reset pin is also 4 pin, SPI clock pins is also 10 pin, digital regulation resistance reset pin is also 11 pin, SPI input pin is also 12 pin, it is also 13 pin that 3.3V power supply AD gathers pin, it is also 14 pin that 5V power supply AD gathers pin, SPI output pin is also 15 pin, temperature acquisition pin is also 17 pin, ISP clock pins is also 18 pin, ISP data pin is also 19 pin, microcontroller digitally pin is also 20 pin, wherein 5 pin, 6 pin, 7 pin, 8 pin, 9 pin and 16 pin all unsettled, wiring is as follows: 1 pin of microcontroller U41 connects 3.3V power supply, and 3.3V power supply is by the 12 electric capacity C72 ground connection, and 3 pin and 2 pin of U41 are connected to crystal oscillator two ends respectively, 4 pin are connected to MCLR debugging interface, and 18 pin and 19 pin are connected to ICSPCLK and ICSPDAT debugging interface respectively.The temperature acquisition part line of microcontroller U41 is as follows: AD conversion reference voltage VREF is connected to 18 pin of U41 by the 12 resistance R47, ground connection after VREF is connected in series with the 11 resistance R48 by thermistor R43,11 electric capacity C73 is connected in parallel on the two ends of the 11 resistance R48, and 17 pin that thermistor R43 is connected to U41 with the phase pin of the 11 resistance R48 input as AD.The pin connection of microcontroller upper domination number word potentiometer: 10 pin are connected to P_CLK as SPI clock line, 12 pin are connected to P_COUT as the input of SPI data, and 15 pin are connected to P_DQ and export as SPI data, and 11 pin are connected to RESET and reset as digital regulation resistance.In addition, microcontroller also gathers 3.3V and 5V supply voltage respectively by 13 pin and 14 pin, can send warning when voltage exceedes predefined value.
In the present embodiment, microcontroller model is PIC16F1829, but is not limited thereto in other embodiments, requires that microcontroller at least has output switch parameter, analog input, AD conversion, SPI interface function.Microcontroller and digital regulation resistance are by SPI interface communication.
Please refer to Fig. 6, the circuit diagram of the digital regulation resistance that Fig. 6 provides for the embodiment of the present invention, as shown in Figure 6, it is also 1 pin that digital regulation resistance P13 has substrate bias pin, the high-end pin of first potentiometer is also 3 pin, first potentiometer low side pin is also 4 pin, first potentiometer sliding end pin is also 5 pin, serial line interface the RESET input pin is also 6 pin, serial interface clock input end pin is also 7 pin, grounding pin is also 8 pin, serial interface data input end pin is also 9 pin, cascade system data output pins is also 10 pin, second potentiometer low side pin is also 11 pin, the high-end pin of potentiometer is also 12 pin, potentiometer sliding end pin is also 13 pin, tandem data output pins is also 14 pin, digital regulation resistance power pins also i.e. 16 pin, wherein 2 pin and 15 pin unsettled, the wiring of digital regulation resistance P13 pin is as follows: 1 pin, 4 pin and 8 pin ground connection, 16 pin are connected to+5V power supply, + 5V power supply is by the 13 electric capacity C75 ground connection, 3 pin meet P_H1 to signal amplification circuit, 5 pin meet P_W1 to signal amplification circuit, and 6 pin are connected to 11 pin of U41, and 7 pin are connected to P_CLK as SPI clock, 9 pin are connected to P_DQ as the input of SPI data, and 10 pin are connected to P_COUT and export as SPI data.
In the present embodiment, the model of digital regulation resistance is DS1267, is not limited thereto in other embodiments.
Technological scheme in the embodiment of the present invention, at least tool has the following advantages or beneficial effect:
1, photoelectric coupling mode is adopted because the electric current loop in embodiment of the present invention signal conditioner receives, receive at current signal pressure being become output and be converted on the basis of voltage signal, provide pressure to become and the high reliability Signal transmissions of signal conditioner and effective electrical isolation, so greatly reduce the possibility of interference so that circuit damage mutually.
2, because the temperature-compensation circuit in embodiment of the present invention signal conditioner has automatic temperature compensation function.Temperature compensation unit take microcontroller as core, Real-time Collection ambient temperature, by regulating digital regulation resistance to adjust gain amplifier, this temperature correction mode fast response time, compensation precision are high, to conform the ability of factors vary so significantly can strengthen signal conditioner.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (2)
1. a signal conditioner, is characterized in that, comprising:
Electric current loop receiving circuit, for receiving the current signal that pressure transmitter sends, and is converted to voltage signal by described current signal; Described electric current loop receiving circuit comprises:
Positive input;
First operational amplifier, there is the first positive input pin, the first negative input pin, the first power pins, second source pin and the first output pin, described first power pins is connected with described positive input, and described second source pin is by the first resistance eutral grounding;
First electric capacity, the first end of described first electric capacity is connected with described negative input pin, and the second end of described first electric capacity is connected with described first output pin;
First linear optical coupling, the negative pole of described first linear optical coupling is connected by described first resistance eutral grounding and by the second resistance with described first negative input pin, and the positive pole of described first linear optical coupling is by the 3rd resistance eutral grounding and be connected with described first positive input pin;
Second linear optical coupling, the positive pole of described second linear optical coupling is connected with described positive input;
First triode, the emitter of described first triode is connected by the negative pole of the 4th resistance with described second linear optical coupling, and the base stage of described first triode is connected with described first output pin;
First reference diode, the positive pole of described first reference diode is connected with the collector electrode of described first triode, and the negative pole of described first reference diode is connected with the positive pole of described second linear optical coupling;
Second electric capacity, the first end of described second electric capacity is connected with the positive pole of described first reference diode, and the second end of described second electric capacity is connected with the negative pole of described first reference diode;
Temperature-compensation circuit, for according to real time environment temperature, determines the signal gain amplifier of described voltage signal at described real time environment temperature;
Signal amplification circuit, is connected with described temperature-compensation circuit with described electric current loop receiving circuit, for carrying out amplification process according to described signal gain amplifier to described voltage signal; Described signal amplification circuit comprises:
3rd electric capacity, the first end of described 3rd electric capacity is connected with the second end of described second electric capacity;
5th resistance, the first end of described 5th resistance is connected with the second end of described 3rd electric capacity;
Second operational amplifier, has the second positive input pin, the second negative input pin, the 3rd power pins, the 4th power pins and the second output pin, and described second negative input pin is connected with the second end of described 5th resistance;
6th resistance, the first end of described 6th resistance is connected with described second negative input pin, and the second end of described 6th resistance is connected with described second output pin;
4th electric capacity, the first end of described 4th electric capacity is connected with described second negative input pin, and the second end of described 4th electric capacity is connected with described second output pin;
5th electric capacity, the first termination first positive voltage of described 5th electric capacity and being connected with described 3rd power pins, the second end ground connection of described 5th electric capacity;
6th electric capacity, the first termination first negative voltage of described 6th electric capacity and being connected with described 4th power pins, the second end ground connection of described 6th electric capacity;
7th resistance, the first end of described 7th resistance is connected with described second positive input pin, the second end ground connection of described 7th resistance;
Low-pass filter circuit, for the signal of filtering higher than predeterminated frequency, obtains the signal in range of target frequencies; Described low-pass filter circuit comprises:
8th resistance, the first end of described 8th resistance is connected with described second output pin;
9th resistance, the first end of described 9th resistance is connected with the second end of described 8th resistance;
7th electric capacity, the first end of described 7th electric capacity is connected with the second end of described 8th resistance;
Tenth resistance, the first end of described tenth resistance is connected with the second end of described 8th resistance, the second end ground connection of described tenth resistance;
8th electric capacity, the first end of described 8th electric capacity is connected with the second end of described 9th resistance, the second end ground connection of described 8th electric capacity;
3rd operational amplifier, there is the 3rd positive input pin, the 3rd negative input pin, the 5th power pins, the 6th power pins and the 3rd output pin, described 3rd positive input pin is connected with the second end of described 9th resistance, and described 3rd negative input pin is connected with the second end of described 7th electric capacity and is connected with described 3rd output pin;
9th electric capacity, the first termination second positive voltage of described 9th electric capacity and being connected with described 5th power pins, the second end ground connection of described 9th electric capacity;
Tenth electric capacity, the first termination second negative voltage of described tenth electric capacity and being connected with described 6th power pins, the second end ground connection of described tenth electric capacity.
2. signal conditioner as claimed in claim 1, it is characterized in that, described temperature-compensation circuit comprises:
Thermistor, the first end of described thermistor connects reference voltage;
11 resistance, the described first end of the 11 resistance is connected with the second end of described thermistor, the second end ground connection of described 11 resistance;
11 electric capacity, the first end of described 11 electric capacity is connected with the first end of described 11 resistance, and the second end of described 11 electric capacity is connected with the second end of described 11 electronics;
12 resistance, reference voltage described in the first termination of described 12 resistance;
12 electric capacity, the first end of described 12 electric capacity is connected with the first principal voltage, the second end ground connection of described 12 electric capacity;
Microcontroller, there is microcontroller power pins, first clock pins, second clock pin, microcontroller reset pin, SPI clock pins, digital regulation resistance reset pin, SPI input pin, 3.3V power supply AD gathers pin, 5V power supply AD gathers pin, SPI output pin, temperature acquisition pin, ISP clock pins, ISP data pin, microcontroller is pin digitally, described microcontroller power pins is connected with the first end of described 12 electric capacity, described first clock pins is connected with the output terminal of crystal oscillator, described second clock pin is connected with the input end of described crystal oscillator, described microcontroller reset pin and MCLR debug to hold and are connected, described 3.3V power supply AD gathers pin and is connected with interim 3.3 volts of voltages, described 5V power supply AD gathers pin and is connected with interim 5 volts of voltages, described ISP clock pins is connected with the second end of described 12 resistance, described microcontroller digitally pin is connected and ground connection with the second end of described 11 resistance,
Digital regulation resistance, has substrate bias pin, the high-end pin of first potentiometer, first potentiometer low side pin, first potentiometer sliding end pin, serial line interface the RESET input pin, serial interface clock input end pin, grounding pin, serial interface data input end pin, cascade system data output pins, second potentiometer low side pin, the high-end pin of potentiometer, potentiometer sliding end pin, tandem data output pins, digital regulation resistance power pins, described substrate bias pin, described first potentiometer low side pin is connected and ground connection with described grounding pin, the high-end pin of described first potentiometer is connected with the first end of described 5th resistance by the 13 resistance, described first potentiometer sliding end pin is connected with described second negative input pin by the 14 resistance, described serial line interface the RESET input pin is connected with described digital regulation resistance reset pin, described serial interface clock input end is connected with described SPI clock pins, described serial interface data input end pin is connected with SPI output pin, described cascade system data output pins is connected with described SPI input pin, and described digital regulation resistance power pins is connected with 5V voltage and passes through the 13 capacity earth.
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| CN105202372B (en) | 2018-03-09 |
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