CN105187187B - Clock correcting method based on PTP protocol - Google Patents
Clock correcting method based on PTP protocol Download PDFInfo
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- CN105187187B CN105187187B CN201510362586.0A CN201510362586A CN105187187B CN 105187187 B CN105187187 B CN 105187187B CN 201510362586 A CN201510362586 A CN 201510362586A CN 105187187 B CN105187187 B CN 105187187B
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Abstract
The invention belongs to the technical field of time synchronized.In order to solve in PTP domains from clock existence time deviation, and to this after the time deviation of clock is calibrated, during through after a while time deviation should be there is also from clock, this can influence the problem of this is from the downstream of clock from the lock in time of clock from the time deviation of clock, the present invention proposes a kind of clock correcting method based on PTP protocol, comprises the following steps：(1) time tester is connected with verification clock source；(2) time tester is connected with to be calibrated from clock, to measure this from the reporting M of clock and the verification clock source；(3) downstream is measured from the reporting N of clock and the verification clock source；(4) according to the reporting M and the reporting N trend, calibration range value of the downstream from clock is calculated.Accuracy and the degree of accuracy of time synchronized are improved from the downstream of clock from the influence of clock lock in time to this The present invention reduces the time deviation from clock.
Description
Technical field
The invention belongs to the technical field of time synchronized, and in particular to a kind of clock correcting method based on PTP protocol.
Background technology
In a communication network, perhaps multiple services normal operation requires network clocking synchronization, Precision Time Protocol
(Precision Time Protocol, hereinafter referred to as PTP) is a kind of agreement of time synchronized, has been widely used for the 4th
In third-generation mobile communication technology (4th-Generation, 4G).Lower PTP protocol is briefly described below, applies the network of PTP protocol
Referred to as PTP domains, usual PTP domains include a master clock and more from clock, and Fig. 1 show a PTP domain.PTP protocol defines
Following three types of fundamental clock node：
(1) ordinary clock (Ordinary Clock, hereinafter referred to as OC)：The clock node only has in same PTP domains
One PTP port participates in time synchronized, and by the port from upstream clock node lock in time.In addition, when clock node is made
For clock source when, can be only by a PTP port downstream clock node issuing time, we are also referred to as OC.
(2) boundary clock (Boundary Clock, hereinafter referred to as BC)：The clock node possesses in same PTP domains
Multiple PTP ports participate in time synchronized.It, from upstream clock node lock in time, and passes through remaining end by one of port
Mouth downstream clock node issuing time.In addition, when clock node is as clock source, can be downward by multiple PTP ports
Clock node issuing time is swum, we are also referred to as BC.
(3) transparent clock (Transparent clock, hereinafter referred to as TC)：Compared with BC/OC, BC/OC need with it is other
The clock node retention time is synchronous, and TC is not then synchronous with other clock node retention times.TC has multiple PTP ports, but it
PTP protocol message is only forwarded between these ports and Forwarding Latency correction is carried out to it, without same by any one port
Walk the time.
As shown in figure 1, master clock 10 is with global positioning system (Global Positioning System, hereinafter referred to as GPS)
For clock source, GPS absolute clocks are obtained.Master clock 10 and time synchronized is carried out by BC patterns between clock A 11, specifically, main
Clock 10 periodically with carrying out MESSAGE EXCHANGE from clock A 11, adjusts the time of oneself according to the message of exchange, with reality from clock A 11
Now with the time synchronized of master clock 10；Then periodically report is exchanged from clock D 14 from clock C 13 and downstream with downstream from clock A 11
Text, downstream adjust the time of oneself from clock D 14 from clock C 13 and downstream according to the message of exchange, with realization and from clock A's 11
Time synchronized.Likewise, realizing the time synchronized with master clock 10 from clock B 12, downstream is realized from clock E 15 and downstream from clock F 16
Time synchronized with from the time synchronizeds of clock B 12, finally realizing whole PTP domains.
When from clock A 11, because of crystal oscillator failure and other reasons itself and during existence time deviation, downstream is from clock C 13 and downstream from clock
D 14 with after clock A 11 is synchronous, downstream deviation also can accordingly occur from clock C 13 and downstream from clock D 14 lock in time, this
, can be by being calibrated from clock A 11 to eliminate the time deviation from clock A 11, so as to eliminate downstream from clock C in the case of kind
13 and downstream from clock D 14 caused by corresponding time deviation.When failure be present from clock A 11 crystal oscillator itself, to from clock A 11
Time deviation calibrated after, there is also time deviation from clock A 11, in order to eliminate the time deviation from clock A 11, just need
Will every a period of time to from clock A 11 carry out primary calibration, but twice calibrate between this period from clock A 11 and in the presence of
Between deviation, and when more from clock in PTP domains, to all cycles for once needing to grow very much from clock calibration in PTP domains, to same
One also can be longer from the time interval between clock time calibration twice, from clock A within this section of long period between calibrating twice
11 and existence time deviation, and time deviation may be also very big, to downstream from clock C 13 and downstream from clock D 14 same
The step time has an impact.So need a kind of downstream can be inclined according to the time from clock A 11 from clock D 14 from clock C 13 and downstream
The method that difference adjusts the time of oneself, to reduce from clock A 11 time deviation to downstream from clock C 13 and downstream from clock D's 14
The influence of lock in time.
The content of the invention
In order to solve from clock existence time deviation in PTP domains, and to this after the time deviation of clock is calibrated, by one section
When time should there is also time deviation from clock, this should can be influenceed from the downstream of clock from the lock in time of clock from the time deviation of clock
The problem of, the present invention proposes a kind of clock correcting method based on PTP protocol, so that downstream can be according to the time from clock from clock
The time of deviation adjusting oneself, reduce the influence from clock time deviation, improve downstream from clock with from the synchronous accuracy of clock time
And the degree of accuracy.
Clock correcting method of the invention based on PTP protocol, this method comprise the following steps：
(1) time tester is connected with verification clock source, the synchronised clock of the verification clock source and the master clock in PTP domains
Source is identical；
(2) time tester is connected with to be calibrated from clock, to measure this from clock and the verification clock source
Reporting M；
(3) time tester is connected with described from the downstream of clock from clock, to measure the downstream from clock and the school
Test the reporting N of clock source；
(4) according to the reporting M and the reporting N trend, calibration of the downstream from clock is calculated
Value range.
Wherein, in the step (4), if the reporting M is partially slow just, to show the time from clock, then
The downstream carries out time calibration from clock with Delay+Offset+N；If the reporting M is negative, show described from clock
Time it is fast, then the downstream from clock with Delay+Offset-N carry out time calibration.
Wherein, this method also includes, and is calibrated according to the reporting M that the step (2) obtains to described from clock.
Wherein, the reporting M and N is the average value that the time tester measurement is drawn afterwards several times.
Wherein, if the reporting from clock and it is preceding once measure should be from the difference between the reporting of clock
When value is more than preset value, then it is assumed that should be from clock failure.
Wherein, when the failure from clock, alerted.
Wherein, if reporting of the downstream from the reporting of clock with preceding downstream once measured from clock
Between difference when being more than preset value, then it is assumed that the downstream is from clock failure.
Wherein, when the failure from clock, alerted.
Wherein, the verification clock source and the synchronous clock source are GPS.
Wherein, the verification clock source and the synchronous clock source are BDS.
Clock correcting method of the invention based on PTP protocol has following beneficial effect：
In PTP domains, when from clock due to crystal oscillator failure and other reasons existence time deviation itself, and to this from clock carry out
In this section of long period between calibrating twice in succession, time deviation should be there is also from clock, and the time deviation may be very
Greatly, downstream from clock with should from clock time it is synchronous when, should can influence lock in time of the downstream from clock from the time deviation of clock, the present invention
Clock correcting method based on PTP protocol, it is fast or partially slow to detect first from clock relative to verification clock source, if from clock
Reporting should be fast from clock for negative explanation, then time school should be carried out with Delay+Offset-N from the downstream of clock from clock
Standard, should be from the downstream of clock from clock with Delay+Offset+N if should be partially slow from clock for positive explanation from the reporting of clock
Time calibration is carried out, wherein, N refers to reporting of the downstream from clock, and such downstream can be according to the time deviation from clock from clock
The trend adjustment time of value, reduce inclined from clock time within to this section of long period between from clock calibrate twice in succession
The fast or influence to downstream from clock slowly partially, accordingly even when from clock existence time deviation, downstream from clock with from clock time it is synchronous after pass through
Cross the calibration of the clock correcting method based on PTP protocol of the invention, downstream is also accurate from the time of clock, improve downstream from
The synchronous accuracy of Zhong Yucong clock times and the degree of accuracy, finally improve accuracy and the degree of accuracy of whole PTP domains time synchronized.
Brief description of the drawings
Fig. 1 is the principle schematic of PTP protocol time synchronized；
Fig. 2 is the principle schematic of the clock correcting method of the invention based on PTP protocol；
Fig. 3 is master clock and the principle schematic from clock synchronization in PTP domains.
Embodiment
Technical scheme is introduced below in conjunction with the accompanying drawings.
Clock correcting method of the invention based on PTP protocol, comprises the following steps：
(1) time tester is connected with verification clock source, the synchronised clock of the verification clock source and the master clock in PTP domains
Source is identical；
(2) time tester is connected with to be calibrated from clock, to measure this from the time deviation of clock and verification clock source
Value M；
(3) time tester is connected with the downstream from clock from clock, with measure the downstream from clock with verification clock source when
Between deviation N；
(4) according to reporting M and reporting N trend, calibration range value of the downstream from clock is calculated.
Wherein, in step (4), if reporting M for just, show it is partially slow from time of clock, then downstream from clock with
Delay+Offset+N carries out time calibration；If reporting M is negative, show fast from time of clock, then downstream is from clock
Time calibration is carried out with Delay+Offset-N.
Above-mentioned steps (1)-(5) are described in detail below.
(1) as shown in Fig. 2 time tester 18 is connected with verification clock source 19, such time tester 18 just can
The time of verification clock source 19 is read, and precise time is obtained from verification clock source 19.Verify clock source 19 and PTP domains (i.e.
Apply the network of PTP protocol) in master clock 10 synchronous clock source 17 it is identical, for example, verification clock source 19 and synchronous clock source
17 can be GPS, and time tester 18 obtains GPS precise absolute times after be connected with verification clock source 19, master clock 10 with together
Step clock source 17 connects, and by sending message mutually with synchronous clock source 17, the timestamp adjustment time in message with
Keep obtaining the GPS precise absolute times provided by synchronous clock source 17 with the time synchronized of synchronous clock source 17, master clock 10.Verification
Clock source 19 and synchronous clock source 17 can also be Beidou satellite navigation system (BeiDou Navigation Satellite
System, abbreviation BDS), such time tester 18 obtains BDS precise absolute times, master clock after being connected with verification clock source 19
10 are connected with synchronous clock source 17, and by sending message mutually with synchronous clock source 17, the timestamp adjustment in message
Time with keep with the time synchronized of synchronous clock source 17, and obtain the BDS precise absolute times that are provided by synchronous clock source 17.School
Test clock source 19 and the clock source that relative time is provided is can also be with synchronous clock source 17, when such time tester 18 is by verifying
Clock source 19 obtains relative time, and master clock 10 is synchronous with the retention time of synchronous clock source 17, and obtains and provided by synchronous clock source 17
Relative time.The clock source that verification clock source 19 can be to provide absolute time with synchronous clock source 17 can also be to provide phase
To the clock source of time, the clock correcting method so of the invention based on PTP protocol is applicable not only to clock source and provides absolute time
Between situation, apply also for clock source provide relative time situation, improve the present invention applicability.Below to verify clock
Source 15 and synchronous clock source 10 are to be introduced exemplified by GPS.
(2) time tester 18 is connected with from clock A 11, such time tester 18 can be just read from clock A's 11
Time, time tester 18 is connected with verification clock source 19 and obtains GPS absolute times, time test in step (1)
Instrument 18 is synchronous with the verification retention time of clock source 19.The GPS absolute times that time tester 18 will be obtained by verification clock source 19
Compared with reading from clock A 11 time, the difference of GPS absolute times and the time from clock A 11 are from clock A
The 11 reporting M with verifying clock source 19, such as divide 13 seconds 56 milliseconds of 3 microseconds, GPS from when clock A 11 time is 18 45
45 divide 13 seconds 56 milliseconds of 7 microseconds when absolute time is 18, and GPS absolute times and the difference of the time from clock A 11 are 4 microseconds, from
The reporting M of clock A 11 and verification clock source 19 is 4 microseconds, and reporting M is just, to illustrate to verify from clock A 11 is relative
The time of clock source 19 is partially slow.Because verification clock source 19 is identical with synchronous clock source 17, measure obtain from clock A 11 and
The reporting of clock source 19 is verified namely from clock A 11 and synchronous clock source 17 reporting, synchronous clock source 17
For the time source of master clock 10 in PTP domains, master clock 10 keeps synchronous with synchronous clock source 17, from clock A 11 and synchronous clock source 17
Reporting is namely from clock A 11 and master clock 10 reporting, so reporting M is from clock A 11 and master clock
10 reporting.
Preferably, measured from the reporting of clock A 11 and master clock 10 for time tester 18 from clock A 11 several times after
The average value drawn, that is, the average value of multiple reporting obtained after repeatedly measurement is sought, using the average value as from clock A
11 reporting.
Preferably, obtain after the reporting M of clock A 11 and master clock 10, to being carried out time calibration from clock A 11, when
Between deviation M be timing, it is partially slow from the relative verification times of clock source 19 of clock A 11, the time will be added from clock A 11 current time
Deviation M；Reporting M for it is negative when, it is fast from the relative verification times of clock source 19 of clock A 11, by from clock A 11 it is current when
Between subtract reporting M, to eliminate from clock A 11 time deviation.
Preferably, when deployed between tester 18 to being taken multiple measurements from clock A 11 when, if the time from clock A 11
Deviation and it is preceding once measure from the difference between clock A 11 reporting be more than preset value when, then it is assumed that from clock A 11
Failure.Preset value can be set according to being actually needed, such as could be arranged to 50 microseconds, 90 microseconds or 160 microseconds, if continuously
What is measured twice is more than preset value from the difference between clock A 11 reporting, then it is assumed that from the failures of clock A 11, it may be possible to
From clock A 11 crystal oscillator failure, it is also possible to link failure.Alerted when being broken down from clock A 11, such as can be from clock
Warning light is set on A 11, from clock 11 failures of A when warning light redden, buzzer can also be installed from clock A 11, from clock A
Buzzer sends alerting tone during 11 failure, to remind user to be broken down from clock A 11, it is necessary to be repaired, such user
Failure and on-call maintenance can be found in time, to reduce from influence caused by clock A 11 failure.
(3) by time tester 18 with being disconnected from clock A 11, then it is connected from clock C 13 with downstream, now time test
Instrument 18 is connected with downstream from clock C 13 and verification clock source 19 respectively.Time tester 18 is read after being connected with downstream from clock C 13
Downstream is connected with verification clock source 19 from clock C 13 time, time tester 18 and obtains GPS absolute times, time tester
18 is synchronous with the verification retention time of clock source 19.Time tester 18 by the GPS absolute times obtained by verification clock source 19 with
The downstream read is compared from clock C 13 time, and GPS absolute times are from the difference of clock C 13 time with downstream
Downstream is divided 46 seconds from the clock C 13 and reporting N for verifying clock source 19, such as downstream from when clock C 13 time is 12 32
19 millisecond of 27 microsecond, 32 divide 46 seconds 19 milliseconds of 32 microseconds, GPS absolute times and downstream from clock C 13 when GPS absolute times are 12
The difference of time be 5 microseconds, downstream from clock C 13 and verification clock source 19 reporting N be 5 microseconds.Because during verification
Clock source 19 is identical with synchronous clock source 17, so reporting of the obtained downstream of measurement from clock C 13 and verification clock source 19
Namely downstream from the reporting of clock C 13 and synchronous clock source 17, synchronous clock source 17 be in PTP domains master clock 10 when
Between source, master clock 10 keeps synchronous with synchronous clock source 17, downstream from the reporting of clock C 13 and synchronous clock source 17 also
Downstream from clock C 13 and master clock 10 reporting, thus reporting N be downstream from clock C 13 and master clock 10 when
Between deviation.Preferably, downstream measures downstream from clock C from the reporting of clock C 13 and master clock 10 for time tester 18
13 average values drawn afterwards several times, that is, the average value of the multiple reporting obtained after repeatedly measurement is sought, by the average value
Reporting as downstream from clock C 13.
Preferably, when deployed between tester 18 to downstream from clock C 13 take multiple measurements when, if downstream is from clock C
13 reporting and the preceding downstream once measured from the difference between clock C 13 reporting be more than preset value when, then
Think downstream from the failures of clock C 13.Wherein, preset value can according to be actually needed setting, such as could be arranged to 100 microseconds,
120 microseconds or 190 microseconds, preset if the downstream measured twice in succession is more than from the difference between clock C 13 reporting
Value, then it is assumed that from the failures of clock C 13, fault type is probably crystal oscillator failure of the downstream from clock C 13 in downstream, it is also possible to link event
Barrier.Downstream is alerted when being broken down from clock C 13, such as can set warning light from clock C 13 in downstream, and downstream is from clock
Warning light reddens during 13 failures of C, can also install buzzer from clock C 13 in downstream, downstream from clock 13 failures of C when buzzing
Device sends alerting tone, and to remind user downstream to be broken down from clock C 13, it is necessary to be repaired, such user can be timely
It was found that failure and on-call maintenance, influence caused by reduce downstream from clock C 13 failure.
(4) according to the reporting M and reporting N trend obtained in above-mentioned steps, downstream is calculated from clock C
13 calibration range value.Specifically, if reporting M is just, show it is partially slow from clock A 11 crystal oscillator vibration, with respect to master clock
10 times are partially slow, and over time, from clock A 11 time can be slow it is more, downstream from clock C 13 with from clock A 11
, also can be partially slow from clock C 13 lock in time by the trip under the influence of clock A 11 after synchronization, now downstream from clock C 13 with formula
Delay+Offset+N carries out time bias, and the process of time bias is that downstream is added into Delay+ from clock C 13 current time
Offset+N, such as 11 divide 21 seconds 17 milliseconds of 33 microseconds when downstream from clock C 13 current time is 9, Delay value is 3,
Offset value is 2, and reporting N value is 1, then Delay+Offset+N value is 6, by when 9 11 divide 21 seconds 17 milliseconds
11 divide 21 seconds 17 milliseconds of 39 microseconds when 33 microseconds obtain 9 plus 6 microseconds, divide 21 seconds 17 milliseconds of 39 microseconds to be used as downstream using when 9 11
From clock C 13 current time, it is achieved thereby that reducing partially slow from the times of clock A 11 from clock C 13 time bias to downstream
Influence to downstream from the locks in time of clock C 13.If reporting M is negative, show it is fast from the vibration of clock A 11 crystal oscillator,
It is fast with respect to the time of master clock 10, and over time, from clock A 11 time can be fast it is more, downstream from clock C 13 with
, also can be fast from clock C 13 lock in time by the trip under the influence of clock A 11 after the synchronizations of clock A 11, now downstream is from clock C
13 carry out time bias with formula Delay+Offset-N, and the process of time bias is to add in downstream from clock C 13 current time
Upper Delay+Offset-N, such as 53 divide 46 seconds 8 milliseconds of 14 microseconds, Delay value when downstream from clock C 13 current time is 6
Value for 2, Offset is 1, and reporting N value is 2, then Delay+Offset-N value is 1, divides 46 seconds 8 millis by when 6 53
53 divide 46 seconds 8 milliseconds of 15 microseconds when 14 microseconds of second obtain 6 plus 1 microsecond, divide 46 seconds 8 milliseconds of 15 microseconds to be used as downstream using when 6 53
From clock C13 current time, it is achieved thereby that to downstream from clock C 13 time bias, it is fast right from the times of clock A 11 to reduce
From the influences of the locks in time of clock C 13, M refers to the reporting from clock A 11 and master clock 10 measured in step (2), N in downstream
Refer to the downstream that is measured in step (3) from clock C 13 and master clock 10 reporting.
Wherein, Delay is network delay, and Offset is clock offset, and Delay and Offset are fixed in PTP protocol
Justice, lower Delay and Offset is described below.As shown in figure 3, master clock is periodically reported to broadcast transmission synchronization Sync on network
Text, at the same time, master clock monitoring simultaneously stab the actual time T1 sent of above-mentioned sync message as the precise time of sync message,
And carry T1 in subsequent Follow_Up messages.From clock after Sync sync messages are received, being accurate to for message is write down first
Up to time T2, Follow_Up messages are then received, take-off time stabs T1 from Follow_Up messages.In order to obtain principal and subordinate's clock
Propagation delay time, ask Delay_Req messages to master clock forward delay interval from clock with mode of unicast in network, while record the report
Actual transmission time T3 of the text at network interface.Correspondingly, this message can be write down when master clock receives latency request message
Accurate arrival time T4, and T4 is sent to from clock in subsequent Delay_Resp messages, receive Delay_Resp reports from clock
Wen Hou, it is taken out time stamp T 4.Time stamp T 1, T2, T3, T4 are so just obtained from clock, can be with according to this four time values
The offset offset and propagation delay time delay of principal and subordinate's clock are calculated, from clock according to offset offset and propagation delay time delay
The time of oneself is adjusted, so as to realize the synchronization of principal and subordinate's clock.Network delay Delay and clock offset Offset calculating side
Method is：Offset=1/2 [(T2-T1)-(T4-T3)]；Delay=1/2 [(T2-T1)+(T4-T3)] is by clock offset and net
Network delay adjusts the system time of oneself.
Similarly, row clock school can be entered from clock D 14 to downstream using the above-mentioned clock correcting method based on PTP protocol
Standard, with reduce downstream from clock D 14 with from clock 11 time synchronizeds of A when, from clock A 11 time deviation to downstream from clock D's 14
Influence.Using the above-mentioned clock correcting method based on PTP protocol can also to from clock B 12, downstream from clock E 15 and downstream from clock
F 16 carry out clock alignment, with reduce downstream from clock E 15 and downstream from clock F 16 respectively with from clock 12 time synchronizeds of B when, from
Clock B 12 time deviation to downstream from clock E 15 and downstream from clock F 16 influence so that the time synchronized in whole PTP domains
It is more accurate, more accurate.
The clock correcting method based on PTP protocol of the invention, detect first from clock relative to verification clock source be it is fast also
It is partially slow, should be from the downstream of clock from clock with Delay+ if should be fast from clock for negative explanation from the reporting of clock
Offset-N carries out time calibration, if should be partially slow from clock for positive explanation from the reporting of clock, should from the downstream of clock from
Clock carries out time calibration with Delay+Offset+N, wherein, N refers to reporting of the downstream from clock, and such downstream can from clock
According to the trend adjustment time of the reporting from clock, reduce to this section between from clock calibrate twice in succession compared with
From clock time is fast or the influence to downstream from clock slowly partially in for a long time, accordingly even when from clock existence time deviation, downstream is from clock
It is also from the time of clock by the calibration of clock correcting method of the present invention based on PTP protocol, downstream after synchronous with from clock time
Accurately, downstream is improved from clock with from the synchronous accuracy of clock time and the degree of accuracy, it is same to finally improve the whole PTP domains time
The accuracy of step and the degree of accuracy.
Embodiment 1
Clock correcting method based on PTP protocol comprises the following steps：
(1) time tester 18 is connected with verification clock source 19, the verification clock source 19 is GPS, time tester 18
GPS precise absolute times are obtained from verification clock source 19, and it is synchronous with the verification retention time of clock source 19.Synchronous clock source 17 is
GPS, master clock 10 are synchronous by sending the message retention time mutually with synchronous clock source 17.
(2) time tester 18 is connected with from clock A 11, such time tester 18 can be just read from clock A's 11
Time, 31 divide 28 seconds 44 milliseconds of 7 microseconds when the current time from clock A 11 read is 10；What time tester 18 obtained
31 divide 28 seconds 44 milliseconds of 10 microseconds when GPS absolute times are 10, and time tester 18 is by GPS absolute times and working as from clock A 11
The preceding time is compared, and the difference of GPS absolute times and the current time from clock A 11 is 3 microseconds, then from clock A 11 and verification
The reporting M of clock source 19 is 3 microseconds, and reporting M is also the reporting from clock A 11 and master clock 10.When
Between deviation M for just, illustrate it is partially slow from the relative verification times of clock source 19 of clock A 11,
(3) by time tester 18 with being disconnected from clock A 11, then it is connected from clock C 13 with downstream, now time test
Instrument 18 is connected with downstream from clock C 13 and verification clock source 19 respectively.Time tester 18 is read after being connected with downstream from clock C 13
From clock C 13 time, 27 seconds 52 milliseconds of 37 microseconds 34 are divided in the downstream read when from clock C 13 current time being 10 in downstream,
34 divide 27 seconds 52 milliseconds of 40 microseconds when the GPS absolute times that time tester 18 is obtained by verification clock source 19 are 10, and the time surveys
Instrument 18 is tried by GPS absolute times compared with the downstream read is from clock C 13 current time, GPS absolute times and downstream
Difference from clock C 13 current time is 3 microseconds, i.e., downstream is 3 with the reporting N for verifying clock source 19 from clock C 13
Microsecond, reporting N are also reporting of the downstream from clock C 13 and master clock 10.
(4) the reporting M from clock A 11 and master clock 10 obtained by step (2) is 3 microseconds, and reporting M is
Just, show it is partially slow from the vibration of clock A 11 crystal oscillator, it is partially slow with respect to the time of master clock 10, and over time, from clock A 11
Time can be slow it is more, downstream from clock C 13 with after clock A 11 is synchronous, downstream also can be by from clock A from clock C 13 time
11 influence, now downstream from clock C 13 with formula Delay+Offset+N carry out time bias.Time in PTP protocol message
It is known quantity to stab T1, T2, T3 and T4, according to Offset=1/2 [(T2-T1)-(T4-T3)]；Delay=1/2 [(T2-T1)+
(T4-T3) Offset and Delay] are calculated, the value that the value for calculating Offset is 3, Delay is 4, is drawn down by step (3)
It is 3 microseconds to swim from clock C 13 and verification clock source 19 reporting N, and Delay+Offset+N value is 10, by downstream from
34 divide 27 seconds 52 milliseconds of 37 microseconds to add 10 microseconds during clock C 13 current time 10, when obtaining 10 34 divide 27 seconds 52 milliseconds it is 47 micro-
Second, divide current time of 27 seconds 52 milliseconds of 47 microseconds as downstream from clock C 13 using when 10 34, it is achieved thereby that to downstream from clock C
13 time bias, reduce from the influence to downstream from the locks in time of clock C 13 slowly partially of the times of clock A 11.
Embodiment 2
Clock correcting method based on PTP protocol comprises the following steps：
(1) time tester 18 is connected with verification clock source 19, the verification clock source 19 is BDS, time tester 18
BDS precise absolute times are obtained from verification clock source 19, and it is synchronous with the verification retention time of clock source 19.Synchronous clock source 17 is
BDS, master clock 10 are synchronous by sending the message retention time mutually with synchronous clock source 17.
(2) time tester 18 is connected with from clock A 11, such time tester 18 can be just read from clock A's 11
Time, 52 divide 11 seconds 21 milliseconds of 27 microseconds when the current time from clock A 11 read is 13；What time tester 18 obtained
52 divide 11 seconds 21 milliseconds of 25 microseconds when BDS absolute times are 13, and time tester 18 is by BDS absolute times and working as from clock A 11
The preceding time is compared, and the difference of BDS absolute times and the current time from clock A 11 is -2 microseconds, then from clock A 11 and verification
The reporting M of clock source 19 is -2 microseconds, and reporting M is also the reporting from clock A 11 and master clock 10.
Reporting M is negative, illustrate it is fast from the relative verification times of clock source 19 of clock A 11,
(3) by time tester 18 with being disconnected from clock A 11, then it is connected from clock C 13 with downstream, now time test
Instrument 18 is connected with downstream from clock C 13 and verification clock source 19 respectively.Time tester 18 is read after being connected with downstream from clock C 13
From clock C 13 time, 8 seconds 14 milliseconds of 19 microseconds 54 are divided in the downstream read when from clock C 13 current time being 13 in downstream, when
Between the BDS absolute times that are obtained by verification clock source 19 of tester 18 54 divide 8 seconds 14 milliseconds of 20 microseconds, time tester when being 13
18 by BDS absolute times compared with the downstream read is from clock C 13 current time, BDS absolute times and downstream are from clock
The difference of C 13 current time is 1 microsecond, i.e., downstream is 1 microsecond with the reporting N for verifying clock source 19 from clock C 13,
Reporting N is also reporting of the downstream from clock C 13 with the downstream of master clock 10 from clock C 13 and master clock 10.
(4) the reporting M from clock A 11 and master clock 10 obtained by step (2) is -2 microseconds, and reporting M is
It is negative, show it is fast from clock A 11 crystal oscillator vibration, it is fast with respect to the time of master clock 10, and over time, from clock A 11
Time can be fast it is more, downstream from clock C 13 with after clock A 11 is synchronous, downstream also can be by from clock A from clock C 13 time
11 influence, now downstream from clock C 13 with formula Delay+Offset-N carry out time bias.Time in PTP protocol message
It is known quantity to stab T1, T2, T3 and T4, according to Offset=1/2 [(T2-T1)-(T4-T3)]；Delay=1/2 [(T2-T1)+
(T4-T3) Offset and Delay] are calculated, the value that the value for calculating Offset is 2, Delay is 4, is drawn down by step (3)
It is 1 microsecond to swim from clock C 13 and verification clock source 19 reporting N, and Delay+Offset-N value is 5, by downstream from clock
54 divide 8 seconds 14 milliseconds of 19 microseconds to add 5 microseconds during C 13 current time 13, and 54 divide 8 seconds 14 milliseconds of 24 microseconds when obtaining 13, with
54 divide current time of 8 seconds 14 milliseconds of 24 microseconds as downstream from clock C 13 when 13, it is achieved thereby that to downstream from clock C's 13
Time bias, reduce from the influence to downstream from the locks in time of clock C 13 slowly partially of the times of clock A 11.
Based on the present invention thinking it is also contemplated that in different time link switchovers, in Signal Degrade and temperature change
When, in the case of close coupling and loose coupling, under different networking mode scenes, to providing suitable offset or benefit from clock
Scope is repaid, to carrying out time bias from clock, to improve from the synchronous degree of accuracy of clock time.
Claims (10)
1. a kind of clock correcting method based on PTP protocol, it is characterised in that this method comprises the following steps：
(1) time tester is connected with verification clock source, the synchronous clock source phase of the verification clock source and the master clock in PTP domains
Together；
(2) time tester is connected with to be calibrated from clock, to measure this from the time of clock and the verification clock source
Deviation M；
(3) time tester is connected with described from the downstream of clock from clock, to measure the downstream from clock and during the verification
Zhong Yuan reporting N；
(4) according to the reporting M and the reporting N trend, calibration range of the downstream from clock is calculated
Value.
2. the clock correcting method according to claim 1 based on PTP protocol, it is characterised in that in the step (4),
If the reporting M for just, shows that the time from clock is partially slow, then the downstream from clock with Delay+Offset+N
Carry out time calibration；If the reporting M is negative, show that the time from clock is fast, then the downstream from clock with
Delay+Offset-N carries out time calibration.
3. the clock correcting method according to claim 1 or 2 based on PTP protocol, it is characterised in that this method is also wrapped
Include, calibrated according to the reporting M that the step (2) obtains to described from clock.
4. the clock correcting method according to claim 1 or 2 based on PTP protocol, it is characterised in that the time deviation
Value M and N are the average value that the time tester measurement is drawn afterwards several times.
5. the clock correcting method according to claim 1 or 2 based on PTP protocol, it is characterised in that if described from clock
Reporting and it is preceding once measure should from the difference between the reporting of clock be more than preset value when, then it is assumed that this from
Clock failure.
6. the clock correcting method according to claim 5 based on PTP protocol, it is characterised in that when described from clock failure
When, alerted.
7. the clock correcting method according to claim 1 or 2 based on PTP protocol, it is characterised in that if the downstream
From the reporting of clock and preceding downstream once measured from the difference between the reporting of clock be more than preset value when, then
Think the downstream from clock failure.
8. the clock correcting method according to claim 7 based on PTP protocol, it is characterised in that when the downstream is from clock
During failure, alerted.
9. the clock correcting method according to claim 1 or 2 based on PTP protocol, it is characterised in that the verification clock
Source and the synchronous clock source are GPS.
10. the clock correcting method according to claim 1 or 2 based on PTP protocol, it is characterised in that during the verification
Zhong Yuan and the synchronous clock source are BDS.
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| CN110267200A (en) * | 2019-06-27 | 2019-09-20 | 合肥更鼓电子科技有限公司 | A kind of base station positioning method based on precise synchronization network |
| CN112019291B (en) * | 2020-08-31 | 2022-12-27 | 合肥中科君达视界技术股份有限公司 | Network equipment timing method |
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| CN102420667A (en) * | 2011-11-29 | 2012-04-18 | 浙江省电力公司 | System and implementation method of time synchronization network based on synchronous digital hierarchy (SDH) |
| WO2013143112A1 (en) * | 2012-03-30 | 2013-10-03 | Telefonaktiebolaget L M Ericsson(Publ) | Method and system for robust precision time protocol synchronization |
| CN104145435A (en) * | 2012-02-27 | 2014-11-12 | 瑞典爱立信有限公司 | Frequency distribution using precision time protocol |
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| CN102420667A (en) * | 2011-11-29 | 2012-04-18 | 浙江省电力公司 | System and implementation method of time synchronization network based on synchronous digital hierarchy (SDH) |
| CN104145435A (en) * | 2012-02-27 | 2014-11-12 | 瑞典爱立信有限公司 | Frequency distribution using precision time protocol |
| WO2013143112A1 (en) * | 2012-03-30 | 2013-10-03 | Telefonaktiebolaget L M Ericsson(Publ) | Method and system for robust precision time protocol synchronization |
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