CN105187054A - Phase-locked loop system - Google Patents
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Abstract
Provided in the invention is a phase-locked loop system comprising a first-stage phase-locked loop and a second-stage phase-locked loop. The output terminal of the first-stage phase-locked loop is connected with the input terminal of the second-stage phase-locked loop; and the input terminal of the first-stage phase-locked loop is connected with a clock. The second-stage phase-locked loop contains phase-locked loops with the number corresponding to that of components in an application system; the phase-locked loops include feedback loops; input terminals of the phase-locked loops are adjacent to the output terminal of the first-stage phase-locked loop; and output terminals of the phase-locked loops approach input terminals of the corresponding components. According to the embodiment of the invention, a synchronous rate of clock signals received by all components of the application system and thus accuracy of data and command transmission between electronic devices is improved.
Description
Technical field
The present invention relates to electronic technology field, particularly relate to a kind of phase-locked loop systems.
Background technology
PLL (phase-locked loop, phaselockedloop) be a kind of utilize feedback control principle to realize frequency and the simultaneous techniques of phase place, it can be widely used in each class of electronic devices, the clock exported to make the circuit of electronic equipment is synchronous with the reference clock of its outside, when the frequency of reference clock or phase place change, phase-locked loop systems can detect this change, and carrys out regulation output frequency by the reponse system of its inside, until both re-synchronizations.
Phase-locked loop is transmitting in the process of clock signal to the application system in electronic equipment, easy appearance shake (jitter), this jitter can comprise: due to jitter2 that noise jamming brings on the transmission path clock of the jitter1 that phase-locked loop brings and phase-locked loop and above-mentioned application system; Phase-locked loop is a closed-loop system, and within jitter1 is present in the loop of phase-locked loop, the size of jitter1 just can be known by those skilled in the art at the beginning of design, and can be adjusted by the loop of self and control; Jitter2 is present on the clock bang path outside loop, and the size of jitter2 can not be estimated, and transmission path clock is longer, and the impact of jitter2 on clock signal is larger.
When above-mentioned phase-locked loop needs to provide synchronous clock signal to two in application system and above parts, when the clock signal transmission transferred out from phase-locked loop is to above-mentioned parts, due to the impact of jitter2 can be subject on the transmit path, because this reducing the sync rates of the clock signal between above-mentioned each parts, so cause above-mentioned electric room transmit data, order accuracy low.Such as, with reference to Fig. 1, show traditional DDRPHY (physical layer interface of chip memory, DoubleDataRatephysicallayerinterface) structural representation of system, specifically can comprise: phase-locked loop (PLL) 101, controller (Controller) 102, command transfer interface (CMDPHY) 103 and data transmission interface (DQPHY) 104; Wherein, phase-locked loop 101 needs respectively to above-mentioned controller 102, command transfer interface 103 and data transmission interface 104 transmit clock signal, and need to ensure that the clock signal that phase-locked loop 101 transmits to above-mentioned controller 102, command transfer interface 103 and data transmission interface 104 remains synchronous, SOC (SOC (system on a chip) is ensured with this, SystemonChip) with between DRAM (dynamic random access memory, DynamicRandomAccessMemory) chip the accuracy of data, order is transmitted.
Because clock signal is transmitted out from above-mentioned phase-locked loop 101, in the transmission path transferring to above-mentioned controller 102, command transfer interface 103 and data transmission interface 104, the impact of jitter2 can be subject to, therefore, the clock signal that phase-locked loop 101 transmits to above-mentioned controller 102, command transfer interface 103 and data transmission interface 104 there will be nonsynchronous problem, so make to transmit between SOC and dram chip data, order accuracy low.
Summary of the invention
Embodiment of the present invention technical problem to be solved is to provide a kind of phase-locked loop systems, can improve the sync rates of the clock signal that each parts of above-mentioned application system receive, and then improves the accuracy of electric room transmission data, order.
In order to solve the problem, the invention discloses a kind of phase-locked loop systems, comprising: first order phase-locked loop and second level phase-locked loop; The output of described first order phase-locked loop is connected with the input of described second level phase-locked loop;
Wherein, the input of described first order phase-locked loop is connected with clock;
Described second level phase-locked loop comprises: the phase-locked loop that quantity is corresponding to parts in application system; Described phase-locked loop comprises feedback loop, and the input of described phase-locked loop is closely adjacent with the output of described first order phase-locked loop, and the output of described phase-locked loop is near the input of corresponding component.
Preferably, described feedback loop is periphery feedback loop, then described phase-locked loop also comprises: the internal feedback loop of disconnection, and input, the output in described internal feedback loop are connected with output with the input in described periphery feedback loop respectively.
Preferably, the output of each phase-locked loop is identical with the distance of the input of corresponding component.
Preferably, the input of each phase-locked loop is identical with the distance of described first order phase-locked loop.
Preferably, the quantity of described second level phase-locked loop is 3.
Compared with prior art, the embodiment of the present invention comprises following advantage:
The phase-locked loop systems that the embodiment of the present invention provides, because the clock signal that transfers out from first order phase-locked loop to be passed to the parts of application system through second level phase-locked loop, therefore in known first order phase-locked loop to the transmission path clock of the parts of application system, some transmission path clock is included in inside the feedback loop of above-mentioned phase-locked loop, and this section clock transmission path is not by the impact of jitter2, remaining another part path is the transmission path clock of phase-locked loop to corresponding component, because phase-locked loop to the transmission path clock of corresponding component is the part of first order phase-locked loop to the transmission path clock of the parts of application system, and the output of phase-locked loop is near the input of corresponding component in the phase-locked loop of the above-mentioned second level, known phase-locked loop is shorter to the transmission path clock of corresponding component, much smaller than first order phase-locked loop to the transmission path clock of the parts of application system, therefore, the transmission path clock that contrasting affects by jitter2 in existing technical scheme is the transmission path clock of first order phase-locked loop to the parts of application system, in the embodiment of the present invention, the transmission path clock affected by jitter2 is the transmission path clock of phase-locked loop to corresponding component, also be, the embodiment of the present invention shortens the transmission path clock affected by jitter2, and then the impact of the clock signal on transmission path clock by jitter2 can be reduced in, when above-mentioned phase-locked loop systems to need in application system two and above parts to provide synchronous clock signal, the impact of the jitter2 be subject to due to the clock signal transferring to above-mentioned parts by second level phase-locked loop is less, therefore, it is possible to improve the sync rates of second level phase-locked loop to the clock signal of each part transfers of above-mentioned application system, also the sync rates of the clock signal that each parts of above-mentioned application system receive can namely be improved, and then improve electric room transmission data, the accuracy of order.
Accompanying drawing explanation
Fig. 1 is the structural representation of traditional DDRPHY system;
Fig. 2 is the structural representation of a kind of phase-locked loop systems embodiment one provided by the invention;
Fig. 3 is the structural representation of a kind of phase-locked loop systems embodiment two provided by the invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Embodiment one
With reference to Fig. 2, show the structural representation of a kind of phase-locked loop systems embodiment one provided by the invention, specifically can comprise: first order phase-locked loop 201 and second level phase-locked loop 202; Wherein, the input of above-mentioned first order phase-locked loop 201 can be connected with clock;
Above-mentioned second level phase-locked loop 202 specifically can comprise: the phase-locked loop that quantity is corresponding to parts in application system; Above-mentioned phase-locked loop specifically can comprise feedback loop, and the input of above-mentioned phase-locked loop can be closely adjacent with the output of above-mentioned first order phase-locked loop 201, and the output of above-mentioned phase-locked loop can near the input of corresponding component.
The embodiment of the present invention can be applied in electronic equipment, to make application system in electronic equipment in the process transmitting clock signal, reduces the impact that clock signal is subject to jitter2, and then can ensure the accuracy of electric room transmission data, order.Application system in the embodiment of the present invention can be the application system in electronic equipment, the parts of application system can for needing the parts receiving synchronous clock signal in application system, such as: the DDRPHY system in electronic equipment SOC, the parts receiving synchronizing clock signals are needed to comprise in above-mentioned DDRPHY system: controller, command transfer interface and data transmission interface.
In the embodiment of the present invention, the input of first order phase-locked loop 201 can be connected with clock, output is connected with above-mentioned second level phase-locked loop 202, there is provided source clock with the phase-locked loop thought in above-mentioned second level phase-locked loop 202, also namely first order phase-locked loop 201 can as the reference clock of above-mentioned second level phase-locked loop 202; When the clock that the clock that second level phase-locked loop 202 exports and the first order phase-locked loop 201 received export is asynchronous, second level phase-locked loop 202 can carry out the clock signal of regulation output by the reponse system of inside, until the clock signal synchronization that the clock signal of second level phase-locked loop 202 output and above-mentioned first order phase-locked loop 201 export.
In the embodiment of the present invention, the parts of above-mentioned application system are specifically as follows the parts needing to receive synchronous clock signal, the quantity of the phase-locked loop that second level phase-locked loop 202 comprises can be equal with the quantity of above-mentioned parts, and can be one-to-one relationship between above-mentioned phase-locked loop and above-mentioned parts; Suppose that above-mentioned application system comprises the parts (parts 1, parts 2 ..., parts n) that n needs to receive synchronizing signal, then second level phase-locked loop 202 also can comprise n phase-locked loop (phase-locked loop 2021, phase-locked loop 2022 ..., phase-locked loop 202n), and phase-locked loop 2021 corresponds to parts 1, phase-locked loop 2022 corresponds to parts 2, and phase-locked loop 202n corresponds to parts n; Wherein, said n is any positive integer; Such as: be arranged in the DDRPHY system on SOC, comprise: controller, command transfer interface and data transmission interface totally three need to receive the parts of synchronizing clock signals, then above-mentioned second level phase-locked loop 202 comprises three phase-locked loops: phase-locked loop 2021, phase-locked loop 2022 and phase-locked loop 2023.
In the embodiment of the present invention, above-mentioned phase-locked loop comprises feedback loop, and the input of above-mentioned phase-locked loop can be closely adjacent with the output of above-mentioned first order phase-locked loop 201, also namely above-mentioned phase-locked loop can be closely adjacent with above-mentioned first order phase-locked loop on physics putting position, the output of above-mentioned phase-locked loop can near the input of corresponding component, the clock signal exported due to first order phase-locked loop 201 to pass to the parts of above-mentioned application system through second level phase-locked loop 202, then the input of phase-locked loop is closely adjacent with the output of above-mentioned first order phase-locked loop 201, the output of phase-locked loop is near the input of corresponding component, can make be included in the loop of above-mentioned phase-locked loop by some path in the transmission path clock of the parts of first order phase-locked loop 201 to application system, this part is arranged in the transmission path clock of cycle of phase-locked loop not by the impact of jitter2, another part by the output of phase-locked loop to the transmission path clock of the input of corresponding component, for phase-locked loop systems of the present invention is to the transmission path clock of the parts of application system, because the output of phase-locked loop is near the input of corresponding component, therefore the known above-mentioned transmission path clock from phase-locked loop to corresponding component is shorter.
In an embodiment of the present invention, the above-mentioned output of each phase-locked loop can be identical with the distance of the input of corresponding component, namely also phase-locked loop to the transmission path clock of corresponding component can be equal, so, avoid because phase-locked loop is unequal and occur time delay to the transmission path clock of corresponding component, and then bring the nonsynchronous problem of clock signal by time delay, therefore, it is possible to improve the sync rates that phase-locked loop transfers to the clock signal of corresponding component.
In another embodiment of the invention, the input of each phase-locked loop can be identical with the distance of above-mentioned first order phase-locked loop, namely also first order phase-locked loop 201 to the transmission path clock of each phase-locked loop of above-mentioned second level phase-locked loop 202 can be equal, avoid because above-mentioned first order phase-locked loop 201 is unequal and occur time delay to the transmission path clock of each phase-locked loop of above-mentioned second level phase-locked loop 202, and then the nonsynchronous problem of clock signal to be brought by time delay, therefore, it is possible to improve the sync rates of first order phase-locked loop 201 to each phase-locked loop transmit clock signal in second level phase-locked loop 202, the sync rates of the clock signal received due to each phase-locked loop in above-mentioned second level phase-locked loop 202 is high, and then the sync rates that above-mentioned phase-locked loop transfers to the clock signal of corresponding component can be improved.
In an embodiment of the present invention, above-mentioned feedback loop can be periphery feedback loop, then above-mentioned phase-locked loop also comprises: the internal feedback loop of disconnection, and input, the output in above-mentioned internal feedback loop are connected with output with the input in above-mentioned periphery feedback loop respectively, because the phase-locked feedback loop connecting inside is in off-state, and the input in internal feedback loop, output is connected with output with the input in above-mentioned periphery feedback loop respectively, thus the cyclic system that periphery feedback loop can make phase-locked loop become new, output due to periphery feedback loop is also the output of above-mentioned phase-locked loop, then in specific implementation process, by the input of the output in above-mentioned periphery feedback loop near corresponding component, namely the output of above-mentioned phase-locked loop can be made near the input of above-mentioned corresponding component, to make can more be included in inside the loop of phase-locked loop from the transmission path clock of first order feedback circuit 201 to application system.
In specific operation process, after starting first order phase-locked loop 201, start the phase-locked loop that above-mentioned second level phase-locked loop 202 comprises simultaneously, namely can realize above-mentioned functions.
To sum up, a kind of phase-locked loop systems that the embodiment of the present invention provides, specifically can comprise: first order phase-locked loop and second level phase-locked loop; Wherein, the input of above-mentioned first order phase-locked loop 201 can be connected with clock; Above-mentioned second level phase-locked loop 202 specifically can comprise: the phase-locked loop that quantity is corresponding to parts in application system; Above-mentioned phase-locked loop specifically can comprise feedback loop, and the input of above-mentioned feedback loop can be closely adjacent with the output of above-mentioned first order phase-locked loop 201, and the output of above-mentioned feedback loop can near the input of corresponding component.
In the embodiment of the present invention, because the clock signal that transfers out from first order phase-locked loop to be passed to the parts of application system through second level phase-locked loop, therefore in known first order phase-locked loop to the transmission path clock of the parts of application system, some transmission path clock is included in inside the feedback loop of above-mentioned phase-locked loop, and this section clock transmission path is not by the impact of jitter2, remaining another part path is the transmission path clock of phase-locked loop to corresponding component, because phase-locked loop to the transmission path clock of corresponding component is the part of first order phase-locked loop to the transmission path clock of the parts of application system, and the output of phase-locked loop is near the input of corresponding component in the phase-locked loop of the above-mentioned second level, known phase-locked loop is shorter to the transmission path clock of corresponding component, be less than the transmission path clock of first order phase-locked loop to the parts of application system, therefore, the transmission path clock that contrasting affects by jitter2 in existing technical scheme is the transmission path clock of first order phase-locked loop to the parts of application system, in the embodiment of the present invention, the transmission path clock affected by jitter2 is the transmission path clock of phase-locked loop to corresponding component, therefore, shorten the transmission path clock affected by jitter2, and then the impact of the clock signal on transmission path clock by jitter2 can be reduced in, when above-mentioned phase-locked loop systems to need in application system two and above parts to provide synchronous clock signal, the impact of the jitter2 be subject to due to the clock signal transferring to above-mentioned parts by second level phase-locked loop is less, therefore, it is possible to improve the sync rates of second level phase-locked loop to the clock signal of each part transfers of above-mentioned application system, also the sync rates of the clock signal that each parts of above-mentioned application system receive can namely be improved, and then improve electric room transmission data, the accuracy of order.
Embodiment two
With reference to Fig. 3, show the structural representation of a kind of phase-locked loop systems embodiment two provided by the invention, specifically can comprise: the first phase-locked loop (PLL1) 301, second phase-locked loop (PLL2) the 302, the 3rd phase-locked loop (PLL3) the 303, the 4th phase-locked loop (PLL4) 304;
In the embodiment of the present invention, application system can be DDRPHY system, specifically can comprise three parts: first component can for controller (Controller) 305, second component can data transmission interface (DQPHY) 307 for command transfer interface (CMDPHY) the 306, the 3rd parts;
In the embodiment of the present invention, first order phase-locked loop specifically can comprise: the first phase-locked loop 301, and second level phase-locked loop specifically can comprise: the second phase-locked loop 302, the 3rd phase-locked loop 303 and the 4th phase-locked loop 304; Wherein, the input of the first phase-locked loop 301 can be connected with clock, output is connected with above-mentioned second phase-locked loop 302, the 3rd phase-locked loop 303 and the 4th phase-locked loop 304 respectively, with thinking that above-mentioned second phase-locked loop 302, the 3rd phase-locked loop 303 and the 4th phase-locked loop 304 provide source clock, also namely first order phase-locked loop 301 can as the reference clock of above-mentioned second phase-locked loop 302, the 3rd phase-locked loop 303 and the 4th phase-locked loop 304.
In the embodiment of the present invention, the corresponding above-mentioned controller 305 of above-mentioned second phase-locked loop 302, thinks that above-mentioned controller provides clock signal; The corresponding mentioned order coffret 306 of above-mentioned 3rd phase-locked loop 303, thinks that mentioned order coffret 306 provides clock signal; The corresponding above-mentioned data transmission interface 307 of above-mentioned 4th phase-locked loop 304, thinks that above-mentioned data transmission interface 307 provides clock signal.
In the embodiment of the present invention, the input of above-mentioned second phase-locked loop 302, the 3rd phase-locked loop 303 and the 4th phase-locked loop 304 is identical with the distance of above-mentioned first phase-locked loop 301, therefore, avoid because distance does not wait and there is time delay, and then the nonsynchronous problem of clock signal that above-mentioned second phase-locked loop 302, the 3rd phase-locked loop 303 and the 4th phase-locked loop 304 are received, therefore, it is possible to improve the sync rates of the clock signal that above-mentioned second phase-locked loop 302, the 3rd phase-locked loop 303 and the 4th phase-locked loop 304 receive.
In the embodiment of the present invention, above-mentioned second phase-locked loop 302, the input of the 3rd phase-locked loop 303 and the 4th phase-locked loop 304 respectively with above-mentioned controller 305, command transfer interface 306, the distance of data transmission interface 307 is equal, also be the transmission path clock of above-mentioned second phase-locked loop 302 to above-mentioned controller 305, 3rd phase-locked loop 303 is to the transmission path clock of above-mentioned command transfer interface 306, and the 4th phase-locked loop 304 to the transmission path clock of above-mentioned data transmission interface 307 be equal, therefore, avoid because distance does not wait and there is time delay, and then make above-mentioned controller 305, the nonsynchronous problem of clock signal that command transfer interface 306 and data transmission interface 307 receive, therefore, it is possible to improve the second phase-locked loop 302, 3rd phase-locked loop 303 and the 4th phase-locked loop 304 transfer to controller 305, the sync rates of the clock signal of command transfer interface 306 and data transmission interface 307.
In an embodiment of the present invention, above-mentioned second phase-locked loop 302, the 3rd phase-locked loop 303 and the 4th phase-locked loop 304 all can comprise one article of feedback loop, can be respectively: the first feedback loop 3021, second feed back loop 3031, the 3rd feedback loop 3041; Wherein, above-mentioned feedback loop can be all periphery feedback loop.
Above-mentioned second phase-locked loop 302 can also comprise an internal feedback loop disconnected, the input in above-mentioned internal feedback loop, output respectively with the input of above-mentioned first feedback loop 3021, output is connected, because the feedback circuit of inside is in off-state, and the input in above-mentioned internal feedback loop, output respectively with the input of above-mentioned first feedback loop 3021, output is connected, therefore the first feedback loop 3021 can make the second phase-locked loop 302 form new cyclic system, in specific implementation process, by the input of the output of above-mentioned first feedback loop 3021 near controller 305, namely the input of output near above-mentioned controller 305 of above-mentioned second phase-locked loop 302 can be made, to make the transmission path clock of the controller 305 in above-mentioned first order phase-locked loop 301 to DDRPHY system, inside the loop that more can be included in the second phase-locked loop 302, and then the transmission path clock making the controller 305 in first order phase-locked loop 301 to DDRPHY system affect by jitter2 reduces,
In like manner, second feed back loop 3031 can make the 3rd phase-locked loop 303 form new cyclic system, to make the transmission path clock of the command transfer interface 306 in above-mentioned first order phase-locked loop 301 to DDRPHY system, inside the loop that more can be included in the 3rd phase-locked loop 303, the transmission path clock therefore making first order phase-locked loop 301 to command transfer interface 306 affect by jitter2 reduces;
3rd feedback loop 3041 can make the 4th phase-locked loop 304 form new cyclic system, to make the transmission path clock of the data transmission interface 307 in above-mentioned first order phase-locked loop 301 to DDRPHY system, inside the loop that more can be included in the 4th phase-locked loop 304, the transmission path clock therefore making first order phase-locked loop 301 to data transmission interface 307 affect by jitter2 reduces.
To sum up, a kind of phase-locked loop systems that the embodiment of the present invention provides, because the transmission path clock affected by jitter2 from the controller 305 in first order phase-locked loop 301 to DDRPHY system, command transfer interface 306, data transmission interface 307 all reduces, the clock signal that then controller 305, command transfer interface 306, data transmission interface 307 receive is subject to the impact of jitter2 also less, therefore, it is possible to the sync rates of the clock signal of raising controller 305, command transfer interface 306, data transmission interface 307 reception;
Because DDRPHY system is positioned on SOC, for transmitting data, order between SOC and DRAM, the sync rates of the clock signal that above-mentioned controller 305, command transfer interface 306, data transmission interface 307 receive improves, then can improve the accuracy transmitting data, order between above-mentioned SOC and dram chip further, and then the exchange velocity of data, order between above-mentioned SOC and dram chip can be improved.
Each embodiment in this specification all adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar part mutually see.
Those skilled in the art should understand, the embodiment of the embodiment of the present invention can be provided as method, device or computer program.Therefore, the embodiment of the present invention can adopt the form of complete hardware embodiment, completely software implementation or the embodiment in conjunction with software and hardware aspect.And the embodiment of the present invention can adopt in one or more form wherein including the upper computer program implemented of computer-usable storage medium (including but not limited to magnetic disc store, CD-ROM, optical memory etc.) of computer usable program code.
The embodiment of the present invention describes with reference to according to the flow chart of the method for the embodiment of the present invention, terminal equipment (system) and computer program and/or block diagram.Should understand can by the combination of the flow process in each flow process in computer program instructions realization flow figure and/or block diagram and/or square frame and flow chart and/or block diagram and/or square frame.These computer program instructions can being provided to the processor of all-purpose computer, special-purpose computer, Embedded Processor or other programmable data processing terminal equipment to produce a machine, making the instruction performed by the processor of computer or other programmable data processing terminal equipment produce device for realizing the function of specifying in flow chart flow process or multiple flow process and/or block diagram square frame or multiple square frame.
These computer program instructions also can be stored in can in the computer-readable memory that works in a specific way of vectoring computer or other programmable data processing terminal equipment, the instruction making to be stored in this computer-readable memory produces the manufacture comprising command device, and this command device realizes the function of specifying in flow chart flow process or multiple flow process and/or block diagram square frame or multiple square frame.
These computer program instructions also can be loaded on computer or other programmable data processing terminal equipment, make to perform sequence of operations step to produce computer implemented process on computer or other programmable terminal equipment, thus the instruction performed on computer or other programmable terminal equipment is provided for the step realizing the function of specifying in flow chart flow process or multiple flow process and/or block diagram square frame or multiple square frame.
Although described the preferred embodiment of the embodiment of the present invention, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of embodiment of the present invention scope.
Finally, also it should be noted that, in this article, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operating space, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or terminal equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or terminal equipment.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the terminal equipment comprising described key element and also there is other identical element.
Above a kind of phase-locked loop systems provided by the present invention is described in detail, apply specific case herein to set forth principle of the present invention and execution mode, the explanation of above embodiment just understands method of the present invention and core concept thereof for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (5)
1. a phase-locked loop systems, is characterized in that, comprising: first order phase-locked loop and second level phase-locked loop; The output of described first order phase-locked loop is connected with the input of described second level phase-locked loop;
Wherein, the input of described first order phase-locked loop is connected with clock;
Described second level phase-locked loop comprises: the phase-locked loop that quantity is corresponding to parts in application system; Described phase-locked loop comprises feedback loop, and the input of described phase-locked loop is closely adjacent with the output of described first order phase-locked loop, and the output of described phase-locked loop is near the input of corresponding component.
2. system according to claim 1, it is characterized in that, described feedback loop is periphery feedback loop, then described phase-locked loop also comprises: the internal feedback loop of disconnection, and input, the output in described internal feedback loop are connected with output with the input in described periphery feedback loop respectively.
3. system according to claim 1, is characterized in that, the output of each phase-locked loop is identical with the distance of the input of corresponding component.
4. system according to claim 2, is characterized in that, the input of each phase-locked loop is identical with the distance of described first order phase-locked loop.
5., according to the arbitrary described system of Claims 1-4, it is characterized in that, the quantity of described second level phase-locked loop is 3.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108173545A (en) * | 2018-01-17 | 2018-06-15 | 上海交通大学 | Phase-locked loop circuit, more phase-locked loop systems and its output phase synchronous method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1862273A (en) * | 2006-01-09 | 2006-11-15 | 北京大学深圳研究生院 | System for testing clock signal dither and method thereof |
| US7433439B1 (en) * | 2002-12-20 | 2008-10-07 | Cypress Semiconductor Corp. | Apparatus, system, and method for synchronizing signals received by one or more system components |
| CN101944912A (en) * | 2010-07-30 | 2011-01-12 | 炬力集成电路设计有限公司 | Monocrystal oscillator electronic device and method for determining frequency division coefficient |
| CN102823137A (en) * | 2010-03-29 | 2012-12-12 | 飞思卡尔半导体公司 | Apparatus and method to compensate for injection locking |
| CN104639162A (en) * | 2013-11-12 | 2015-05-20 | 北京信威通信技术股份有限公司 | Parallel-connected multi-channel RRF (radio-frequency remote unit) device and local oscillator signal generating method thereof |
-
2015
- 2015-09-15 CN CN201510587408.8A patent/CN105187054A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7433439B1 (en) * | 2002-12-20 | 2008-10-07 | Cypress Semiconductor Corp. | Apparatus, system, and method for synchronizing signals received by one or more system components |
| CN1862273A (en) * | 2006-01-09 | 2006-11-15 | 北京大学深圳研究生院 | System for testing clock signal dither and method thereof |
| CN102823137A (en) * | 2010-03-29 | 2012-12-12 | 飞思卡尔半导体公司 | Apparatus and method to compensate for injection locking |
| CN101944912A (en) * | 2010-07-30 | 2011-01-12 | 炬力集成电路设计有限公司 | Monocrystal oscillator electronic device and method for determining frequency division coefficient |
| CN104639162A (en) * | 2013-11-12 | 2015-05-20 | 北京信威通信技术股份有限公司 | Parallel-connected multi-channel RRF (radio-frequency remote unit) device and local oscillator signal generating method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108173545A (en) * | 2018-01-17 | 2018-06-15 | 上海交通大学 | Phase-locked loop circuit, more phase-locked loop systems and its output phase synchronous method |
| CN108173545B (en) * | 2018-01-17 | 2021-08-13 | 上海交通大学 | Phase-locked loop circuit, multi-phase-locked loop system and output phase synchronization method thereof |
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