CN105186493A - Method and system for rapid processing of parasitic defect between secondary circuits - Google Patents
Method and system for rapid processing of parasitic defect between secondary circuits Download PDFInfo
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- CN105186493A CN105186493A CN201510544780.0A CN201510544780A CN105186493A CN 105186493 A CN105186493 A CN 105186493A CN 201510544780 A CN201510544780 A CN 201510544780A CN 105186493 A CN105186493 A CN 105186493A
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Abstract
The invention provides a method for rapid processing of a parasitic defect between secondary circuits. The method comprises the following steps of determining a parasitic phenomenon of the current secondary circuit when the secondary circuit is connected to a parasitic circuit to appear a defect, wherein the parasitic phenomenon comprises a homogenous parasitic phenomenon and a heterogeneous parasitic phenomenon; and determining to enter a homogenous parasitic phenomenon processing mode or a heterogeneous parasitic phenomenon processing mode according to the determined parasitic phenomenon of the current secondary circuit, isolating the defected parasitic circuit and restoring normal operation of the secondary circuit. By applying the method and the system, the parasitic phenomenon between the secondary circuits can be rapidly processed, and the normal functions of the secondary circuit are restored.
Description
Technical field
The present invention relates to secondary loop in power system processing technology field, particularly relate to the method and system of the parasitic defect of a kind of fast processing secondary circuit.
Background technology
In power plant and transformer station, usually electric part is divided into primary equipment and secondary device.Be interconnected to constitute the electric loop monitoring primary equipment, control, regulate and protect by secondary device and be called secondary circuit, the normal operation of electrical production usually can be destroyed or affect to the fault of secondary circuit.And secondary circuit parasitism refers to and alters electrical phenomena between different secondary loop, it causes the parafunctional common phenomenon of secondary circuit.If when second loop return wiring has a parasitic loop, then correct supervision can not be carried out to primary equipment, to the information run, attendant provides mistake, be difficult to the operation conditions judging primary equipment.
Therefore, need the method for the parasitic defect of a kind of fast processing secondary circuit badly, can parasitics between fast processing secondary circuit, recover the normal function of secondary circuit.
Summary of the invention
Embodiment of the present invention technical problem to be solved is, provides the method and system of the parasitic defect of a kind of fast processing secondary circuit, can parasitics between fast processing secondary circuit, recovers the normal function of secondary circuit.
In order to solve the problems of the technologies described above, embodiments provide the method for the parasitic defect of a kind of fast processing secondary circuit, described method comprises:
When second loop return wiring has parasitic loop to occur defect, determine the parasitics in current secondary loop; Wherein, described parasitics comprises homology parasitics and allos parasitics;
According to the parasitics in the described current secondary loop determined, determine to enter the parasitic tupe of homology or the parasitic tupe of allos, isolate defects parasitic loop, recovers described secondary circuit and normally runs.
Wherein, the described parasitics according to the described current secondary loop determined, determines to enter the parasitic tupe of homology or the parasitic tupe of allos, isolate defects parasitic loop, recovers the concrete steps that described secondary circuit normally runs and comprises:
When the parasitics in described current secondary loop is homology parasitics, determine the multiple suspected cables that need remove;
The described multiple suspected cables determined are removed one by one, and measures the current potential of the secondary circuit after the dismounting of each suspected cables one by one, till when the current potential measuring described secondary circuit recovers normal;
Determine the suspected cables removed, and further the described suspected cables of dismounting determined all is isolated as parasitism point, recover described secondary circuit and normally run.
Wherein, described method comprises further:
By in the described suspected cables of dismounting determined one by one multiple connection to described secondary circuit, and guarantee that the secondary circuit current potential after described multiple connection is normal; Wherein, when a suspected cables removed as the suspected cables multiple connection of current multiple connection in described secondary circuit, when making described secondary circuit appearance potential abnormal, then abandon the suspected cables of described current multiple connection, and next suspected cables removed of multiple connection.
Wherein, described multiple suspected cables accesses same voltage source.
Wherein, the described parasitics according to the described current secondary loop determined, determines to enter the parasitic tupe of homology or the parasitic tupe of allos, isolate defects parasitic loop, recovers the concrete steps that described secondary circuit normally runs and also comprises:
When the parasitics of described current parasitic loop is allos parasitics, disconnects or close described secondary circuit power supply sky and open, parasitics is reappeared; Wherein, when described second loop return wiring is simple, disconnects described secondary circuit power supply sky and open; When described second loop return wiring is complicated, closed described secondary circuit power supply sky is opened;
Judge whether there is suspected cables in described secondary circuit;
If, then determine the multiple suspected cables that need remove, and the described multiple suspected cables determined are removed one by one, and measure the current potential of the secondary circuit after the dismounting of each suspected cables one by one, till recovering normally when the current potential measuring described secondary circuit, determine the suspected cables removed further, the described suspected cables of dismounting determined all is isolated as parasitism point, recovers described secondary circuit and normally run;
If not, then determine the auxiliary group of device contact be connected between the multiple adjacent cables that need remove, and the described multiple auxiliary group of device contact determined is removed one by one, and measure the current potential of the secondary circuit after each auxiliary group of device contact one by one, till recovering normally when the current potential measuring described secondary circuit, determine the auxiliary group of device contact of having removed further, the described dismounting determined auxiliary group of device contact is all isolated as parasitism point, recovers described secondary circuit and normally run.
Wherein, described method comprises further:
By in the described suspected cables of dismounting determined one by one multiple connection to described secondary circuit, and guarantee that the secondary circuit current potential after described multiple connection is normal; Wherein, when a suspected cables removed as the suspected cables multiple connection of current multiple connection in described secondary circuit, when making described secondary circuit appearance potential abnormal, then abandon the suspected cables of described current multiple connection, and next suspected cables removed of multiple connection.
Wherein, described multiple suspected cables accesses multiple voltage source.
Wherein, described auxiliary group of equipment is that among circuit breaker, switch, disconnecting link, it is a kind of or it is multiple.
The embodiment of the present invention additionally provides the system of the parasitic defect of a kind of fast processing secondary circuit, and described system comprises:
Parasitics determining unit, during for having parasitic loop to occur defect at second loop return wiring, determines the parasitics in current secondary loop; Wherein, described parasitics comprises homology parasitics and allos parasitics;
Defect processing unit, for the parasitics according to the described current secondary loop determined, determine to enter the parasitic tupe of homology or the parasitic tupe of allos, isolate defects parasitic loop, recovers described secondary circuit and normally runs.
Implement the embodiment of the present invention, there is following beneficial effect:
In embodiments of the present invention, during owing to having parasitic loop to occur defect at second loop return wiring, according to the parasitics of secondary circuit, select different tupes, isolate defects parasitic loop, recover secondary circuit normally to run, thus can parasitics between fast processing secondary circuit, recover the normal function of secondary circuit.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, the accompanying drawing obtaining other according to these accompanying drawings still belongs to category of the present invention.
The flow chart of the method for the parasitic defect of fast processing secondary circuit that Fig. 1 provides for the embodiment of the present invention;
The structural representation of the system of the parasitic defect of fast processing secondary circuit that Fig. 2 provides for the embodiment of the present invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the present invention is described in further detail.
As shown in Figure 1, in the embodiment of the present invention, the method for the parasitic defect of a kind of fast processing secondary circuit provided, described method comprises:
Step S1, when second loop return wiring has parasitic loop to occur defect, determine the parasitics in current secondary loop; Wherein, described parasitics comprises homology parasitics and allos parasitics;
Should be noted that, the parasitics in current secondary loop is by searching parasitic source to determine, because allos parasitics to come judgement by disconnecting wiring simple secondary circuit power supply sky is opened or closed wiring is more complicated secondary circuit power supply sky, after disconnection or closed action complete, if during parasitics reproduction, be then allos parasitics; No, be then homology parasitics.
Step S2, parasitics according to the described current secondary loop determined, determine to enter the parasitic tupe of homology or the parasitic tupe of allos, isolate defects parasitic loop, recovers described secondary circuit and normally runs.
Detailed process is, in step s 2, according to the parasitics of step S1, can select corresponding tupe, isolate defects parasitic loop, recover described secondary circuit and normally run.This tupe comprises the parasitic tupe of homology and the parasitic tupe of allos, and specific implementation step is as follows:
(1) the parasitic tupe of homology: when the parasitics in current secondary loop is homology parasitics, determine the multiple suspected cables that need remove; The multiple suspected cables determined are removed one by one, and measures the current potential of the secondary circuit after the dismounting of each suspected cables one by one, till when the current potential measuring described secondary circuit recovers normal; Determine the suspected cables removed, and further the suspected cables of dismounting determined all is isolated as parasitism point, recover secondary circuit and normally run.
It should be noted that homology parasitism refers to adopt between the difference in functionality loop of same power supply and alter electrical phenomena, therefore in the parasitic tupe of homology, multiple suspected cables accesses same voltage source.
In order to recover the normal cable torn open in demolishing process by mistake, therefore described method comprises further:
By the suspected cables of dismounting determined one by one multiple connection in secondary circuit, and guarantee that the secondary circuit current potential after multiple connection is normal; Wherein, when a suspected cables removed as the suspected cables multiple connection of current multiple connection in secondary circuit, when making secondary circuit appearance potential abnormal, then abandon the suspected cables of current multiple connection, and next suspected cables removed of multiple connection.
(2) the parasitic tupe of allos: when the parasitics of current parasitic loop is allos parasitics, disconnects or closed secondary circuit power supply sky is opened, and parasitics is reappeared; Wherein, when second loop return wiring is simple, disconnects secondary circuit power supply sky and open; When second loop return wiring is complicated, closed described secondary circuit power supply sky is opened;
Judge whether there is suspected cables in secondary circuit;
If, then determine the multiple suspected cables that need remove, and the multiple suspected cables determined are removed one by one, and measure the current potential of the secondary circuit after the dismounting of each suspected cables one by one, till recovering normally when the current potential measuring secondary circuit, determine the suspected cables removed further, the suspected cables of dismounting determined all is isolated as parasitism point, recover secondary circuit and normally run;
If not, then determine the auxiliary group of device contact be connected between the multiple adjacent cables that need remove, and the multiple auxiliary group of device contact determined is removed one by one, and measure the current potential of the secondary circuit after each auxiliary group of device contact one by one, till recovering normally when the current potential measuring secondary circuit, determine the auxiliary group of device contact of having removed further, the auxiliary group of device contact of dismounting determined all is isolated as parasitism point, recovers described secondary circuit and normally run; Wherein, auxiliary group of equipment is that among circuit breaker, switch, disconnecting link, it is a kind of or it is multiple.
It should be noted that allos parasitism refers to adopt between the secondary circuit of different electrical power and alter electrical phenomena, therefore in the parasitic tupe of allos, multiple suspected cables accesses multiple voltage source.
In order to recover the normal cable torn open in demolishing process by mistake, because the method comprises further:
By the suspected cables of dismounting determined one by one multiple connection in secondary circuit, and guarantee that the secondary circuit current potential after multiple connection is normal; Wherein, when a suspected cables removed as the suspected cables multiple connection of current multiple connection in described secondary circuit, when making secondary circuit appearance potential abnormal, then abandon the suspected cables of current multiple connection, and next suspected cables removed of multiple connection.
As shown in Figure 2, in the embodiment of the present invention, the system of the parasitic defect of a kind of fast processing secondary circuit provided, described system comprises:
Parasitics determining unit 210, during for having parasitic loop to occur defect at second loop return wiring, determines the parasitics in current secondary loop; Wherein, described parasitics comprises homology parasitics and allos parasitics;
Defect processing unit 220, for the parasitics according to the described current secondary loop determined, determine to enter the parasitic tupe of homology or the parasitic tupe of allos, isolate defects parasitic loop, recovers described secondary circuit and normally runs.
Implement the embodiment of the present invention, there is following beneficial effect:
In embodiments of the present invention, during owing to having parasitic loop to occur defect at second loop return wiring, according to the parasitics of secondary circuit, select different tupes, isolate defects parasitic loop, recover secondary circuit normally to run, thus can parasitics between fast processing secondary circuit, recover the normal function of secondary circuit.
It should be noted that in said system embodiment, each included system unit is carry out dividing according to function logic, but is not limited to above-mentioned division, as long as can realize corresponding function; In addition, the concrete title of each functional unit, also just for the ease of mutual differentiation, is not limited to protection scope of the present invention.
One of ordinary skill in the art will appreciate that all or part of step realized in above-described embodiment method is that the hardware that can carry out instruction relevant by program has come, described program can be stored in a computer read/write memory medium, described storage medium, as ROM/RAM, disk, CD etc.
Above disclosedly be only present pre-ferred embodiments, certainly can not limit the interest field of the present invention with this, therefore according to the equivalent variations that the claims in the present invention are done, still belong to the scope that the present invention is contained.
Claims (9)
1. a method for the parasitic defect of fast processing secondary circuit, it is characterized in that, described method comprises:
When second loop return wiring has parasitic loop to occur defect, determine the parasitics in current secondary loop; Wherein, described parasitics comprises homology parasitics and allos parasitics;
According to the parasitics in the described current secondary loop determined, determine to enter the parasitic tupe of homology or the parasitic tupe of allos, isolate defects parasitic loop, recovers described secondary circuit and normally runs.
2. the method for claim 1, it is characterized in that, the described parasitics according to the described current secondary loop determined, determine to enter the parasitic tupe of homology or the parasitic tupe of allos, isolate defects parasitic loop, recovers the concrete steps that described secondary circuit normally runs and comprises:
When the parasitics in described current secondary loop is homology parasitics, determine the multiple suspected cables that need remove;
The described multiple suspected cables determined are removed one by one, and measures the current potential of the secondary circuit after the dismounting of each suspected cables one by one, till when the current potential measuring described secondary circuit recovers normal;
Determine the suspected cables removed, and further the described suspected cables of dismounting determined all is isolated as parasitism point, recover described secondary circuit and normally run.
3. method as claimed in claim 2, it is characterized in that, described method comprises further:
By in the described suspected cables of dismounting determined one by one multiple connection to described secondary circuit, and guarantee that the secondary circuit current potential after described multiple connection is normal; Wherein, when a suspected cables removed as the suspected cables multiple connection of current multiple connection in described secondary circuit, when making described secondary circuit appearance potential abnormal, then abandon the suspected cables of described current multiple connection, and next suspected cables removed of multiple connection.
4. method as claimed in claim 2, it is characterized in that, described multiple suspected cables accesses same voltage source.
5. the method for claim 1, it is characterized in that, the described parasitics according to the described current secondary loop determined, determine to enter the parasitic tupe of homology or the parasitic tupe of allos, isolate defects parasitic loop, recovers the concrete steps that described secondary circuit normally runs and also comprises:
When the parasitics of described current parasitic loop is allos parasitics, disconnects or close described secondary circuit power supply sky and open, parasitics is reappeared; Wherein, when described second loop return wiring is simple, disconnects described secondary circuit power supply sky and open; When described second loop return wiring is complicated, closed described secondary circuit power supply sky is opened;
Judge whether there is suspected cables in described secondary circuit;
If, then determine the multiple suspected cables that need remove, and the described multiple suspected cables determined are removed one by one, and measure the current potential of the secondary circuit after the dismounting of each suspected cables one by one, till recovering normally when the current potential measuring described secondary circuit, determine the suspected cables removed further, the described suspected cables of dismounting determined all is isolated as parasitism point, recovers described secondary circuit and normally run;
If not, then determine the auxiliary group of device contact be connected between the multiple adjacent cables that need remove, and the described multiple auxiliary group of device contact determined is removed one by one, and measure the current potential of the secondary circuit after each auxiliary group of device contact one by one, till recovering normally when the current potential measuring described secondary circuit, determine the auxiliary group of device contact of having removed further, the described dismounting determined auxiliary group of device contact is all isolated as parasitism point, recovers described secondary circuit and normally run.
6. method as claimed in claim 5, it is characterized in that, described method comprises further:
By in the described suspected cables of dismounting determined one by one multiple connection to described secondary circuit, and guarantee that the secondary circuit current potential after described multiple connection is normal; Wherein, when a suspected cables removed as the suspected cables multiple connection of current multiple connection in described secondary circuit, when making described secondary circuit appearance potential abnormal, then abandon the suspected cables of described current multiple connection, and next suspected cables removed of multiple connection.
7. method as claimed in claim 5, it is characterized in that, described multiple suspected cables accesses multiple voltage source.
8. method as claimed in claim 5, is characterized in that, described auxiliary group of equipment is that among circuit breaker, switch, disconnecting link, it is a kind of or it is multiple.
9. a system for the parasitic defect of fast processing secondary circuit, it is characterized in that, described system comprises:
Parasitics determining unit, during for having parasitic loop to occur defect at second loop return wiring, determines the parasitics in current secondary loop; Wherein, described parasitics comprises homology parasitics and allos parasitics;
Defect processing unit, for the parasitics according to the described current secondary loop determined, determine to enter the parasitic tupe of homology or the parasitic tupe of allos, isolate defects parasitic loop, recovers described secondary circuit and normally runs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510544780.0A CN105186493A (en) | 2015-08-31 | 2015-08-31 | Method and system for rapid processing of parasitic defect between secondary circuits |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510544780.0A CN105186493A (en) | 2015-08-31 | 2015-08-31 | Method and system for rapid processing of parasitic defect between secondary circuits |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101750540A (en) * | 2009-12-25 | 2010-06-23 | 上海希明电气技术有限公司 | Method for detecting parasitic loop of transformer station direct current system |
| CN201576070U (en) * | 2009-12-25 | 2010-09-08 | 上海希明电气技术有限公司 | Integrated monitoring device for monitoring parasitic loops in DC system of transformer station |
| JP2011223801A (en) * | 2010-04-13 | 2011-11-04 | Chugoku Electric Power Co Inc:The | Dc grounding position searching method, grounding current supply device and dc ground monitoring system |
| CN202502158U (en) * | 2012-03-15 | 2012-10-24 | 上海市电力公司 | Direct current system parasitic circuit resistance measuring device |
| CN203350385U (en) * | 2013-06-18 | 2013-12-18 | 国家电网公司 | Direct current system parasitic circuit on-line detection apparatus |
-
2015
- 2015-08-31 CN CN201510544780.0A patent/CN105186493A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101750540A (en) * | 2009-12-25 | 2010-06-23 | 上海希明电气技术有限公司 | Method for detecting parasitic loop of transformer station direct current system |
| CN201576070U (en) * | 2009-12-25 | 2010-09-08 | 上海希明电气技术有限公司 | Integrated monitoring device for monitoring parasitic loops in DC system of transformer station |
| JP2011223801A (en) * | 2010-04-13 | 2011-11-04 | Chugoku Electric Power Co Inc:The | Dc grounding position searching method, grounding current supply device and dc ground monitoring system |
| CN202502158U (en) * | 2012-03-15 | 2012-10-24 | 上海市电力公司 | Direct current system parasitic circuit resistance measuring device |
| CN203350385U (en) * | 2013-06-18 | 2013-12-18 | 国家电网公司 | Direct current system parasitic circuit on-line detection apparatus |
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Application publication date: 20151223 |