CN105183555A - Hardware virtualization for media processing - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
- G06F9/5077—Logical partitioning of resources; Management or configuration of virtualized resources
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
- G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/461—Saving or restoring of program or task context
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
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- Stored Programmes (AREA)
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Abstract
Each embodiment of the invention relates to hardware virtualization for media processing. Methods and systems for implementing virtual processors are disclosed. For example, in an embodiment a processing apparatus configured to act as a plurality of virtual processors includes a first virtual program space that includes a first program execution memory, the first program execution memory including code to run a non-real-time operating system capable of supporting a one or more non-real-time applications, a second virtual program space that includes a second program execution memory, the second program execution memory including code to run one or more real-time processes, and a central processing unit (CPU) configured to operate in a first operating mode and a second operating mode; the CPU being configured to perform operating system and application activities using the first virtual program space for the first operating mode without using the second virtual program space and without appreciably interfering with the one or more real-time processes that are running in the second operating mode.
Description
divisional application explanation
The application on January 13rd, 2011 submit to, on June 18th, 2012 enter National Phase in China, application number is 201180005023.6, name is called the Chinese invention patent application of " hardware virtualization for media processing " divisional application.
quote combination
This application claims to be incorporated into by overall quoting this, on January 13rd, 2010 submit to, title is the right of priority of the 61/294th, No. 711 U.S. Provisional Applications of " HARDWAREVIRTUALIZATIONFORVoIPMEDIAPROCESSING ".
Technical field
The application relates to the method and system for implementing virtual processor.
Background technology
Here the background description provided is the contextual object for presenting disclosure generally.In the degree that the work of the current inventor named describes this work in the background section and otherwise do not belong to when submitting prior art description in, neither express the prior art be not also impliedly recognized as relative to present disclosure.
Computer based disposal system is all there is in present every part modern consumer electronic installation actually.Such as, residential gateway often also comprises two or three separate processors and each processor performs independent function except other electronic hardware multiple.For example, first processor in telecommunication apparatus (such as gateway) can only for the treatment of Streaming Media (such as ip voice, Internet Protocol Television or IP video), and the second processor in telecommunication apparatus can be used for performing multiple application, such as serve Streaming Media and even other application (as interactive game and calendar are provided).As used herein, term " processor " can refer to one of individual plants and the multiple processors in multi-nuclear processor equipment.
Although the processor stability provided by multiple processor may be wish, multiple processor is used to bring great amount of cost.Usually conventional single-processor solution is avoided; these solution party are configured in software layer, support real-time media process and other both application multiple in theory; because in conventional implementation; if " glitch (glitch) " if come across in the application program run or need software upgrading simultaneously, then can not suitably protect real-time media process.
Summary of the invention
Various aspect of the present invention and embodiment are below more specifically described.
In one embodiment, a kind for the treatment of apparatus being configured to serve as multiple virtual processor comprises: the first virtual program space, comprise the first program execution memory, the first program execution memory comprises the code for running the non-real time operating system can supporting one or more non real-time application; Second virtual program space, comprises the second program execution memory, and the second program execution memory comprises the code for running one or more real-time process; And CPU (central processing unit) (CPU), be configured to operate in the first operator scheme and the second operator scheme, CPU is configured to the first virtual program space to be used for the first operator scheme to be come executive operating system and application activity and not to use the second virtual program space and one or more real-time process of running in this second mode of operation of not obvious interference.
In another embodiment, a kind of being used for comprises in the upper method performing multiple virtual processor of single CPU (central processing unit) (CPU): limit the first virtual program space comprising the first program execution memory, the first program execution memory is configured to run the non-real time operating system can supporting one or more non real-time application; Limit the second virtual program space comprising the second program execution memory, the second program execution memory is configured to run one or more real-time process; And CPU switching is so that between the first operator scheme and the second operator scheme alternately, thus at the first operator scheme period CPU from the first virtual program spatial operation, thus make the real-time process that the not obvious interference of any operant activity occurred during the first operator scheme performs during the second operator scheme.
Accompanying drawing explanation
Describe the various embodiments of the present disclosure exemplarily proposed in detail with reference to the following drawings, similar label quotes similar elements in the accompanying drawings, and in the accompanying drawings:
Fig. 1 depicts can as the disposal system of two independent virtual processor work.
Fig. 2 depicts the details of the CPU of Fig. 1.
Fig. 3 depicts the sequential chart for two virtual processors implementing Fig. 1.
Fig. 4 summarises for using single processor to perform the process flow diagram of the operation of the method and system disclosed in multiple virtual processor.
Embodiment
The method and system of following discloses in general manner and can be described in concrete example and/or specific embodiment.Such as, when quoting detailed example and/or embodiment, any ultimate principle described by attention, unless otherwise expressing, will be not limited to single embodiment as is understood by those of ordinary skill, but can be expanded for using together with system with any other method described herein.
Hereafter describe the disposal system that one has single CPU (central processing unit) (CPU), this CPU is configured to serve as two independent virtual processor: in one embodiment, and a virtual processor is configured to use operating system to run common application; Another virtual processor is configured to perform process in real time with reliable fashion.A special advantage of method and system described below is: be different from multiprocessing on the surface of known operation system (such as, different windows in software layer runs different application), how all the embodiment of virtual processor described below is designed to utilize different hardware thread and allows any possible fault execution time key operation of another virtual processor of virtual processor thus.Therefore, in one embodiment, although use single cpu, even if a virtual processor still reliably performs various real time critical process operation when another virtual processor experience may need to reboot " collapse " that solve and does not interrupt.
Fig. 1 depicts the treating apparatus 100 be configured to as two independent virtual processor work according to an embodiment.As shown in fig. 1, treating apparatus 100 comprises CPU110, Memory Management Unit (MMU) 112, interrupt control circuit 114, timer circuit 116, first virtual program space 120 and the second virtual program space 130.First virtual program space 120 and the second virtual program space 130 be CPU110 can total memory space 111 in limit independent space.
In one embodiment, the first virtual program space 120 comprises the first program execution memory 122, first memory 124 and is coupled to one group of first input/output circuitry 126 of the various peripheral hardware such as such as keypad, display, loudspeaker of any number.First program execution memory 122 comprises for running the code can supporting the non-real time operating system (OS) of multiple application (human interaction such as without the need to the accurate response time is applied (such as, keypad typing and display)).First memory 124 comprises can writing of any number and type and the storer (such as volatibility and nonvolatile RAM (RAM)) read from it, to support resident OS and application in the first program execution memory 122.
In one embodiment, the second virtual program space 130 comprises the second program execution memory 132, second memory 134 and is coupled to such as sending in time division multiplex (TDM) mode of any number and variously with the port of the grouping received based on wireless medium, T1/E1 data-interface, Ethernet interface etc. communicates/one group of second input/output circuitry 136 of media peripheral hardware.
Second program storage 132 comprises write being configured to run and can processing the code of the multiple real-time processes importing and spread out of media in time thereon.Such as, in one embodiment, the second program storage 132 comprise the code that processes for voice-over ip (VoIP) and/or for any number speech codec, dtmf relay support, packet loss concealment, echo cancellation, voice activity detection, comfort noise generates, general multitone generates and/or detects, caller ID generates and/or detects, voice mixing and fax generates and the code of decoding.Similar to the first memory 124, the second memory 134 comprises the storer that can write and read of any number and type to support real-time process.
For the object of present disclosure, note storer 122,124,132 and 134 to be depicted as entities different in logic, but in one embodiment, they are combined in single memory unit physically.Such as, In a particular embodiment, first memory 124 and the second memory 134 exist as two unitary part of single RAM, and the first program execution memory 122 and the second program execution memory 132 exist as the unitary part of another single memory equipment (such as ROM (read-only memory) (ROM)).Alternatively, in another embodiment, all four storeies 122,124,132 and 134 are as the different piece of single memory equipment or as the different memory section existence be incorporated in integrated circuit.
Generally speaking, as long as the OS of the first operating space and application " obviously cannot disturb " execution of the real-time process of the second operating space 130, then the resource between the first operating space 120 with the second operating space 130 is overlapping is possible.Such as, first program execution memory 122 and the second program execution memory 132 can share common code section (such as, be embedded in the basic input/output (BIOS) in ROM) in order to avoid code repeats, as long as such sharing does not cause the execution obviously disturbing the real-time process of the second operating space 130.In addition, some memory resource (such as cache memory transparent for (except performance enhancement) being performed for code) can be shared between operating space 120 and 130 and in the context of present disclosure, not be considered as the execution that it obviously disturbs the real-time process of the second operating space 130.
In operation, treating apparatus 100 performs hardware initialization process (such as power on and reboot), thus makes all devices 110-136 be arranged to predefine or original state.
In operation, this group second input/output circuitry 136 in CPU110 initialization interrupt control circuit 114, timer circuit 116 and the second virtual program space 130.The some parts of interrupt control circuit 114 and timer circuit 116 or be all regarded as the part in the second virtual program space 130.In various embodiments, MMU112, interrupt control circuit 114, timer circuit 116 and may certain part of this group second input/output circuitry 136 be " fixing " equipment of being programmed, thus make CPU only have very limited impact to their behavior or without impact.In such embodiments, the initialization in the second virtual program space 120 is the very limited tasks be such as limited to the circular buffer in the second memory 134 or pointer zero.
MMU112 is the hardware component being responsible for the access to storer and peripherals that process is asked by CPU110.Its function comprises and becomes physical address (i.e. virtual storage management), storage protection, high-speed cache to control and bus arbitration virtual address translation.This MMU112 is configured to just generate when storage protection is violated and occurred interrupt or mark.
Interrupt control circuit 114 is following equipment, and this equipment is used for that some interrupt source is combined to one or more CPU and may have access on circuit, allows the interrupt output to it to distribute priority-level simultaneously.This interrupt control circuit 114 has the ability to present to CPU110 the interruption of not maskable, high-priority interrupt (such as indicating the interruption of TDM frame boundaries) and multiple more low priority.
Timer circuit 116 is used to regularly generate the counter interrupted, and these interruptions can be high priority, not maskable and/or more low priority.
In one embodiment, CPU110 also this group first input/output circuitry 126, then initialization first program execution memory in initialization first virtual program space 120 OS and such as relate to the application of any concrete mark such as application of update service application.
In the embodiment in figure 1, interrupt control circuit 114 comprises CPU110 and cannot " high priority " of universal shield (directly or indirectly) interrupt.Therefore, upon initialization, so not maskable, high-priority interrupt force CPU110 to switch from first (non real-time) operator scheme of the resource in use first virtual program space 120 to second (in real time) operator scheme of the resource in use second virtual program space 130.Suitably interruption return command is used to realize back switching from the second operator scheme to the first operator scheme.Therefore, two " virtual " processors can be maintained.The example of maskable, high-priority interrupt does not comprise quick-speed interruption (FIQ) circuit shared by shared not maskable interrupts (NMI) circuit of the processor based on Intel8086 and arm processor.
In various embodiments, wish that any activity (such as, fault) ensureing to occur in a virtual processor does not cause the obvious interference to another virtual processor.In order to realize this point, MMU112 is configured to stop the software operated from the first operating space 120 may affect the storer of the second operating space 130 and any equipment by harmful way.Such as, using MMU112, suitably notifying that CPU110 (time in a first mode of operation) when performing the code from the OS in the first virtual program space 120 and/or any application does not access or otherwise change the second memory 134 or the second input/output circuitry 136.Similarly, in one embodiment, do not access or otherwise change the first memory 124 or the first input/output circuitry 126 is useful when using MMU112 to make CPU110 in this second mode of operation.By ensureing the exclusivity (or at least guaranteeing noiseless) of the resource between the first virtual program space 120 and the second virtual program space 130, effectively prevent the activity that obviously may affect another operator scheme---the especially fault occurred in an operator scheme.
In order to ensure the operation of not obvious another virtual processor of interference of virtual processor further, in one embodiment, in response to activation high-priority interrupt, store the mode of operation of CPU110, thus make the CPU mode of operation retaining the first operator scheme when CPU operates in this second mode of operation.By retaining such mode of operation to " press-in " mode of operation in the software stack be positioned on the second memory, and rebuild these modes of operation by back " pulling " data stored from software stack to suitable CPU register.Alternatively, such state is stored in the special memory built in CPU110.
Fig. 2 show the CPU100 of Fig. 1 of an embodiment according to disclosure as lower part, this part comprises Status Flag register 210, one group of data register 212, group address pointer 214 and programmable counter 216.Although shown register 210-216 is present in most cpu type (comprising the ARM circuit of processor) usually, but note, the shown register/mode of operation 210-216 of Fig. 2 also non exhaustively to store and the type of mode of operation useful in fetching and number in interrupting arranging.As shown in Figure 2, the value of various register 210-216 receives a certain signal triggering high-level interruption in response to CPU110, be stored in mailbox memory 220-226.Also as shown in Figure 2, the value of various register 210-216 can return in response to from high-level interruption, and the corresponding mailbox memory 220-226 by them stores again.Thus, serve high-priority interrupt at CPU and return from high-priority interrupt time retain key operation state.
The same with the mode of operation of reservation first operator scheme, in one embodiment, CPU is configured to the various modes of operation storing the second operator scheme when changing to the first operator scheme, thus makes to receive next high-level interruption, the mode of operation that Fast Reconstruction is such in response at CPU place.
For the system of drives interrupts, there is the multiple useful scheme being used for triggered interrupts or interrupt flow.Such as, wherein according in an embodiment of rule or irregular interval receiving media packet streams, the signal post (semaphore) (such as leaving the FLAG signal of this group second input/output circuitry 136) of a certain form is used for triggering high-priority interrupt at interrupt control circuit 114.Such interrupt scheme allows suitably to process media packet in real time on " as required " basis.
In another embodiment, timing circuit (timer circuit 116 of such as Fig. 1) is used for regularly triggering high-priority interrupt.Suppose that the cycle of timer circuit 116 is abundant, then suitably process media packet and non-fault during those periods when serving high-priority interrupt.
In one embodiment, timer circuit 116 is configured to regularly trigger high-priority interrupt according to the interval more less than the interval sent to treating apparatus 100 or divided into groups by treating apparatus 100 receiving media.In one embodiment, when the real-time process in the second virtual program space 130 be properly configured on multiple time slot, process media packet time, the application performed in the first virtual program space 120 performs with the time delay obviously reduced.
With reference to the sequential chart 300 that Fig. 3, this figure are following suitably interrupt scheme, in this scenario, the treating apparatus 100 of Fig. 1 switches between its first operator scheme and its second operator scheme.In the example of fig. 3, send in time division multiplex (TDM) scheme according to ten milliseconds of speed of often dividing into groups and receiving media grouping (not shown).But, interrupt be configured to every two milliseconds of appearance, wherein note the definite duration of the second operator scheme time slot and frequency dynamic adjustable with the service quality considering media packet (QoS) requirement.Therefore, the process bandwidth of CPU (CPU110 of such as Fig. 1) is divided into one group of the first frame/time slot 310 of first (non real-time) operator scheme (O.M.) and one group of the second frame/time slot 320 of second (in real time) O.M..By using such process bandwidth to arrange, not only set up the first virtual processor and the second virtual processor, and reduce the time delay of the application run during the first operator scheme.Such as, if timing resolution is increased to two milliseconds from eight milliseconds, then the residential gateway application of the support game on line run during the first operator scheme can illustrate that obvious subjective performance improves.
Fig. 4 shows the process flow diagram operating multiple virtual processor according to the use single cpu of an embodiment of disclosure.That is, the process flow diagram of Fig. 4 shows a kind of method of hardware virtualization (as compared with the multithreading using multiple processor or software multitask on a single processor) of the multithreading on single processor.Although conveniently and by step described below be described as occurring according to particular order, note, the order of various operation can change with embodiment.Also note, various operation can occur simultaneously or it can be made to occur in an overlapping arrangement.
This process starts from S402, and the hardware wherein performing following treating apparatus resets, and this device has single cpu and two independent operating spaces---the first (in real time) operating space and second (non real-time) operating space.Then, in step s 404, initialization is used for the second operating space of process in real time.As discussed above, initialization can relate to initialization memory, input/output circuitry, timing circuit and interrupt control circuit.When input/output circuitry, timing circuit and interrupt control circuit can be programmed by CPU, timing circuit and/or interrupt circuit are configured to generate not maskable, high-priority interrupt in response to receiving media grouping or to generate according to the interval that (alternatively) is more less than the interval of the media packet received according to a certain cycle interrupt.But, because input/output circuitry, timing circuit and interrupt control circuit can not be changed in some other embodiment, so CPU the such equipment of initialization and the generation of high-priority interrupt can not remain the function of hardware structure.Control to continue step S406.
In step S406, initialization is used for the operating space in Non real time program space.As discussed above, in one embodiment, such initialization comprises initiating hardware (such as storer and input/output circuitry) and initialized operating system and treats the various application that run on an operating system.Control to continue step S410.
In step S410, carry out the determination about whether having generated high-priority interrupt.As discussed above, such high-priority interrupt is used for enabling CPU to switch between the first operator scheme (wherein the operating system of operating procedure S406 and respective application) and the second operator scheme (wherein the real-time process of operating procedure S404).When generating high-priority interrupt, control to step S412 redirect; Otherwise, control to step S422 redirect.
In step S412, in response to high-priority interrupt, perform the real-time process of step S404 and protect it from the impact of the operating system performed in other step or any non real-time application.As discussed above, in various embodiments, the mode that such real-time process is also configured to reduce the time delay of at least one application initialized in step S406 processes Streaming Media grouping on multiple time slot.Then, in step S414, perform from the second operator scheme returning to the first operator scheme.Control then to return to step S410, wherein receive more multiple interrupt and carry out for each interruption being whether the determination of high-priority interrupt to the interruption received.
In step S422, when the interruption determining to receive is not high-priority interrupt, perform initialized non real-time application and support OS function in step S406.Equally; as discussed above, the hardware protection (MMU112 of such as Fig. 1) being incorporated to a certain form disturbs the real-time process of step S412 to be useful to prevent OS and/or non real-time application examples such as the storer or input/output circuitry by inadvertently changing real-time process use.Then, in step S430, the determination whether come across about fault in one of operating system or application is carried out.Some examples of fault such as comprise the following instruction from MMU, it indicates that and to have carried out the trial of access invalidated memory location or resource or be engaged in and identified infinite software cycles by use Watch Dog Timer subsequently.If fault occurs, then control to continue step S432; Otherwise, control to step S410 back redirect.
In step S432, operation is rebooted to the hardware executing software be associated with step S406, and control to step S406 back redirect, wherein reinitialize operating system and respective application.Because software reboots operation without the need to using high-priority interrupt, so will understand software guiding operation only will affect CPU normally those equipment addressable and storage space during the first operator scheme, and therefore the real-time process of the second operator scheme will remain unaffected.
Although describe the present invention in conjunction with the specific embodiment exemplarily proposed of the present invention, it is clear that many alternative, modifications and variations will be obvious to those skilled in the art.Thus, the embodiments of the invention as set forth here are intended to example and unrestricted.There is the change can made without departing from the scope of the invention.
Claims (14)
1., for the treatment of a method for media packet, comprising:
There is the packet handler place receiving media packet streams of single cpu;
Be two or more frame of protected process operation by the process division of operations of the media packet for the treatment of reception, the time of the passage of two or more frame described in wherein operating for the treatment of protected process is less than the time interval between the described reception to the media packet in described stream and the corresponding frame that protected process operates temporarily is separated;
In the described time interval between the described reception to the media packet in described stream; between following alternately: (i) at described CPU place, perform in protected processing environment by the corresponding frame of the protected process operation of other process operating influences, and (ii) discharge described CPU with between the described temporary transient separation period between the described frame of protected process operation, in non-protected processing environment, optionally perform other process operate.
2. the method for the treatment of media packet according to claim 1, also comprises:
Change to described protected processing environment from described non-protected processing environment in response to interruption; And
Generate described interruption according to the interrupt interval being less than the described time interval, wherein said interrupt interval is dynamically regulated based on the quality of service requirement of described media packet.
3. the method for the treatment of media packet according to claim 1, wherein said protected processing environment processes the described media packet of reception in real time.
4. the method for the treatment of media packet according to claim 1, also comprises:
Not maskable, high-priority interrupt stream is generated, to make described CPU switch to described protected processing environment time in described non-protected environment.
5. the method for the treatment of media packet according to claim 4; the each high-priority interrupt wherein generated in described high-priority interrupt comprises the mode of operation storing described CPU, thus makes the CPU mode of operation retaining described non-protected processing environment when described CPU operates in described protected processing environment.
6. the method for the treatment of media packet according to claim 4, also comprises the described CPU of operation to process voice-over ip (VoIP) media during described protected processing environment.
7. a media packet processor, comprising:
Single process core, described in be arranged to receiving media packet streams; And
CPU (central processing unit) (CPU), it is two or more frame that protected process operates that described CPU is arranged to the process division of operations of the media packet for the treatment of reception, and the time of the passage of two or more frame described in wherein operating for the treatment of protected process is less than the time interval between the described reception to the media packet in described stream and the corresponding frame that protected process operates temporarily is separated;
Wherein, in the described time interval between the described reception to the media packet in described stream; described CPU to be arranged between following alternately: (i) at described CPU place, perform in protected processing environment by the corresponding frame of the protected process operation of other process operating influences, and between (ii) described temporary transient separation period between the described frame of described protected process operation, in non-protected processing environment, optionally perform other process operate.
8. media packet processor according to claim 7; also comprise interrupt control circuit; described interrupt control circuit is arranged to and generates not maskable, high-priority interrupt stream, and described not maskable, high-priority interrupt stream make described CPU switch from described protected processing environment to described non-protected processing environment.
9. media packet processor according to claim 7; also comprise the first state memory; described first state memory stores the mode of operation of described CPU in response to activating high-priority interrupt, thus makes the CPU mode of operation retaining described protected processing environment when described CPU operates in described non-protected processing environment.
10. media packet processor according to claim 9; also comprise the second state memory, described second state memory stores the CPU mode of operation of described non-protected processing environment when described CPU operates in described protected processing environment.
11. media packet processors according to claim 8, wherein during described protected processing environment, described CPU is programmed for supporting voice-over ip (VoIP) media processing.
12. media packet processors according to claim 7, also comprise timer circuit, described timer circuit is arranged to and regularly triggers high-priority interrupt according to the interval more less than the described time interval of the media packet received by described single process core, and the mode that other process described operation is arranged to the time delay reducing at least one application run on described CPU processes media packet on multiple time slot.
13. media packet processors according to claim 11; at least one item wherein in duration of two or more frame described of protected process operation and frequency is dynamically adjustable, to consider service quality (QoS) requirement of described media packet.
14. media packet processors according to claim 7, wherein said protected processing environment processes the described media packet of reception in real time.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US29471110P | 2010-01-13 | 2010-01-13 | |
| US61/294,711 | 2010-01-13 | ||
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| CN102833175B (en) * | 2012-09-21 | 2016-05-04 | 中国科学院声学研究所 | Based on real-time relay transmission engine and the method for OS |
| CN102902576B (en) * | 2012-09-26 | 2014-12-24 | 北京奇虎科技有限公司 | Method, server and system for rendering webpages |
| GB2516435A (en) * | 2013-04-05 | 2015-01-28 | Continental Automotive Systems | Embedded memory management scheme for real-time applications |
| US9262198B2 (en) * | 2013-08-26 | 2016-02-16 | Vmware, Inc. | CPU scheduler configured to support latency sensitive virtual machines |
| DE102016214117A1 (en) * | 2016-08-01 | 2018-02-01 | Siemens Aktiengesellschaft | Determining an execution time of a user program |
| US20180152319A1 (en) * | 2016-11-28 | 2018-05-31 | Schlumberger Technology Corporation | Well Construction Site Communications Network |
| WO2018107394A1 (en) * | 2016-12-14 | 2018-06-21 | Intel Corporation | I/o emulation abortion in virtualized environments |
| EP3540539A1 (en) * | 2018-03-15 | 2019-09-18 | Siemens Aktiengesellschaft | Method for carrying out the computer-aided simulation of the operation of an automatic machine |
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| US7748003B2 (en) * | 2004-12-20 | 2010-06-29 | International Business Machines Corporation | Hard real-time response |
| EP3598304A1 (en) * | 2006-02-09 | 2020-01-22 | Texas Instruments Incorporated | Virtual cores and hardware-supported hypervisor integrated circuits, systems, methods and processes of manufacture |
| JP2008108075A (en) * | 2006-10-25 | 2008-05-08 | Matsushita Electric Ind Co Ltd | Task switch control method, and computer system |
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| EP2210153B1 (en) * | 2007-11-13 | 2013-04-24 | Rockwell Automation Technologies, Inc. | Industrial controller using shared memory multicore architecture |
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