CN105162314B - A kind of over-current detection circuit for BUCK converters - Google Patents
A kind of over-current detection circuit for BUCK converters Download PDFInfo
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- CN105162314B CN105162314B CN201510575228.8A CN201510575228A CN105162314B CN 105162314 B CN105162314 B CN 105162314B CN 201510575228 A CN201510575228 A CN 201510575228A CN 105162314 B CN105162314 B CN 105162314B
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Abstract
The present invention relates to electronic circuit technology field, more particularly to a kind of over-current detection circuit for BUCK converters.Whether major programme of the invention is that can determine whether currently excessively stream occurs by the real-time detection to switching node SW current potentials of Cycle by Cycle.After excessively stream occurs, the upset of excessively stream comparator can shield upper pipe by logic control circuit, keep down tube to open until excessively stream is released.In addition; if continuous 7 cycles detect electric current; the built-in counter counts of circuit can completely control Ctrl signals to overturn afterwards; then excessively stream threshold value limit is reduced; inductive current to a lower value is adjusted in the case where circuit occurs to continue overcurrent condition; circuit overheat, further protective effect is played to circuit in the case of preventing electric current excessive.After excessively stream is released, counter cleaning, the value crossed before ductility limit threshold value is returned to.Beneficial effects of the present invention are to realize a quick adjustment process；The conducting resistance also to lower power tube positive temperature coefficient is compensated simultaneously, makes sampling more accurate.
Description
Technical field
The invention belongs to electronic circuit technology field, more particularly to a kind of over-current detection electricity for BUCK converters
Road.
Background technology
In recent years, with the fast development of power electronics and electronic technology, BUCK converters are in computer, communication, industry
The fields such as automation, electronics or electric instrument are more widely applied.In BUCK converters, high-power MOSFET tube in technology and
Using above there has also been more new breakthrough, pressure drop is more and more lower, and switching speed is more and more faster, by its outstanding HF switch characteristic
And be widely used, but switch mosfet pipe has the weaker ability for bearing short-time overload, in power supply short circuit, internal short-circuit etc.
Under abnormal conditions, the power consumption of generation can be increased dramatically, so as to influence the normal work of switch mosfet pipe, and it may be produced
Permanent damage.Therefore in order to protect switch mosfet pipe, generally current foldback circuit is needed inside BUCK converters.Cross
Stream protection circuit, then according to the size of sample rate current, corresponding actions is carried out by control circuit first to current sample.It is the most frequently used
Current sample method be that sampling resistor is connected with inductance or power device, but this method inductive current or power device
The electric current of part will flow through sampling resistor, therefore power consumption penalty is larger.In the application scenario for requiring low voltage high current, its shortcoming shows
Obtain serious all the more.The conventional method of another kind is to carry out sample rate current using integrating circuit, although this method loss is small, but increases
The difficulty of circuit design.
The content of the invention
It is to be solved by this invention, aiming at asking that the conventional overcurrent protection circuit in above-mentioned BUCK converters is present
Topic, proposes a kind of over-current detection circuit for BUCK converters.
To achieve the above object, the present invention is adopted the following technical scheme that：
A kind of over-current detection circuit for BUCK converters, including first resistor R1, second resistance R2,3rd resistor
R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8, the 9th resistance R9, a PMOS
Pipe MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6,
7th PMOS MP7, the 8th PMOS MP8, the 9th PMOS MP9, the tenth PMOS MP10, the 11st PMOS MP11,
12 PMOS MP12, the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th
NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 9th NMOS tube MN9, the tenth NMOS tube
MN10, the 11st NMOS tube MN11, the 11st NMOS tube MN12, the 13rd NMOS tube MN13, the 14th NMOS tube MN14,
15 NMOS tube MN15, a NLDMOS pipes NLDMOS1, the 2nd NLDMOS pipes NLDMOS2, the 3rd NLDMOS pipes NLDMOS3,
Four NLDMOS pipes NLDMOS4, the 5th NLDMOS pipes NLDMOS5, the first electric capacity C1, the second electric capacity C2, triode, operation amplifier
Device, comparator, phase inverter and current source；
The positive input of operational amplifier connects external reference voltages, and its negative input is followed by by the 7th resistance R7
Ground, the grid of the first NMOS tube MN1 of its output termination；The drain electrode of the first NMOS tube MN1 connects power supply, and its source electrode passes through the 9th resistance
R9 is followed by the drain electrode of the 15th NMOS tube MN15；The grid of the 15th NMOS tube MN15 connects the first external control signal, its drain electrode
By being interconnected with its source electrode after the 8th resistance R8, its source electrode after the 7th resistance R7 by being grounded；
The source electrode of the 12nd PMOS MP12 connects the output end of current source, and its grid connects outside enable signal, and its drain electrode connects
The drain electrode of the second NMOS tube MN2；The grid of the second NMOS tube MN2 connects the drain electrode of the 12nd PMOS MP12, and its source electrode connects the 3rd
The drain electrode of NMOS tube MN3；The grid of the 3rd NMOS tube MN3 connects the drain electrode of the 12nd PMOS MP12, and its source electrode meets the 4th NMOS
The drain electrode of pipe MN4；The grid of the 4th NMOS tube MN4 connects the source electrode of the 3rd NMOS tube MN3, its source ground；
The colelctor electrode of triode connects power supply, and its base stage connects the source electrode of the first NMOS tube MN1, and its emitter stage connects the 6th NMOS tube
The drain electrode of MN6；The grid of the 6th NMOS tube MN6 connects the source electrode of the second NMOS tube MN2, and its source electrode connects the leakage of the 5th NMOS tube MN5
Pole；The grid of the 5th NMOS tube MN5 connects the source electrode of the 3rd NMOS tube MN3, its source ground；
The source electrode of the first PMOS MP1 connects power supply, its grid and drain interconnection, and its drain electrode connects the leakage of the 8th NMOS tube MN8
Pole；The grid of the 8th NMOS tube MN8 connects the source electrode of the second NMOS tube MN2, and its source electrode connects the drain electrode of the 7th NMOS tube MN7；7th
The grid of NMOS tube MN7 connects the source electrode of the 3rd NMOS tube MN3, its source ground；
The source electrode of the second PMOS MP2 connects power supply, and its grid connects the grid of the first PMOS MP1, and its drain electrode connects the 3rd
The source electrode of the source electrode of PMOS MP3 and the 4th PMOS MP4；The grid of the 3rd PMOS MP3 connects the emitter stage of triode, its leakage
Pole connects the drain electrode of the 11st NMOS tube MN11；The grid of the 4th PMOS MP4 connects the source electrode of the 2nd NLDMOS pipes NLDMOS2, its
Drain electrode connects the drain electrode of the tenth NMOS tube MN10；
The source electrode of the 5th PMOS MP5 connects power supply, its grid and drain interconnection, its source electrode for missing the 6th PMOS MP6；
The grid and drain interconnection of the 6th PMOS MP6, it misses the drain electrode for meeting the 9th NMOS tube MN9；The grid of the 9th NMOS tube MN9
The source electrode of the 3rd NMOS tube MN3 is connect, its source ground；
The source electrode of the 7th PMOS MP7 connects power supply, and its grid connects the grid of the 9th PMOS MP9, and it is missed and connects the 8th
The source electrode of PMOS MP8；The grid of the 8th PMOS MP8 connects the drain electrode of the 6th PMOS MP6, and it is missed and connects the 7th PMOS
The drain electrode of the grid of MP7 and the 12nd NMOS tube MN12；The grid of the 12nd NMOS tube MN12 connects the source of the second NMOS tube MN2
Pole, its source electrode connects the drain electrode of the tenth NMOS tube MN10；The grid of the tenth NMOS tube MN10 connects the source electrode of the 3rd NMOS tube MN3, its
Source ground；
The source electrode of the 9th PMOS MP9 connects power supply, and its drain electrode connects the source electrode of the tenth PMOS MP10；Tenth PMOS MP10
Grid connect the drain electrode of the 6th PMOS MP6, its drain electrode connects the drain electrode of the 13rd NMOS tube MN13；13rd NMOS tube MN13's
Grid connects the source electrode of the second NMOS tube MN2, and its source electrode connects the drain electrode of the 11st NMOS tube MN11；The grid of the 11st NMOS tube MN11
Pole connects the source electrode of the 3rd NMOS tube MN3, its source ground；
The source electrode of the 11st PMOS MP11 connects power supply, and its grid connects the drain electrode of the tenth PMOS MP10, and its drain electrode is successively
The drain electrode of the 11st NMOS tube MN11 is followed by by the first electric capacity C1 and the 4th resistance R4；
The voltage signal of the one termination BUCK converter switches nodes of second resistance R2, its other end passes through first resistor R1
It is followed by the drain electrode of a NLDMOS pipes NLDMOS1 and the drain electrode of the 2nd NLDMOS pipes NLDMOS2；First NLDMOS pipes NLDMOS1
Grid connect the second external control signal, its source electrode connects the source electrode of the 4th NLDMOS pipes NLDMOS4；4th NLDMOS is managed
The grid of NLDMOS4 connects the output end of phase inverter, and its drain electrode connects the source electrode of the 14th NMOS tube MN14；First NLDMOS is managed
NLDMOS1 source electrodes are connected with the tie point of the 4th NLDMOS pipe NLDMOS4 source electrodes with the drain electrode of the 11st PMOS MP11；Second
The grid of NLDMOS pipes NLDMOS2 connects the second external control signal, and its source electrode connects the source electrode of the 5th NLDMOS pipes NLDMOS5；The
The grid of five NLDMOS pipes NLDMOS5 connects the output end of phase inverter, and its drain electrode after 3rd resistor R3 by being grounded；2nd NLDMOS
Pipe NLDMOS2 source electrodes are connected with the tie point of the 5th NLDMOS pipes NLDMOS5 with the grid of the 4th PMOS MP4；
The drain electrode of the 3rd NLDMOS pipes NLDMOS3 connects the tie point of first resistor R1 and second resistance R2, and its grid connects
Two external control signals, its source electrode connects the drain electrode of the 14th NMOS tube MN14；The grid of the 14th NMOS tube MN14 connects phase inverter
Output end；The input of phase inverter terminates the second external control signal；
The positive input ground connection of comparator, its reverse input end connects the source electrode of the 3rd NLDMOS pipes NLDMOS3, its output
Hold the output end for over-current detection circuit.
Beneficial effects of the present invention are the current foldback circuit for devising a kind of detection of Cycle by Cycle, when the week for 7 weeks phase still
During generation excessively stream, the threshold value of ductility limit can be reduced, so as to realize a quick adjustment process to output；While circuit of the invention
Conducting resistance also to lower power tube positive temperature coefficient is compensated, and makes sampling more accurate.
Brief description of the drawings
Fig. 1 is principle schematic of the invention；
Fig. 2 is the flow chart of over-current detection principle；
Fig. 3 is the Time-Series analysis figure of over-current detection principle；
Fig. 4 is inductive current waveform diagram；
Fig. 5 is the circuit structure diagram of over-current detection circuit of the invention.
Specific embodiment
Below in conjunction with the accompanying drawings, technical scheme is described in detail：
The protection carried out to system or load in output short-circuit or overload, as overcurrent protection.Current foldback circuit is first
First to current sample, then according to the size of sample rate current, corresponding actions are carried out by control circuit.The most frequently used current sample side
Method is that sampling resistor is connected with inductance or power device, but the electric current of this method inductive current or power device will flow
Over-sampling resistance, therefore power consumption penalty is larger.In the application scenario for requiring low voltage high current, its shortcoming seems serious all the more.
The conventional method of another kind is to carry out sample rate current using integrating circuit, although this method loss is small, but increased circuit design
Difficulty.
When lower power tube is turned on, the conducting resistance that its drain terminal voltage is equal to lower power tube is multiplied by inductive current.Such as Fig. 1 institutes
Show, can be that can determine whether currently whether occurred by the real-time detection to switching node SW current potentials of Cycle by Cycle based on this principle
Stream.The operation principle of circuit is elaborated with reference to the over-current detection principle flow chart of Fig. 2：After excessively stream occurs, excessively stream compares
Device is overturn, and upper pipe can be shielded by logic control circuit, keeps down tube to open until excessively stream is released.If additionally, continuous 7 week
Phase detects electric current, and the completely rear control signal Ctrl upsets of built-in counter counts of circuit then adjust excessively stream threshold value and are limited to one
Individual lower value Iocl_L, plays a quick adjustment process under overcurrent condition to inductive current.After excessively stream is contacted, count
Device can be cleared up, current threshold return to before value Iocl_H.
In Fig. 1, A point current potentials (are produced) by the clamper of amplifier OP to K × Vref-Vbe1 by internal front stage circuits, by electricity
Hinder R1, R2 partial pressure we can obtain：
After excessively stream is detected, the voltage of Vcomp is less than PGND, i.e. Vcomp<0, then have：
The conducting resistance of power tube is set for RDS (on) MB, is then had：
VSW=-IL×RDS(ON)MB
So
Excessively stream threshold value limit can be write as：
From formula it can be seen that, the size for adjusting K is the size of adjustable excessively stream limit；Additionally, the Vbe1 of negative temperature coefficient exists
The error that the positive temperature coefficient of power tube is brought can be compensated in certain temperature range, it is ensured that the test point of excessively stream is more accurate.
Next over-current detection circuit is further elaborated with reference to Fig. 3：OCP_Flag is the output of excessively stream comparator,
Height is output as after detecting excessively stream.Ton_Flag signals are the output of turn-on time generation circuit, and ON time is exported after terminating
Trailing edge.Signal LA is the control signal of minimum turn-off time, and after upper pipe turns off ShiShimonoseki to be opened, LA exports one section of decline arteries and veins
Punching, its width is the system minimum turn-off time.EN signals are used for locked upper pipe to enable signal after LB signal high jumps, keep
Down tube is always on.PWM_Flag is the output of loop comparator, is used as the clock of counter；When counter counts full 7
After the individual cycle, Ctrl signal high jumps, for adjusting the size of K values, limit excessively stream threshold value and are reduced to a lower value.Such as Fig. 3
Shown, after excessively stream is detected, OCP_Flag high jumps now keep LB always under the collective effect of LA and OCP_Flag signals
For height until excessively stream contact, during this period, though loop comparator output PWM_Flag arrive also can locked upper pipe, under holding
Pipe is opened, and reduces electric current on inductance.Now, LC is output as height by LB by the d type flip flop that a rising edge with enabling is triggered,
Enable counter effective.If as shown in figure 4, after continuous 7 cycles detect excessively stream, counter output high jump changed
Ductility limit threshold value is to a lower value Iocl_L.If subsequent cycle does not detect excessively stream within the minimum turn-off time, pass through
The adjustment of LB signals makes counter O reset, and Ctrl jumps low, and excessively stream threshold value limit is recovered to size Iocl_H before.
Fig. 5 is actual circuit structure figure of the invention, including first resistor R1, second resistance R2,3rd resistor R3,
Four resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8, the 9th resistance R9, the first PMOS
MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6,
Seven PMOS MP7, the 8th PMOS MP8, the 9th PMOS MP9, the tenth PMOS MP10, the 11st PMOS MP11, the tenth
Two PMOS MP12, the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS
Pipe MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 9th NMOS tube MN9, the tenth NMOS tube MN10,
11st NMOS tube MN11, the 11st NMOS tube MN12, the 13rd NMOS tube MN13, the 14th NMOS tube MN14, the 15th
NMOS tube MN15, a NLDMOS pipes NLDMOS1, the 2nd NLDMOS pipes NLDMOS2, the 3rd NLDMOS pipes NLDMOS3, the 4th
NLDMOS pipes NLDMOS4, the 5th NLDMOS pipes NLDMOS5, the first electric capacity C1, the second electric capacity C2, triode, operational amplifier,
Comparator, phase inverter and current source；
The positive input of operational amplifier connects external reference voltages, and its negative input is followed by by the 7th resistance R7
Ground, the grid of the first NMOS tube MN1 of its output termination；The drain electrode of the first NMOS tube MN1 connects power supply, and its source electrode passes through the 9th resistance
R9 is followed by the drain electrode of the 15th NMOS tube MN15；The grid of the 15th NMOS tube MN15 connects the first external control signal, its drain electrode
By being interconnected with its source electrode after the 8th resistance R8, its source electrode after the 7th resistance R7 by being grounded；
The source electrode of the 12nd PMOS MP12 connects the output end of current source, and its grid connects outside enable signal, goes drain electrode to connect
The drain electrode of the second NMOS tube MN2；The grid of the second NMOS tube MN2 connects the drain electrode of the 12nd PMOS MP12, and its source electrode connects the 3rd
The drain electrode of NMOS tube MN3；The grid of the 3rd NMOS tube MN3 connects the drain electrode of the 12nd PMOS MP12, and its source electrode meets the 4th NMOS
The drain electrode of pipe MN4；The grid of the 4th NMOS tube MN4 connects the source electrode of the 3rd NMOS tube MN3, its source ground；
The colelctor electrode of triode connects power supply, and its base stage connects the source electrode of the first NMOS tube MN1, and its emitter stage connects the 6th NMOS tube
The drain electrode of MN6；The grid of the 6th NMOS tube MN6 connects the source electrode of the second NMOS tube MN2, and its source electrode connects the leakage of the 5th NMOS tube MN5
Pole；The grid of the 5th NMOS tube MN5 connects the source electrode of the 3rd NMOS tube MN3, its source ground；
The source electrode of the first PMOS MP1 connects power supply, its grid and drain interconnection, and its drain electrode connects the leakage of the 8th NMOS tube MN8
Pole；The grid of the 8th NMOS tube MN8 connects the source electrode of the second NMOS tube MN2, and its source electrode connects the drain electrode of the 7th NMOS tube MN7；7th
The grid of NMOS tube MN7 connects the source electrode of the 3rd NMOS tube MN3, its source ground；
The source electrode of the second PMOS MP2 connects power supply, and its grid connects the grid of the first PMOS MP1, and its drain electrode connects the 3rd
The source electrode of the source electrode of PMOS MP3 and the 4th PMOS MP4；The grid of the 3rd PMOS MP3 connects the emitter stage of triode, its leakage
Pole connects the drain electrode of the 11st NMOS tube MN11；The grid of the 4th PMOS MP4 connects the source electrode of the 2nd NLDMOS pipes NLDMOS2, its
Drain electrode connects the drain electrode of the tenth NMOS tube MN10；
The source electrode of the 5th PMOS MP5 connects power supply, its grid and drain interconnection, its source electrode for missing the 6th PMOS MP6；
The grid and drain interconnection of the 6th PMOS MP6, it misses the drain electrode for meeting the 9th NMOS tube MN9；The grid of the 9th NMOS tube MN9
The source electrode of the 3rd NMOS tube MN3 is connect, its source ground；
The source electrode of the 7th PMOS MP7 connects power supply, and its grid connects the grid of the 9th PMOS MP9, and it is missed and connects the 8th
The source electrode of PMOS MP8；The grid of the 8th PMOS MP8 connects the drain electrode of the 6th PMOS MP6, and it is missed and connects the 7th PMOS
The drain electrode of the grid of MP7 and the 12nd NMOS tube MN12；The grid of the 12nd NMOS tube MN12 connects the source of the second NMOS tube MN2
Pole, its source electrode connects the drain electrode of the tenth NMOS tube MN10；The grid of the tenth NMOS tube MN10 connects the source electrode of the 3rd NMOS tube MN3, its
Source ground；
The source electrode of the 9th PMOS MP9 connects power supply, and its drain electrode connects the source electrode of the tenth PMOS MP10；Tenth PMOS MP10
Grid connect the drain electrode of the 6th PMOS MP6, its drain electrode connects the drain electrode of the 13rd NMOS tube MN13；13rd NMOS tube MN13's
Grid connects the source electrode of the second NMOS tube MN2, and its source electrode connects the drain electrode of the 11st NMOS tube MN11；The grid of the 11st NMOS tube MN11
Pole connects the source electrode of the 3rd NMOS tube MN3, its source ground；
The source electrode of the 11st PMOS MP11 connects power supply, and its grid connects the drain electrode of the tenth PMOS MP10, and its drain electrode is successively
The drain electrode of the 11st NMOS tube MN11 is followed by by the first electric capacity C1 and the 4th resistance R4；
The switching signal of the one termination BUCK converters of second resistance R2, its other end is followed by first by first resistor R1
The drain electrode and the drain electrode of the 2nd NLDMOS pipes NLDMOS2 of NLDMOS pipes NLDMOS1；The grid of the first NLDMOS pipes NLDMOS1 connects
Second external control signal, its source electrode connects the source electrode of the 4th NLDMOS pipes NLDMOS4；The grid of the 4th NLDMOS pipes NLDMOS4
The output end of phase inverter is connect, its drain electrode connects the source electrode of the 14th NMOS tube MN14；First NLDMOS pipe NLDMOS1 source electrodes and the 4th
The tie point of NLDMOS pipe NLDMOS4 source electrodes is connected with the drain electrode of the 11st PMOS MP11；2nd NLDMOS pipes NLDMOS2's
Grid connects the second external control signal, and its source electrode connects the source electrode of the 5th NLDMOS pipes NLDMOS5；5th NLDMOS pipes NLDMOS5
Grid connect the output end of phase inverter, its drain electrode passes through ground connection after 3rd resistor R3；2nd NLDMOS pipe NLDMOS2 source electrodes and
The tie point of five NLDMOS pipes NLDMOS5 is connected with the grid of the 4th PMOS MP4；
The drain electrode of the 3rd NLDMOS pipes NLDMOS3 connects the tie point of first resistor R1 and second resistance R2, and its grid connects
Two external control signals, its source electrode connects the drain electrode of the 14th NMOS tube MN14；The grid of the 14th NMOS tube MN14 connects phase inverter
Output end；The input of phase inverter terminates the second external control signal；
The positive input ground connection of comparator, its reverse input end connects the source electrode of the 3rd NLDMOS pipes NLDMOS3, its output
Hold the output end for over-current detection circuit
From the figure it may be seen that MN15 is opened after Ctrl signal high jumps, by resistance R8 short circuits, you can reduce divider resistance ratio
The size of low k, drops in example；Vbe1 is the difference of triode QN1 base stages and emitter voltage, for doing temperature-compensating.Resistance electricity
Hold R5, C2 to be used for filtering high-frequency noise.By middle two stage amplifer (OP1 in Fig. 1) by 2 points of A, B be clamped to K ×
Vref-Vbe1；Resistance capacitance R4, C1 are used for doing miller compensation, it is ensured that amplifier stability adjusts its bandwidth to maximum simultaneously.When upper
Pipe open when, close to Vin, now voltage ratio is larger for the current potential of SW points, thus in circuit using high pressure NLDMOS drain terminals it is pressure-resistant come
Protect the normal work of low-voltage circuit.In addition two-way selection has been done, during in order to prevent VSW larger, after the larger damage of Vcomp voltages
Level comparator, so in the upper pipe opening time, controlling NLDMOS4, NLDMOS5, MN4 to open by Choose signals, now has：
Vcomp=VA=K × Vref-Vbe1
Within the down tube opening time, NLDMOS1, NLDMOS2, NLDMOS3 are opened, then had：
Wherein NLDMOS4, NLDMOS5 are in order to same NLDMOS1, NLDMOS2 are matched using the effect of high-voltage tube；When upper
When pipe is opened, NLDMOS4, NLDMOS5 are opened, and are that amplifier OP1 sets up an appropriate quiescent point, it is ensured that when down tube is opened
Open, circuit can faster reach stable state after load switching.
Beneficial effects of the present invention are the current foldback circuit for devising a kind of detection of Cycle by Cycle, when the week for 7 weeks phase still
During generation excessively stream, the threshold value of ductility limit can be reduced, circuit overheat in the case of preventing electric current excessive plays further guarantor to circuit
Shield is acted on.Additionally, conducting resistance of the circuit also to lower power tube positive temperature coefficient is compensated, make sampling more accurate.
Claims (1)
1. a kind of over-current detection circuit for BUCK converters, including first resistor R1, second resistance R2,3rd resistor R3,
4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8, the 9th resistance R9, the first PMOS
MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6,
Seven PMOS MP7, the 8th PMOS MP8, the 9th PMOS MP9, the tenth PMOS MP10, the 11st PMOS MP11, the tenth
Two PMOS MP12, the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS
Pipe MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 9th NMOS tube MN9, the tenth NMOS tube MN10,
11st NMOS tube MN11, the 11st NMOS tube MN12, the 13rd NMOS tube MN13, the 14th NMOS tube MN14, the 15th
NMOS tube MN15, a NLDMOS pipes NLDMOS1, the 2nd NLDMOS pipes NLDMOS2, the 3rd NLDMOS pipes NLDMOS3, the 4th
NLDMOS pipes NLDMOS4, the 5th NLDMOS pipes NLDMOS5, the first electric capacity C1, the second electric capacity C2, triode, operational amplifier,
Comparator, phase inverter and current source；
The positive input of operational amplifier connects external reference voltages, its negative input by after the 7th resistance R7 be grounded, its
The grid of the first NMOS tube MN1 of output termination；The drain electrode of the first NMOS tube MN1 connects power supply, and its source electrode is by after the 9th resistance R9
Connect the drain electrode of the 15th NMOS tube MN15；The grid of the 15th NMOS tube MN15 connects the first external control signal, and its drain electrode passes through
Interconnected with its source electrode after 8th resistance R8, its source electrode after the 7th resistance R7 by being grounded；
The source electrode of the 12nd PMOS MP12 connects the output end of current source, and its grid connects outside enable signal, and its drain electrode connects second
The drain electrode of NMOS tube MN2；The grid of the second NMOS tube MN2 connects the drain electrode of the 12nd PMOS MP12, and its source electrode meets the 3rd NMOS
The drain electrode of pipe MN3；The grid of the 3rd NMOS tube MN3 connects the drain electrode of the 12nd PMOS MP12, and its source electrode meets the 4th NMOS tube MN4
Drain electrode；The grid of the 4th NMOS tube MN4 connects the source electrode of the 3rd NMOS tube MN3, its source ground；
The colelctor electrode of triode connects power supply, and its base stage connects the source electrode of the first NMOS tube MN1, and its emitter stage meets the 6th NMOS tube MN6
Drain electrode；The grid of the 6th NMOS tube MN6 connects the source electrode of the second NMOS tube MN2, and its source electrode connects the drain electrode of the 5th NMOS tube MN5；
The grid of the 5th NMOS tube MN5 connects the source electrode of the 3rd NMOS tube MN3, its source ground；
The source electrode of the first PMOS MP1 connects power supply, its grid and drain interconnection, and its drain electrode connects the drain electrode of the 8th NMOS tube MN8；The
The grid of eight NMOS tube MN8 connects the source electrode of the second NMOS tube MN2, and its source electrode connects the drain electrode of the 7th NMOS tube MN7；7th NMOS tube
The grid of MN7 connects the source electrode of the 3rd NMOS tube MN3, its source ground；
The source electrode of the second PMOS MP2 connects power supply, and its grid connects the grid of the first PMOS MP1, and its drain electrode connects the 3rd PMOS
The source electrode of the source electrode of MP3 and the 4th PMOS MP4；The grid of the 3rd PMOS MP3 connects the emitter stage of triode, and its drain electrode connects the
The drain electrode of 11 NMOS tube MN11；The grid of the 4th PMOS MP4 connects the source electrode of the 2nd NLDMOS pipes NLDMOS2, and its drain electrode connects
The drain electrode of the tenth NMOS tube MN10；
The source electrode of the 5th PMOS MP5 connects power supply, its grid and drain interconnection, its source electrode for missing the 6th PMOS MP6；6th
The grid and drain interconnection of PMOS MP6, it misses the drain electrode for meeting the 9th NMOS tube MN9；The grid of the 9th NMOS tube MN9 connects
The source electrode of three NMOS tube MN3, its source ground；
The source electrode of the 7th PMOS MP7 connects power supply, and its grid connects the grid of the 9th PMOS MP9, and it is missed and connects the 8th PMOS
The source electrode of MP8；The grid of the 8th PMOS MP8 connects the drain electrode of the 6th PMOS MP6, and it misses the grid for meeting the 7th PMOS MP7
Pole and the drain electrode of the 12nd NMOS tube MN12；The grid of the 12nd NMOS tube MN12 connects the source electrode of the second NMOS tube MN2, its source electrode
Connect the drain electrode of the tenth NMOS tube MN10；The grid of the tenth NMOS tube MN10 connects the source electrode of the 3rd NMOS tube MN3, its source ground；
The source electrode of the 9th PMOS MP9 connects power supply, and its drain electrode connects the source electrode of the tenth PMOS MP10；The grid of the tenth PMOS MP10
Pole connects the drain electrode of the 6th PMOS MP6, and its drain electrode connects the drain electrode of the 13rd NMOS tube MN13；The grid of the 13rd NMOS tube MN13
The source electrode of the second NMOS tube MN2 is connect, its source electrode connects the drain electrode of the 11st NMOS tube MN11；The grid of the 11st NMOS tube MN11 connects
The source electrode of the 3rd NMOS tube MN3, its source ground；
The source electrode of the 11st PMOS MP11 connects power supply, and its grid connects the drain electrode of the tenth PMOS MP10, and its drain electrode is passed sequentially through
First electric capacity C1 and the 4th resistance R4 are followed by the drain electrode of the 11st NMOS tube MN11；
The voltage signal of the one termination BUCK converter switches nodes of second resistance R2, its other end is followed by by first resistor R1
The drain electrode and the drain electrode of the 2nd NLDMOS pipes NLDMOS2 of the first NLDMOS pipes NLDMOS1；The grid of the first NLDMOS pipes NLDMOS1
Pole connects the second external control signal, and its source electrode connects the source electrode of the 4th NLDMOS pipes NLDMOS4；4th NLDMOS pipes NLDMOS4's
Grid connects the output end of phase inverter, and its drain electrode connects the source electrode of the 14th NMOS tube MN14；First NLDMOS pipe NLDMOS1 source electrodes with
The tie point of the 4th NLDMOS pipe NLDMOS4 source electrodes is connected with the drain electrode of the 11st PMOS MP11；2nd NLDMOS is managed
The grid of NLDMOS2 connects the second external control signal, and its source electrode connects the source electrode of the 5th NLDMOS pipes NLDMOS5；5th NLDMOS
The grid of pipe NLDMOS5 connects the output end of phase inverter, and its drain electrode after 3rd resistor R3 by being grounded；2nd NLDMOS is managed
NLDMOS2 source electrodes are connected with the tie point of the 5th NLDMOS pipes NLDMOS5 with the grid of the 4th PMOS MP4；
The drain electrode of the 3rd NLDMOS pipes NLDMOS3 connects the tie point of first resistor R1 and second resistance R2, and its grid is connect outside second
Portion's control signal, its source electrode connects the drain electrode of the 14th NMOS tube MN14；The grid of the 14th NMOS tube MN14 connects the defeated of phase inverter
Go out end；The input of phase inverter terminates the second external control signal；
The positive input ground connection of comparator, its reverse input end connects the source electrode of the 3rd NLDMOS pipes NLDMOS3, and its output end is
The output end of over-current detection circuit.
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| CN201510575228.8A CN105162314B (en) | 2015-09-10 | 2015-09-10 | A kind of over-current detection circuit for BUCK converters |
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| CN201510575228.8A CN105162314B (en) | 2015-09-10 | 2015-09-10 | A kind of over-current detection circuit for BUCK converters |
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| CN105162314B true CN105162314B (en) | 2017-06-30 |
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| CN105871189B (en) * | 2016-05-24 | 2018-06-29 | 电子科技大学 | A kind of over-current detection circuit |
| CN109541285B (en) * | 2018-12-26 | 2020-12-08 | 东莞市长工微电子有限公司 | Buckboost circuit output current detection method and detection circuit thereof |
| CN111799989B (en) * | 2020-07-15 | 2021-06-08 | 电子科技大学 | Overcurrent detection circuit applied to current mode COT control Buck converter |
| CN112531635B (en) * | 2020-11-11 | 2023-05-26 | 成都矽芯科技有限公司 | Overcurrent protection circuit capable of adjusting valley current |
| CN112730959B (en) * | 2020-12-25 | 2024-04-02 | 意美旭智芯能源科技有限公司 | Overcurrent detection circuit of buck conversion circuit controller |
| CN114759647B (en) * | 2022-05-27 | 2023-03-24 | 电子科技大学 | Flying capacitor pre-charging circuit |
| CN114725892B (en) * | 2022-06-09 | 2022-11-01 | 深圳市泰德半导体有限公司 | Cycle-by-cycle current limiting circuit and power management chip |
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| JP5114818B2 (en) * | 2001-08-13 | 2013-01-09 | ヤマハ株式会社 | Current detection method, current detection circuit and overcurrent protection circuit |
| CN201444572U (en) * | 2009-04-23 | 2010-04-28 | 青岛海信电器股份有限公司 | Over-current protection circuit |
| CN102208802B (en) * | 2010-06-29 | 2013-11-13 | 上海山景集成电路股份有限公司 | Power switching tube overcurrent detection and overcurrent protection circuit |
| CN201937235U (en) * | 2010-12-17 | 2011-08-17 | 西安奇维测控科技有限公司 | Overcurrent protection circuit |
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