CN105161501B - Array base palte and preparation method thereof, display panel and display device - Google Patents
Array base palte and preparation method thereof, display panel and display device Download PDFInfo
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- CN105161501B CN105161501B CN201510512677.8A CN201510512677A CN105161501B CN 105161501 B CN105161501 B CN 105161501B CN 201510512677 A CN201510512677 A CN 201510512677A CN 105161501 B CN105161501 B CN 105161501B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims description 17
- 239000003086 colorant Substances 0.000 claims description 3
- 241001269238 Data Species 0.000 claims 1
- 230000005540 biological transmission Effects 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000011982 device technology Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003724 hair brightness Effects 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Manufacturing & Machinery (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention provides a kind of array base palte and preparation method thereof, display panel and display device, the array base palte includes：The grid line figure and data line graph of substrate and formation on the substrate；The grid line figure and the data line graph limit multiple pixels；The two adjacent data wires of row form a data line group, and two column data lines in each data line group are linked into same data voltage input；Also include the overlap joint line graph for forming viewing area in substrate, the overlap joint line graph includes conductive overlap joint line, and two column data lines in same data line group are connected in viewing area by least one overlap joint line.Array base palte provided by the invention can reduce the transmission delay of data voltage signal on the data line compared with array base palte of the prior art.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of array base palte and preparation method thereof, display panel and aobvious
Showing device.
Background technology
With the development of display device manufacturing technology, liquid crystal display device technology is quickly grown, and oneself has been substituted traditional
Crt display unit and as following flat-panel monitor main flow.In LCD Technology field, tft liquid crystal
Display TFT-LCD (Thin Film Transistor Liquid Crystal Display) is collected with its large scale, height
Into, powerful, technique flexibly, the advantage such as low cost and be widely used in television set, computer, in fields such as machines.
TFT-LCD uses line-column matrix drive pattern, such as works as the product resolution ratio 320x240 of display device, then needs
320, Gate IC lines, data wire then need 240x3 roots (RGB), to realize the control to each pixel.Specifically,
In each frame, the TFT that gate driving circuit control controls each pixel to be connected successively is opened, and data drive circuit passes through institute
Corresponding data voltage signal is written in each pixel by the data wire of connection, so that each pixel has corresponding hair
Brightness.
Due to the limitation of width, data wire typically has higher resistance, can so cause data voltage signal in data
Transmission delay on line is higher, influences luminescence display.
The content of the invention
It is an object of the invention to reduce the transmission delay of data voltage signal on the data line.
In a first aspect, the invention provides a kind of array base palte, including substrate and form grid line on the substrate
Figure and data line graph；The grid line figure and the data line graph limit multiple pixels；The adjacent data wire structure of two row
Into a data line group, two column data lines in each data line group are linked into same data voltage input；Also include shape
Into the overlap joint line graph of the viewing area in substrate, the overlap joint line graph includes conductive overlap joint line, same data line group
In two column data lines viewing area by least one overlap joint line be connected.
Further, the overlap joint line graph is formed with the data line graph by same technique.
Further, the overlap joint line in the overlap joint line graph is formed in non-open areas.
Further, two row grid lines are connected per one-row pixels, the first grid line is located at the top of the row pixel, the second grid line position
In the lower section of the row pixel；Overlap joint line in the overlap joint line graph is located at the second gate of lastrow pixel in adjacent two row pixel
Between line and the first grid line of next line pixel.
Further, the pixel that the grid line figure and the data line graph are limited is used to show three kinds of colors, uses
In showing the pixel of the first color, the pixel for showing second color and for showing that the pixel of the third color is in
Delta is arranged.
Second aspect, the invention provides a kind of preparation method of array base palte, including：
Grid line figure is being formed in substrate and the step of data line graph, grid line figure formed in it and formed
Data line graph limits multiple pixels；The two adjacent data wires of row form a data line group, and two in each data line group
Column data line is linked into same data voltage input；
Also include the viewing area in substrate and form overlap joint line graph, the overlap joint line graph formed includes a plurality of conduction
Overlap joint line, two column data lines in same data line group are connected in viewing area by least one overlap joint line.
Further, the overlap joint line graph that formed in substrate includes：
The overlap joint line graph is formed in the same technique for forming the data line graph.
Further, the overlap joint line graph that formed in substrate includes：
Line is overlapped in each bar that non-open areas is formed in the overlap joint line graph.
Further, in the grid line figure formed, two row grid lines are connected per one-row pixels, the first grid line is located at the row
The top of pixel, the second grid line are located at the lower section of the row pixel；
The overlap joint line graph that formed in substrate includes：In adjacent two row pixel the second grid line of lastrow pixel with
The overlap joint line formed between first grid line of next line pixel in the overlap joint line graph.
The third aspect, the invention provides a kind of display panel, including the array base palte described in any of the above-described.
Fourth aspect, the invention provides a kind of display device, including display panel described above.
In array base palte provided by the invention, the viewing area in substrate is formed with overlap joint line graph, the overlap joint line
Figure includes conductive overlap joint line, and the first data wire and the second data wire in same data line group pass through at least in viewing area
One overlap joint line is connected.Array base palte provided by the invention can reduce data electricity compared with array base palte of the prior art
Press the transmission delay of signal on the data line.
Brief description of the drawings
Fig. 1 is a kind of schematic diagram of the array base palte of array base palte with double grid technology of the prior art；
Fig. 2, Fig. 3 and Fig. 4 are the structural representation of array base palte provided in an embodiment of the present invention；
Fig. 5 is a kind of equivalent resistance figure of the data wire of array base palte of the prior art；
Fig. 6 is the equivalent resistance figure of the data wire of array base palte provided in an embodiment of the present invention.
Embodiment
With reference to the accompanying drawings and examples, the embodiment of the present invention is further described.Following examples are only
For clearly illustrating technical scheme, and can not be limited the scope of the invention with this.
In general, data drive circuit wanted for gate driving circuit it is expensive a lot.So carry in the prior art
Double grid technology (dual gate) is gone out, number is reduced with increase grid line number in the case where guarantee realizes that same pixel count is shown
According to the number of drive circuit, to reduce product cost.Fig. 1 is a kind of existing array base palte using double grid technology, therein one
Any one-row pixels of row pixel, such as the first row pixel R1 connections two row grid line G1 and G2, wherein a line grid line G1 control odd numbers
The pixel of row, the pixel of another row grid line G2 controls even column, the data wire of adjacent two row are connected to same data voltage input,
For example data wire D1 and D2 are connected to same data voltage input I1, the quantity of so required data voltage input is reduced
Half, the number of the required data drive circuit used can be greatly reduced, so as to reduce the cost of corresponding display device.
Array base palte provided by the invention is also the similar array base palte with Fig. 1, i.e., the institute in the substrate of the array base palte
The data wires of adjacent two row form a data line group in the data line graph of formation, two column data lines in same data line group
It is connected to same data voltage input.Unlike, array base palte provided by the invention also includes forming the display in substrate
The overlap joint line graph in region, two column data lines in same data line group are connected in viewing area by overlapping line, so suitable
In by two column data lines by overlap line parallel to together, can so reduce be connected to this two column data line and positioned at overlap joint line
The pixel of lower section (assuming that data voltage input is disposed over) is to the resistance between data voltage input, so as to reduce number
According to the transmission delay of voltage signal to the pixel.
On the other hand, present invention also offers a kind of preparation method of array base palte, this method can be used for making this hair
Bright provided array base palte, this method include：
Grid line figure is being formed in substrate and the step of data line graph, grid line figure formed in it and formed
Data line graph limits multiple pixels；The two adjacent data wires of row form a data line group, and two in each data line group
Column data line is linked into same data voltage input；Also include the viewing area in substrate and form overlap joint line graph, institute's shape
Into overlap joint line graph include a plurality of conductive overlap joint line, the first data wire and the second data wire in same data line group are aobvious
Show that region is connected by least one overlap joint line.
In the specific implementation, above-mentioned array base palte may show as a variety of different concrete structures.Corresponding making side
Method may also be different, illustrates below in conjunction with the accompanying drawings.
Referring to Fig. 2, Fig. 3 and Fig. 4, the structural representation of the array base palte provided for one embodiment of the invention, the array base
Plate includes：Substrate (not shown), the grid line figure and data line graph formed in substrate, the grid line figure include multirow
Grid line G1-G8, data wire figure include multiple columns of data lines D1-D6, and grid line figure and data line graph define the picture of 4 rows 6 row
(pixel connects the adjacent grid line of two rows and two and arranges a rectangle or the approximate rectangular area that adjacent data wire is limited element
Domain), each pixel color has tri- kinds of R, G, B.Wherein, two row grid lines are connected per one-row pixels, a line grid line is located at the row pixel
Top, connect odd column pixel therein, another row grid line is located at the lower section of the row pixel, connects even column picture therein
Element；For example it is connected to the grid line above the row pixel for the first row pixel R1, S1, S3 and S5 row pixel therein
G1, S2, S4 and S6 row pixel therein are connected to the grid line G2 below the row pixel；Two adjacent column data lines are formed
One data line group, two column data lines in a data line group connect same data voltage input, each column data line connection
Pixel on the left of close to it；For example for data wire D1, the pixel column S1 on the left of it is connected, data wire D2 is then connected on the left of it
Pixel column S2, data wire D1 and D2 are connected to same data voltage input I1；
In addition, referring to Fig. 2, Fig. 3 and Fig. 4, the array base palte also includes the overlap joint line of the viewing area formed in substrate
Figure, the overlap joint line graph include the conductive overlap joint line L shown in multiple figures；Two column data lines in same data line group exist
Viewing area is connected by a plurality of overlap joint line L.Each bar overlap joint line can form the connection lastrow pixel in adjacent two row pixel
And between the grid line for being located at the grid line below lastrow pixel and connection next line pixel and being located above next line pixel, such as
In figs. 2,3 and 4, show that the overlap joint line L of label is connected to connection R1 rows pixel and the grid line below R1 row pixels
Between G2 and connection R2 rows pixel and the grid line G3 being located above R2 row pixels.In figs. 2,3 and 4, refer to away from data
The side of voltage input end, and top then refers to close to the side of data voltage input.
Array base palte provided in an embodiment of the present invention, two column data lines of same data voltage input will be connected to aobvious
Show that region is connected by a plurality of overlap joint line, be so parallel to together, can be reduced positioned at overlap joint line equivalent to by two column data lines
The pixel of lower section to the resistance between data voltage input, prolong by the transmission that data voltage signal to corresponding pixel is greatly reduced
When.
Referring to Fig. 5, for the equivalent circuit diagram of data wire in array base palte of the prior art, it is assumed that the array base palte has
320*160 pixel, and be R corresponding to the resistance of the one piece of data line of a pixel, then for X pixel P-X, it arrives number
Enclosed according to voltage input end In resistance and beat up X*R ∥ (2x320-X) R, it is assumed that above-mentioned X is 160, then pixel P-X to data voltage
Input In resistance is 160*R ∥ (2x320-160) R=120R.It is number in array base palte provided by the invention referring to Fig. 6
According to the equivalent circuit diagram of line, the same hypothesis array base palte has 320*160 pixel, and corresponding to a hop count of a pixel
Resistance according to line is R, then for X pixel P-X, it arrives data voltage input In resistance X*R/2, when X is 160,
Pixel P-X to data voltage input In resistance is 80R, it is seen that pixel can be greatly reduced in array base palte provided by the invention
To the resistance of data voltage input, the transmission delay of data voltage signal on the data line is reduced.
Also, in the embodiment of the present invention, overlap joint line is formed between two row grid lines, so on the one hand, due to being arranged on
Non-open areas, the aperture opening ratio of corresponding pixel is not interfered with, on the other hand, because overlap joint line is formed between two row grid lines,
It can so avoid overlapping and electric capacity is formed between line and grid line, lower thus biography of the caused voltage signal in grid line and data wire
Defeated signal delay.
It is understandable to be, in the specific implementation, the grid line above one-row pixels is connected the idol in the pixel column
Ordered series of numbers pixel, the grid line below pixel connect the odd column pixel in the pixel column, can't influence the implementation of the present invention,
Corresponding technical scheme should be also fallen into by protection scope of the present invention.
Understandable to be, only in order to reach the purpose for the aperture opening ratio for not influenceing pixel, above-mentioned overlap joint is linear
Into in non-open areas, without being formed between two row grid lines.And reduce data voltage letter if only in order to reach
For the purpose of transmission delay number on the data line, above-mentioned overlap joint line need not be simultaneously formed in non-open areas.These sides
Case also should fall into protection scope of the present invention.
In the specific implementation, above-mentioned overlap joint line graph can be formed with data line graph in same technique, so may be used
To reduce manufacture difficulty.Certainly in actual applications, the overlap joint line graph made by other means also can solve the problem that the present invention
The basic problem proposed, corresponding technical scheme should also fall into protection scope of the present invention.
In the specific implementation, the color of above-mentioned pixel is not limited to three kinds, as long as forming overlap joint line in viewing area
Figure, and two column data lines for making to be connected to same data voltage input are connected by overlapping line, corresponding technical scheme is equal
General object of the present invention can be reached, also should fall into protection scope of the present invention.
In the specific implementation, can be arranged referring to Fig. 2, above-mentioned each colored pixels R, G, B according to stripelike manner, i.e., it is every
The pixel of one row is same color.Or can also according to mode as shown in Figure 3, the pixel of adjacent three different colours,
Red pixel R, blue pixel B and green pixel G are distributed in positive triangle, i.e., are arranged in delta shapes.
The array base palte that Fig. 4 is illustrated that in Fig. 3 is the liquid crystal battle array of aligned twisted (Twisted Nematic, TN) pattern
The schematic diagram of which part structure during row substrate.Understandable to be, above-mentioned liquid crystal array substrate also may be used in actual applications
Think the liquid crystal array substrate of Senior super dimension field switch technology (ADvanced Super Dimension Switch, ADS) pattern
Or the liquid crystal array substrate of other patterns.Or in actual applications, above-mentioned array base palte can not also be liquid crystal array
Substrate, and it is other kinds of array base palte, corresponding technical scheme should fall into protection scope of the present invention.
It can be specifically included for the preparation method of the array base palte described in Fig. 2, Fig. 3 and Fig. 4：
Gate patterns and data line graph are formed in substrate by Patternized technique, and are forming the same of data line graph
In one procedure, overlap joint line graph is formed in non-open areas.Specifically, lastrow pixel is connected in adjacent two row pixel
And formed between the grid line for being located at the grid line below lastrow pixel and connection next line pixel and being located above next line pixel
Overlap each bar overlap joint line in line graph.
Grid line figure is formed by Patternized technique and data line graph and overlap joint line chart are formed by Patternized technique
The concrete technology of shape may be referred to Patternized technique of the prior art, and the present invention no longer describes in detail herein.
The third aspect, present invention also offers a kind of display panel, including above-mentioned array base palte.
Fourth aspect, present invention also offers a kind of display device, including display panel described above.
Here display device can be：Electronic Paper, mobile phone, tablet personal computer, television set, display, notebook computer, number
Any product or part with display function such as code-phase frame, navigator.
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, some improvements and modifications can also be made, these improvements and modifications
Also it should be regarded as protection scope of the present invention.
Claims (11)
1. a kind of array base palte, including substrate and form grid line figure and data line graph on the substrate；The grid
Line graph and the data line graph limit multiple pixels；The adjacent data wire of two row forms a data line group, each number
Same data voltage input is linked into according to two column data lines in line group；Characterized in that, also include being formed in substrate
The overlap joint line graph of viewing area, the overlap joint line graph include conductive overlap joint line, two column datas in same data line group
Line is connected in viewing area by least one overlap joint line, and picture is provided between two column data lines in each group of data wire
Element.
2. array base palte as claimed in claim 1, it is characterised in that the overlap joint line graph passes through same with the data line graph
Technique is formed.
3. array base palte as claimed in claim 1 or 2, it is characterised in that the overlap joint line in the overlap joint line graph is formed
Non-open areas.
4. array base palte as claimed in claim 3, it is characterised in that two row grid lines, the first grid line position are connected per one-row pixels
In the top of the row pixel, the second grid line is located at the lower section of the row pixel；Overlap joint line in the overlap joint line graph is positioned at adjacent
In two row pixels between the second grid line of lastrow pixel and the first grid line of next line pixel.
5. array base palte as claimed in claim 1, it is characterised in that the grid line figure and the data line graph are limited
Each pixel be used for show three kinds of colors, for show the first color pixel, for show second of color pixel
With the pixel for showing the third color in delta arrangements.
6. a kind of preparation method of array base palte, including：
Grid line figure is being formed in substrate and the step of data line graph, grid line figure formed in it and the data formed
Line graph limits multiple pixels；The two adjacent data wires of row form a data line group, two columns in each data line group
Same data voltage input is linked into according to line；Characterized in that,
Also include the viewing area in substrate and form overlap joint line graph, the overlap joint line graph formed includes a plurality of conductive take
Wiring, two column data lines in same data line group are connected in viewing area by least one overlap joint line, each group of number
According to being provided with pixel between two column data lines in line.
7. method as claimed in claim 6, it is characterised in that the overlap joint line graph that formed in substrate includes：
The overlap joint line graph is formed in the same technique for forming the data line graph.
8. method as claimed in claims 6 or 7, it is characterised in that the overlap joint line graph that formed in substrate includes：
Line is overlapped in each bar that non-open areas is formed in the overlap joint line graph.
9. method as claimed in claim 6, it is characterised in that in the grid line figure formed, the connection two per one-row pixels
Row grid line, the first grid line are located on the top of the row pixel, and the second grid line is located at the lower section of the row pixel；
The overlap joint line graph that formed in substrate includes：In adjacent two row pixel the second grid line of lastrow pixel with it is next
The overlap joint line formed between first grid line of row pixel in the overlap joint line graph.
10. a kind of display panel, it is characterised in that including the array base palte as described in claim any one of 1-5.
11. a kind of display device, it is characterised in that including display panel as claimed in claim 10.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510512677.8A CN105161501B (en) | 2015-08-19 | 2015-08-19 | Array base palte and preparation method thereof, display panel and display device |
| PCT/CN2015/097491 WO2017028415A1 (en) | 2015-08-19 | 2015-12-15 | Array substrate and manufacturing method thereof, and corresponding display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510512677.8A CN105161501B (en) | 2015-08-19 | 2015-08-19 | Array base palte and preparation method thereof, display panel and display device |
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| Publication Number | Publication Date |
|---|---|
| CN105161501A CN105161501A (en) | 2015-12-16 |
| CN105161501B true CN105161501B (en) | 2018-03-30 |
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| CN201510512677.8A Active CN105161501B (en) | 2015-08-19 | 2015-08-19 | Array base palte and preparation method thereof, display panel and display device |
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| WO (1) | WO2017028415A1 (en) |
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| WO2018120021A1 (en) * | 2016-12-30 | 2018-07-05 | 陶霖密 | Display panel, display apparatus and pixel rendering method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101299124A (en) * | 2008-06-25 | 2008-11-05 | 昆山龙腾光电有限公司 | Array substrates of LCD devices |
| CN102856320A (en) * | 2012-08-13 | 2013-01-02 | 京东方科技集团股份有限公司 | TFT (thin film transistor) array substrate and display |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI384308B (en) * | 2009-07-01 | 2013-02-01 | Au Optronics Corp | Display apparatus and display driving method |
| CN102004361B (en) * | 2010-10-18 | 2013-03-06 | 深超光电（深圳）有限公司 | Pixel array |
| CN103744239A (en) * | 2013-12-26 | 2014-04-23 | 深圳市华星光电技术有限公司 | Embedded type touch control array substrate structure |
-
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- 2015-08-19 CN CN201510512677.8A patent/CN105161501B/en active Active
- 2015-12-15 WO PCT/CN2015/097491 patent/WO2017028415A1/en active Application Filing
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101299124A (en) * | 2008-06-25 | 2008-11-05 | 昆山龙腾光电有限公司 | Array substrates of LCD devices |
| CN102856320A (en) * | 2012-08-13 | 2013-01-02 | 京东方科技集团股份有限公司 | TFT (thin film transistor) array substrate and display |
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| Publication number | Publication date |
|---|---|
| CN105161501A (en) | 2015-12-16 |
| WO2017028415A1 (en) | 2017-02-23 |
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