CN105144084B - 提高处理器中返回分支指令的执行速度的方法 - Google Patents

提高处理器中返回分支指令的执行速度的方法 Download PDF

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Publication number
CN105144084B
CN105144084B CN201480013935.1A CN201480013935A CN105144084B CN 105144084 B CN105144084 B CN 105144084B CN 201480013935 A CN201480013935 A CN 201480013935A CN 105144084 B CN105144084 B CN 105144084B
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China
Prior art keywords
instruction
processor
counter
branch instruction
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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CN201480013935.1A
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English (en)
Chinese (zh)
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CN105144084A (zh
Inventor
罗德尼·韦恩·史密斯
杰弗里·M·斯科特米勒
迈克尔·斯科特·麦克勒瓦伊内
布莱恩·迈克尔·斯坦普尔
梅林达·J·布朗
达朗·尤金·施特雷特
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Qualcomm Inc
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Qualcomm Inc
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Publication of CN105144084B publication Critical patent/CN105144084B/zh
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
CN201480013935.1A 2013-03-15 2014-03-14 提高处理器中返回分支指令的执行速度的方法 Expired - Fee Related CN105144084B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/833,844 US9411590B2 (en) 2013-03-15 2013-03-15 Method to improve speed of executing return branch instructions in a processor
US13/833,844 2013-03-15
PCT/US2014/029778 WO2014145101A1 (en) 2013-03-15 2014-03-14 Method to improve speed of executing return branch instructions in a processor

Publications (2)

Publication Number Publication Date
CN105144084A CN105144084A (zh) 2015-12-09
CN105144084B true CN105144084B (zh) 2018-03-20

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CN201480013935.1A Expired - Fee Related CN105144084B (zh) 2013-03-15 2014-03-14 提高处理器中返回分支指令的执行速度的方法

Country Status (6)

Country Link
US (1) US9411590B2 (enExample)
EP (1) EP2972789B8 (enExample)
JP (1) JP6257745B2 (enExample)
KR (1) KR20150130513A (enExample)
CN (1) CN105144084B (enExample)
WO (1) WO2014145101A1 (enExample)

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US9934831B2 (en) * 2014-04-07 2018-04-03 Micron Technology, Inc. Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters
US10120688B2 (en) * 2016-11-15 2018-11-06 Andes Technology Corporation Data processing system and method for executing block call and block return instructions
US20180203703A1 (en) * 2017-01-13 2018-07-19 Optimum Semiconductor Technologies, Inc. Implementation of register renaming, call-return prediction and prefetch
GB2571996B (en) * 2018-03-16 2020-09-09 Advanced Risc Mach Ltd Branch target variant of branch-with-link instruction
US10831884B1 (en) * 2019-09-16 2020-11-10 International Business Machines Corporation Nested function pointer calls
CN114647445A (zh) * 2020-12-18 2022-06-21 意法半导体(格勒诺布尔2)公司 在处理器上的逆向工程检测方法和对应集成电路
US20240220267A1 (en) * 2022-12-30 2024-07-04 Akeana, Inc. Return address stack with branch mispredict recovery

Citations (3)

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US5623614A (en) * 1993-09-17 1997-04-22 Advanced Micro Devices, Inc. Branch prediction cache with multiple entries for returns having multiple callers
US6170054B1 (en) * 1998-11-16 2001-01-02 Intel Corporation Method and apparatus for predicting target addresses for return from subroutine instructions utilizing a return address cache
CN101281459A (zh) * 2007-04-03 2008-10-08 Arm有限公司 受保护的功能调用

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US4164037A (en) * 1976-10-27 1979-08-07 Texas Instruments Incorporated Electronic calculator or microprocessor system having combined data and flag bit storage system
US4112495A (en) * 1977-02-09 1978-09-05 Texas Instruments Incorporated Electronic calculator or microprocessor having a selectively loadable instruction register
US5193205A (en) * 1988-03-01 1993-03-09 Mitsubishi Denki Kabushiki Kaisha Pipeline processor, with return address stack storing only pre-return processed address for judging validity and correction of unprocessed address
US5179673A (en) * 1989-12-18 1993-01-12 Digital Equipment Corporation Subroutine return prediction mechanism using ring buffer and comparing predicated address with actual address to validate or flush the pipeline
US6157999A (en) * 1997-06-03 2000-12-05 Motorola Inc. Data processing system having a synchronizing link stack and method thereof
US6092188A (en) 1997-12-23 2000-07-18 Intel Corporation Processor and instruction set with predict instructions
SE513431C2 (sv) * 1999-01-11 2000-09-11 Ericsson Telefon Ab L M Buffert för icke-rapporterade hopp
US6848044B2 (en) * 2001-03-08 2005-01-25 International Business Machines Corporation Circuits and methods for recovering link stack data upon branch instruction mis-speculation
US7024537B2 (en) * 2003-01-21 2006-04-04 Advanced Micro Devices, Inc. Data speculation based on addressing patterns identifying dual-purpose register
US20080040576A1 (en) 2006-08-09 2008-02-14 Brian Michael Stempel Associate Cached Branch Information with the Last Granularity of Branch instruction in Variable Length instruction Set
US7478228B2 (en) * 2006-08-31 2009-01-13 Qualcomm Incorporated Apparatus for generating return address predictions for implicit and explicit subroutine calls
US7617387B2 (en) 2006-09-27 2009-11-10 Qualcomm Incorporated Methods and system for resolving simultaneous predicted branch instructions
US8438372B2 (en) * 2007-10-05 2013-05-07 Qualcomm Incorporated Link stack repair of erroneous speculative update
US7971044B2 (en) * 2007-10-05 2011-06-28 Qualcomm Incorporated Link stack repair of erroneous speculative update
US8341383B2 (en) * 2007-11-02 2012-12-25 Qualcomm Incorporated Method and a system for accelerating procedure return sequences
US10042776B2 (en) 2012-11-20 2018-08-07 Arm Limited Prefetching based upon return addresses

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5623614A (en) * 1993-09-17 1997-04-22 Advanced Micro Devices, Inc. Branch prediction cache with multiple entries for returns having multiple callers
US6170054B1 (en) * 1998-11-16 2001-01-02 Intel Corporation Method and apparatus for predicting target addresses for return from subroutine instructions utilizing a return address cache
CN101281459A (zh) * 2007-04-03 2008-10-08 Arm有限公司 受保护的功能调用

Also Published As

Publication number Publication date
US20140281394A1 (en) 2014-09-18
EP2972789B8 (en) 2020-03-04
CN105144084A (zh) 2015-12-09
EP2972789B1 (en) 2019-11-20
JP2016517092A (ja) 2016-06-09
KR20150130513A (ko) 2015-11-23
US9411590B2 (en) 2016-08-09
WO2014145101A1 (en) 2014-09-18
EP2972789A1 (en) 2016-01-20
JP6257745B2 (ja) 2018-01-10

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