CN105140305B - High-pressure flat plate electric capacity and demagnetization sample circuit - Google Patents
High-pressure flat plate electric capacity and demagnetization sample circuit Download PDFInfo
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- CN105140305B CN105140305B CN201510565641.6A CN201510565641A CN105140305B CN 105140305 B CN105140305 B CN 105140305B CN 201510565641 A CN201510565641 A CN 201510565641A CN 105140305 B CN105140305 B CN 105140305B
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- 230000005347 demagnetization Effects 0.000 title claims abstract description 113
- 239000002184 metal Substances 0.000 claims abstract description 54
- 229910052751 metal Inorganic materials 0.000 claims abstract description 54
- 239000004065 semiconductor Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 239000002210 silicon-based material Substances 0.000 claims description 7
- 238000005070 sampling Methods 0.000 abstract description 31
- 239000002699 waste material Substances 0.000 abstract description 4
- 230000005611 electricity Effects 0.000 description 12
- 230000003071 parasitic effect Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 7
- 238000004804 winding Methods 0.000 description 5
- 238000001514 detection method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000004308 accommodation Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/005—Electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/005—Electrodes
- H01G4/008—Selection of materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/018—Dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/018—Dielectrics
- H01G4/06—Solid dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
The present invention provides high-pressure flat plate electric capacity and demagnetization sample circuit, wherein high-pressure flat plate electric capacity includes top crown and bottom crown, described top crown is placed in above bottom crown, described top crown is metallic conduction plate, bottom crown is low-doped n type semiconductor board, first medium layer and second dielectric layer it is disposed with from top to bottom between top crown and bottom crown, second dielectric layer is provided with metal area, being provided with heavily doped N-type semiconductor region in bottom crown, first medium layer is provided with connection metal area and the conductive through hole of heavily doped N-type semiconductor region.The high-pressure flat plate electric capacity of the present invention can use device of the present invention to carry out demagnetization sampling as demagnetization Sampling device in the Application Design such as AC/DC LED driving, it is not necessary to extra demagnetization Sampling device waste chip area, this high-voltage capacitance can regulate as required simultaneously.
Description
Technical field
The present invention relates to electronic circuit field, particularly relate to high-performance high-pressure flat plate electric capacity and demagnetization sampling electricity
Road.
Background technology
How to detect the demagnetization of peripheral system inductor device in applications such as AC/DC LED drivings to terminate
One of signal key becoming current design.Prior art totally can be divided into two classes: 1, utilizes outside chip
The demagnetization signal of inductance, transformer coil is sampled chip feed back input port by the resistance pressure-dividing network enclosed.
2, the demagnetization signal of chip internal high pressure parasitic capacitance sampling system is utilized.
The most traditional first kind demagnetization sampling schematic diagram is as shown in Figure 1.First kind demagnetization sampling side
Former for transformator T1 limit demagnetization signal is transformed in auxiliary winding by formula, then by R1, R2 resistance to moving back
Magnetic signal carries out dividing potential drop sampling.Switching logic control circuit is provided to process sampling gained demagnetization signal, defeated
Go out corresponding signal and control switching device Q1.
Equations of The Second Kind utilizes high-voltage grid drain capacitance Cgd demagnetization the sampling schematic diagram such as figure of an extra HVMOS
Shown in 2, additionally increasing a HVMOS device at chip internal, the source electrode of this HVMOS device hangs
Empty or by source electrode and the mode such as grid is connected.Drain-gate capacitance Cgd detection demagnetization signal, demagnetizes gained
Signal provides switching logic control circuit to process.
The implementation of existing high-voltage capacitance has substantially with the implementation still imperfection of demagnetization sample circuit
Shortcoming.
First its shortcoming of the implementation of the high-voltage capacitance of prior art is: A, the high pressure of prior art
Electric capacity is that HVMOS parasitism gate leakage capacitance forms series relationship with gate-source capacitance, grid capacitance to substrate simultaneously,
When actually used, the impact of the biased voltage of gate leakage capacitance and other parasitic capacitance cannot function as one solely
Vertical high-voltage capacitance uses.B, needs increase a High-tension Switch Devices at chip internal and utilize its grid leak electricity
Holding, generally this capacitance is smaller, needs to increase the size of High-tension Switch Devices to increase capacitance,
This mode serious waste chip area, chip cost is high.
And its shortcoming of implementation of existing demagnetization Sampling techniques is: A, first kind demagnetization sampling side
Formula system peripherals needs additional auxiliary winding, divider resistance and feedback port, increases system cost；B,
One class demagnetization sample mode chip demagnetization signal feedback port is easily disturbed, and causes demagnetization sampling instability.C、
Equations of The Second Kind demagnetization sample mode needs to increase a High-tension Switch Devices at chip internal and utilize its grid leak electricity
Holding, generally this capacitance is smaller, needs to increase the size of High-tension Switch Devices to increase capacitance,
This mode serious waste chip area.
Traditional switching device LDMOS high pressure gate-drain parasitic capacitances structure cell schematic diagram as it is shown on figure 3,
Traditional LDMOS is that four-terminal device is respectively DRAIN, GATE, SOURCE, SUBSTRATE.
The high-voltage grid drain capacitance of LDMOS device is mainly made up of two parts: a part is grid and trench ends electricity
Hold；Another part is the covering electric capacity between field plate and drift region, grid and pole, field in traditional devices
Plate is connected, and gate-drain parasitic Cgd is the two electric capacity sum, and the two electric capacity and LDMOS have identical
Pressure.The shortcoming of the most traditional Cgd high-voltage capacitance is: 1, grid G ATE is not only
A pole plate as Cgd electric capacity is also one pole plate of Cgs, Cgb electric capacity simultaneously.This means that
High-voltage capacitance Cgd parasitic for LDMOS, by GATE Yu Cgs, Cgb capacitances in series, utilizes in reality
Need to take into full account the interaction of each electric capacity during Cgd, limit the use of high-voltage capacitance Cgd.2, pass
The Cgd high-voltage capacitance of system needs the most additionally to increase a high-voltage switch gear when applying to demagnetization sampling
The chip area of device.
Summary of the invention
The technical problem to be solved in the present invention, is to provide
High-pressure flat plate electric capacity and demagnetization sample circuit, solve existing high-voltage capacitance cost height, demagnetization sampling electricity
The problem that road cost is high, chip area is big.
The present invention is achieved in that the first high-pressure flat plate electric capacity, including top crown and bottom crown, institute
Stating top crown and be placed in above bottom crown, described top crown is metallic conduction plate, and bottom crown is low-doped n type
Semiconductor board, is disposed with first medium layer and second medium from top to bottom between top crown and bottom crown
Layer, is provided with metal area, is provided with heavily doped N-type semiconductor region in bottom crown in second dielectric layer, the
One dielectric layer is provided with connection metal area and the conductive through hole of heavily doped N-type semiconductor region.
Further, bottom crown lower surface is provided with P type substrate layer.
Further, metal area is to be arranged on the annulus bottom second dielectric layer.
Further, heavily doped N-type semiconductor region is arranged on the top of bottom crown.
And the present invention also provides for the second high-pressure flat plate electric capacity, including top crown and bottom crown, described on
Pole plate is placed in above bottom crown, and described top crown is polycrystalline silicon material plate or metallic conduction plate, described under
Pole plate is n-type doping semiconductor board, and bottom crown top is provided with low-doped P-type semiconductor district and heavy doping
N-type semiconductor district, is provided with field oxide between top crown and low-doped P-type semiconductor district, field aoxidizes
Layer upper surface, heavily doped N-type semiconductor region upper surface are provided with first medium layer, table on first medium layer
Face is provided with second dielectric layer, is provided with the first metal area bottom second dielectric layer, table in second dielectric layer
Face is provided with the second metal area, is provided with connection heavily doped N-type semiconductor region and first in first medium layer
First conductive through hole of metal area, is provided with the of the first metal area and the second metal area in first medium layer
Two conductive through holes.
Further, bottom crown lower surface is provided with P type substrate layer.
Further, when described top crown is polycrystalline silicon material plate, top crown is arranged on first medium layer
Bottom and at the upper surface of field oxide；
Or described top crown be with the first metal area with the metallic conduction plate of material time, top crown is arranged on
The bottom of second dielectric layer and at the upper surface of first medium layer；
Or described top crown be with the second metal area with the metallic conduction plate of material time, top crown is arranged on
The upper surface of second dielectric layer.
Further, described top crown is annular slab.
And on the basis of above-mentioned capacity plate antenna, the present invention also provides for a kind of demagnetization sample circuit, including height
Locating back electric capacity, high voltage power device, inductor device, output rectification circuit, demagnetization signal sampling electricity
Road, demagnetization time timing circuit and switching logic control circuit；
One end of inductor device primary coil is connected with positive source, inductor device primary coil another
One end is connected with the high-pressure side of high-pressure flat plate electric capacity and the drain electrode of high voltage power device, and inductor device is secondary
Coil is connected with output rectification circuit, and the low-pressure end of high-pressure flat plate electric capacity is defeated with demagnetization signal sample circuit
Entering end to connect, the outfan of demagnetization signal sample circuit is connected with the input of demagnetization time timing circuit,
The outfan of demagnetization time timing circuit is connected with the input of switching logic control circuit, switching logic control
The outfan of circuit processed is connected with the grid of high voltage power device, and the source electrode of high voltage power device is born with power supply
Pole connects；
Described high-pressure flat plate electric capacity is for detecting the demagnetization signal of the drain electrode of high voltage power device, and will examine
The demagnetization signal measured exports demagnetization signal sample circuit；
The demagnetization signal of input is converted into digital level and is input to described by described demagnetization signal sample circuit
Demagnetization time timing circuit；
When described demagnetization time timing circuit is used for the demagnetization according to digital level record inductor device
Between, this demagnetization time is input to described switching logic control circuit；
Described switching logic control circuit controls conducting and the shutoff of high voltage power device according to the demagnetization time
Time；
Described high-pressure flat plate electric capacity is the high-pressure flat plate electric capacity described in any of the above-described item.
Further, described demagnetization signal sample circuit includes voltage comparator or current comparator.
Present invention have the advantage that A, the present invention high-pressure flat plate electric capacity with traditional high pressure drain-gate electricity
Hold parallel connection, not by gate-source capacitance, the tandem effects of grid capacitance to substrate, this high-voltage capacitance be one independent
Electric capacity its value simultaneously can be realized by regulation capacity area according to actual needs.B, the high-voltage flat of the present invention
Plate electric capacity can use the present invention as demagnetization Sampling device in the Application Design such as AC/DC LED driving
Device carries out demagnetization sampling, it is not necessary to extra demagnetization Sampling device waste chip area, simultaneously this high-tension electricity
Appearance can regulate as required.C, the demagnetization sample circuit of the present invention utilize the high-pressure flat plate electric capacity of the present invention to examine
Surveying demagnetization signal, high-pressure flat plate electric capacity can need to be placed on any position according to chip layout layout.So
Be effectively reduced chip area, and relative to first kind sample mode save auxiliary winding, divider resistance and
Feedback port, hence it is evident that saved chip cost and system cost.
Accompanying drawing explanation
Fig. 1 is that the tradition first kind utilizes auxiliary winding and divider resistance demagnetization sampling schematic diagram；
Fig. 2 is the high pressure drain-gate capacitance Cgd demagnetization sampling schematic diagram that tradition utilizes HVMOS；
Fig. 3 is that Conventional switch devices LDMOS gate leaks parasitic capacitance structure cell schematic diagram；
Fig. 4 is traditional switching device LDMOS device plane schematic top plan view；
Fig. 5 is the first high-pressure flat plate electric capacity top view of the present invention；
Fig. 6 is the first high-pressure flat plate electric capacity profile of the present invention；
Fig. 7 is the second high-pressure flat plate electric capacity schematic top plan view of the present invention；
Fig. 8 is the second high-pressure flat plate electric capacity generalized section of the present invention (intercepting the left-half of Fig. 7)；
Fig. 9 is that the second high-pressure flat plate electric capacity profile of the present invention is with M1 for top crown schematic diagram；
Figure 10 is that the second high-pressure flat plate electric capacity profile of the present invention is with M2 for top crown schematic diagram；
Figure 11 is that the present invention utilizes high-pressure flat plate electric capacity to carry out the circuit diagram of demagnetization sampling.
Detailed description of the invention
By describing the technology contents of the present invention, structural feature in detail, being realized purpose and effect, below tie
Close embodiment and coordinate accompanying drawing to be explained in detail.
Refer to Fig. 1 to Figure 11, present invention firstly provides the implementation of two kinds of high-pressure flat plate electric capacity, and
The demagnetization sample circuit that rear proposition realizes according to capacity plate antenna of the present invention.
One, the implementation method of the first high-pressure flat plate electric capacity and principle, its top plan view as shown in Figure 5,
Profile is as shown in Figure 6.In Fig. 6, Psub is can be plus outside p-type on P type substrate this substrate if desired
Prolong layer (i.e. P type substrate layer)；Nwell is low-doped n type semiconductor regions；M1, M2 are that metal is led
Electric material；Medium 1 is the isolated material between M1 metal and Nwell；Medium 2 be M2 metal with
Isolated material between M1 metal；N+ is that N-type heavily-doped semiconductor region is as Ohmic contact；W1
For the conductive through hole between M1 metal and N+.
The first capacity plate antenna comprises top crown and bottom crown, and top crown is M2, bottom crown is Nwell
(Nwell with M1 is connected), by medium 1 (i.e. first medium layer) and medium between M2 and Nwell
2 (second dielectric layer) form a capacity plate antenna.Bottom crown Nwell by N+ inject, W1 hole with
M1 is connected, and when using this high-pressure flat plate electric capacity, M1 metal (i.e. metal area) is connected to the ground needed
Side.Bottom crown M1 connects low-pressure end.Top crown is M2 metal, and top crown M2 is connected to the height of circuit
Pressure side.Design field is driven, it will usually top crown M2 metal is connected to high-voltage LDMOS at LED
High pressure DRAIN end (drain electrode) of power tube.Utilize this high-pressure flat plate electric capacity can sample LDMOS
The change in voltage of DRAIN end.
When top crown M2 metal is connected to high-pressure side, due to the specific medium 1 formed in manufacturing process
High pressure can be born with medium 2, hold from without breakdown potential.
Formula according to capacity plate antenna: electric capacity
The dielectric constant ρ of the first high-pressure flat plate electric capacity of the present invention and medium 1, medium 2 are relevant；S is
The right opposite of capacity plate antenna amasss, and is the area of top crown M2 in the present invention；D is the upper and lower of capacity plate antenna
The spacing of pole plate, is the thickness of medium 1+ medium 2 in the present invention.According to above formula, using
The area i.e. area of top crown M2 of S can be regulated as required during this electric capacity.
The first high-pressure flat plate capacitance size of the present invention can by regulation top crown M2 metal with under
The right opposite of pole plate Nwell amasss and realizes.The i.e. value of this separate high pressure capacity plate antenna can be according to actual need
Capacity area to be adjusted, compares traditional parasitic high-voltage capacitance and has bigger range of accommodation, and phase
Bigger electric capacity can be realized in equal area than traditional parasitic high-voltage capacitance.
As it is shown in figure 5, high-voltage capacitance top crown M2 metal of the present invention retains with bottom crown M1 metal
Certain spacing, on the one hand prevents the high pressure interference to other circuit on top crown M2, ensures M2 simultaneously
The thickness that between metal and M1 metal, medium is certain realizes pressure.Metal area can be to be arranged on second Jie
Annulus bottom matter layer.Heavily doped N-type semiconductor region can be the top being arranged on bottom crown.
Two, the implementation method of the second high-pressure flat plate electric capacity and principle, its top view as shown in Figure 7, cut open
Face figure is as shown in Figure 8.In fig. 8, Psub is P type substrate region (i.e. P type substrate layer)；DN is
N-type doping semiconductor regions；PT is low-doped P-type semiconductor region；FOX is field oxide region；
D1 is the isolated material between M1 metal and lower floor；D2 is the isolated material between M2 metal and lower floor；
N+ is that N-type heavily doped region is for Ohmic contact；Poly is polycrystalline silicon material；W1 be M1 metal with
Conductive through hole between N+；W2 is the conductive through hole between M2 metal and M1 metal.Wherein top crown
Polysilicon Poly is used for connecting low-pressure end, bottom crown DN and M2 metal is connected and for being connected high-pressure side.
The second high-pressure flat plate electric capacity, including top crown and bottom crown, described top crown is placed on bottom crown
Side, described top crown is polycrystalline silicon material plate or metallic conduction plate, and described bottom crown is n-type doping half
Conductor plate, bottom crown top is provided with low-doped P-type semiconductor district and heavily doped N-type semiconductor region, on
Field oxide, field oxide upper surface, heavy doping N it is provided with between pole plate and low-doped P-type semiconductor district
Type semiconductor region upper surface is provided with first medium layer, and first medium layer upper surface is provided with second dielectric layer,
Being provided with the first metal area bottom second dielectric layer, second dielectric layer upper surface is provided with the second metal area,
The first conduction being provided with connection heavily doped N-type semiconductor region and the first metal area in first medium layer is logical
Hole, is provided with the second conductive through hole of the first metal area and the second metal area in first medium layer.
As in Fig. 8 to Figure 10, D2 is second dielectric layer, and D1 is first medium layer, and Poly is top crown,
DN is bottom crown, and PT is low-doped P-type semiconductor district, and M1 is the first metal area, and M2 is the second gold medal
Belong to district, N+ is heavily doped N-type semiconductor region, in Fig. 8 top crown be arranged on first medium layer bottom and
Upper surface at field oxide.
The top crown of the second high-pressure flat plate electric capacity of the present invention is Poly (polycrystalline silicon material plate), lower pole
Plate is DN, and wherein DN is connected by N+ with W1, M1, W2, M2 the connection end of therefore bottom crown
For M2 metal.Between upper bottom crown, medium is FOX layer (field oxide).
The right opposite of the second high-pressure flat plate electric capacity of the present invention amasss the area that S is polysilicon Poly, is situated between
Matter thickness is about the thickness of field oxide FOX.
The big I of the second high-pressure flat plate electric capacity of the present invention is by regulation top crown Poly and bottom crown
The right opposite of DN is long-pending to be realized.The value of this separate high pressure capacity plate antenna can be adjusted electricity according to actual needs
Hold area, compare traditional parasitic high-tension electricity and have bigger range of accommodation, and compare traditional parasitic height
Voltage capacitance can realize bigger electric capacity in equal area.
The second high-pressure flat plate electric capacity of the present invention has high voltage bearing performance.When bottom crown M2 metal connects
When connecing high-pressure side, in Fig. 7, N+, DN region is also high-pressure side, and high pressure makes two poles that DN Yu PT is constituted
Managing reverse-biased, the depletion region of diode expands, and can realize high voltage bearing performance by diode depletion region.
The top crown of the second high-pressure flat plate electric capacity of the present invention also can come real by M1 or M2
Existing.As it is shown in figure 9, described top crown be with the first metal area with the metallic conduction plate of material time, upper pole
Plate is arranged on the bottom of second dielectric layer and at the upper surface of first medium layer.As shown in Figure 10, on described
Pole plate be with the second metal area with the metallic conduction plate of material time, top crown is arranged on the upper of second dielectric layer
Surface.
To sum up, the high-pressure flat plate electric capacity of the present invention has the following advantages relative to prior art:
(1) the drain-gate capacitance phase of high-pressure flat plate electric capacity of the present invention and traditional power tube LDMOS
Ratio, electric capacity of the present invention does not constitutes series relationship with Cgd, Cgb of power tube, is not imitated by circuit Miller
The impact answered.
(2) high-pressure flat plate electric capacity of the present invention can be placed on any of chip layout according to actual needs
Position, uses as separate high pressure electric capacity, it is not necessary to be integrated in power tube LDMOS.
(3) high-pressure flat plate electric capacity of the present invention can regulate capacity area size, phase according to actual needs
Use more convenient than conventional parasitic high-voltage capacitance.
Three, the invention allows for a kind of circuit utilizing described high-pressure flat plate electric capacity to carry out demagnetization sampling,
Described demagnetization sample circuit comprises two kinds of high-pressure flat plate electric capacity, high voltage power devices that the present invention proposes
HVMOS, inductor device and output rectification circuit, demagnetization signal sample circuit, demagnetization time timing electricity
Road, switching logic control circuit.
Described high-pressure flat plate electric capacity for detecting the demagnetization signal of power tube drain terminal, will detect simultaneously
Demagnetization signal exports demagnetization signal sample circuit and processes.
Described inductor device and output rectification circuit are when system worked well: produce demagnetization and start and knot
Bundle signal, transfers energy to load simultaneously.
Described high voltage power device LDMOS device is as switching device.
The demagnetization signal of input is converted into digital level and is input to described by described demagnetization signal sample circuit
Demagnetization time timing circuit.
The described demagnetization time timing circuit record inductor device demagnetization time, this demagnetization time is input to
Described switching logic control circuit realizes constant output current and calculates.
Described switching logic control circuit, according to constant output current algorithm, controls the conducting of switching device
With the turn-off time.
The high-voltage capacitance device using the present invention carries out the circuit of demagnetization signal sampling, has following useful effect
Really:
(1) the high-voltage capacitance device sampling demagnetization signal utilizing the present invention can save the auxiliary of chip periphery
Winding and resistance sampling network, reduce system cost.
(2) the high-voltage capacitance device capacitance size of the present invention can be according to the demand regulation of demagnetization sample circuit.
In order to the technology contents of the clearer description present invention, enumerate reality below according to spirit of the present invention
Execute example and carry out labor.
Specifically, the circuit utilizing high-pressure flat plate electric capacity to carry out demagnetization sampling of the present invention, its circuit is tied
Fruit is as shown in figure 11.And traditional demagnetization sample circuit is as shown in Figure 1 and Figure 2.Traditional demagnetization sampling
Circuit is required to extra demagnetization Sampling device when detection demagnetization.The demagnetization sample circuit of the present invention comprises
Output rectification circuit, inductor device transformator T1, integrated high voltage electric capacity LDMOS device Q1, high pressure
Capacity plate antenna 1, demagnetization signal sample circuit 2, demagnetization time timing circuit 3, switching logic control circuit
4。
One end primary for transformator T1 connects the other end that input power positive pole Vin+, transformator T1 are primary
The DRAIN end of connecting valve device LDMOS and the high-pressure side of high-pressure flat plate electric capacity.Transformator T1 time
One end of level connects the diode D1 positive pole of output rectification circuit, and the other end of T1 level of transformator connects
The negative pole of output rectification circuit filter capacitor C1, the both positive and negative polarity of load circuit connects diode D1 respectively and bears
Pole, filter capacitor C1 negative pole.
The high-pressure side of high-pressure flat plate electric capacity connects the input of demagnetization signal sample circuit, passes through high-pressure flat plate
Electric capacity sampling demagnetization signal.
The input of demagnetization signal sample circuit 2 connects the low-pressure end of high-pressure flat plate electric capacity, and demagnetization signal is adopted
Sample circuit can be realized by voltage comparator or current comparator, will detection gained demagnetization signal and comparator
Reference signal compare.Demagnetization signal sample circuit 2 is output as digital logic level, demagnetization letter
The outfan of number sample circuit 2 connects the input of demagnetization time timing circuit 3.
The input of demagnetization time timing circuit 3 connects the outfan of demagnetization signal sample circuit 2, demagnetization
Time timing circuit 3 starts timing from the switching device LDMOS shutoff moment, by demagnetization signal sampling electricity
Road 2 samples demagnetization end signal.The demagnetization time input of detection gained is opened by demagnetization time timing circuit 3
Close logic control circuit 4.
The input of switching logic control circuit 4 connects the outfan of demagnetization time timing circuit 3, switch
Logic control circuit 4, according to the switching frequency of constant output current algorithm controls switching device Q1.Switch
Logic control circuit 3 outputs a control signal to the GATE pole of switching device Q1.
The foregoing is only embodiments of the invention, not thereby limit the scope of patent protection of the present invention,
Every equivalent structure utilizing description of the invention and accompanying drawing content to be made or equivalence flow process conversion, or directly
Or indirectly it is used in other relevant technical fields, the most in like manner it is included in the scope of patent protection of the present invention.
Claims (10)
1. high-pressure flat plate electric capacity, it is characterised in that: include that top crown and bottom crown, described top crown are placed in
Above bottom crown, described top crown is metallic conduction plate, and bottom crown is low-doped n type semiconductor board, on
First medium layer and second dielectric layer, second medium it is disposed with from top to bottom between pole plate and bottom crown
Being provided with metal area in Ceng, be provided with heavily doped N-type semiconductor region in bottom crown, first medium layer is arranged
There are connection metal area and the conductive through hole of heavily doped N-type semiconductor region.
High-pressure flat plate electric capacity the most according to claim 1, it is characterised in that: bottom crown lower surface sets
It is equipped with P type substrate layer.
High-pressure flat plate electric capacity the most according to claim 1, it is characterised in that: metal area is for being arranged on
Annulus bottom second dielectric layer.
High-pressure flat plate electric capacity the most according to claim 1, it is characterised in that: heavily doped N-type is partly led
Body district is arranged on the top of bottom crown.
5. high-pressure flat plate electric capacity, it is characterised in that: include that top crown and bottom crown, described top crown are placed in
Above bottom crown, described top crown is polycrystalline silicon material plate or metallic conduction plate, and described bottom crown is N
Type doped semiconductor plate, bottom crown top is provided with low-doped P-type semiconductor district and heavily doped N-type is partly led
Body district, is provided with field oxide between top crown and low-doped P-type semiconductor district, field oxide upper surface,
Heavily doped N-type semiconductor region upper surface is provided with first medium layer, and first medium layer upper surface is provided with
Second medium layer, is provided with the first metal area bottom second dielectric layer, second dielectric layer upper surface is provided with
Two metal areas, are provided with in first medium layer and connect the of heavily doped N-type semiconductor region and the first metal area
One conductive through hole, is provided with the second conductive through hole of the first metal area and the second metal area in first medium layer.
High-pressure flat plate electric capacity the most according to claim 5, it is characterised in that: bottom crown lower surface sets
It is equipped with P type substrate layer.
High-pressure flat plate electric capacity the most according to claim 5, it is characterised in that:
When described top crown is polycrystalline silicon material plate, top crown is arranged on the bottom of first medium layer and on the scene
The upper surface of oxide layer；
Or described top crown be with the first metal area with the metallic conduction plate of material time, top crown is arranged on
The bottom of second dielectric layer and at the upper surface of first medium layer；
Or described top crown be with the second metal area with the metallic conduction plate of material time, top crown is arranged on
The upper surface of second dielectric layer.
High-pressure flat plate electric capacity the most according to claim 5, it is characterised in that: described top crown is ring
Shape plate.
9. a demagnetization sample circuit, it is characterised in that include high-pressure flat plate electric capacity, high voltage power device,
Inductor device, output rectification circuit, demagnetization signal sample circuit, demagnetization time timing circuit and switch
Logic control circuit；
One end of inductor device primary coil is connected with positive source, inductor device primary coil another
One end is connected with the high-pressure side of high-pressure flat plate electric capacity and the drain electrode of high voltage power device, and inductor device is secondary
Coil is connected with output rectification circuit, and the low-pressure end of high-pressure flat plate electric capacity is defeated with demagnetization signal sample circuit
Entering end to connect, the outfan of demagnetization signal sample circuit is connected with the input of demagnetization time timing circuit,
The outfan of demagnetization time timing circuit is connected with the input of switching logic control circuit, switching logic control
The outfan of circuit processed is connected with the grid of high voltage power device, and the source electrode of high voltage power device is born with power supply
Pole connects；
Described high-pressure flat plate electric capacity is for detecting the demagnetization signal of the drain electrode of high voltage power device, and will examine
The demagnetization signal measured exports demagnetization signal sample circuit；
The demagnetization signal of input is converted into digital level and is input to described by described demagnetization signal sample circuit
Demagnetization time timing circuit；
When described demagnetization time timing circuit is used for the demagnetization according to digital level record inductor device
Between, this demagnetization time is input to described switching logic control circuit；
Described switching logic control circuit controls conducting and the shutoff of high voltage power device according to the demagnetization time
Time；
Described high-pressure flat plate electric capacity is the high-pressure flat plate electric capacity described in any one of claim 1 to 8.
Demagnetization sample circuit the most according to claim 9, it is characterised in that: described demagnetization signal
Sample circuit includes voltage comparator or current comparator.
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| CN201510565641.6A CN105140305B (en) | 2015-09-08 | 2015-09-08 | High-pressure flat plate electric capacity and demagnetization sample circuit |
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| CN201510565641.6A CN105140305B (en) | 2015-09-08 | 2015-09-08 | High-pressure flat plate electric capacity and demagnetization sample circuit |
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| JP3576144B2 (en) * | 2002-03-15 | 2004-10-13 | 沖電気工業株式会社 | Method for manufacturing semiconductor device |
| KR20050051140A (en) * | 2003-11-27 | 2005-06-01 | 삼성에스디아이 주식회사 | Capacitor and flat panel display therewith |
| JP4410085B2 (en) * | 2004-11-24 | 2010-02-03 | 日本電信電話株式会社 | Variable capacitance element and manufacturing method thereof |
| CN1988158A (en) * | 2005-12-23 | 2007-06-27 | 上海华虹Nec电子有限公司 | Flat plate capacitor and its realizing method |
| CN101989621B (en) * | 2009-08-06 | 2012-03-07 | 中芯国际集成电路制造(上海)有限公司 | Metal-insulator-metal (MIM) capacitor and manufacturing method thereof |
| CN103280316A (en) * | 2013-06-04 | 2013-09-04 | 周国清 | Capacitor |
| CN103605090B (en) * | 2013-11-26 | 2017-02-08 | 美芯晟科技（北京）有限公司 | Demagnetization detection method, demagnetization detection circuit and constant current driver using circuit |
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