CN105140103A - Semiconductor substrate and method for selectively growing semiconductor material - Google Patents
Semiconductor substrate and method for selectively growing semiconductor material Download PDFInfo
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Abstract
The invention discloses a semiconductor substrate and a method for selectively growing a semiconductor material. The semiconductor substrate a crystal growth surface for semiconductor material epitaxy, and one or more dielectric layer surfaces for limiting the growth of the semiconductor material; the semiconductor material growth method is for performing selective growth of the semiconductor material; normally, in the selective growth process, the semiconductor material can only grow on the crystal growth surface and cannot directly grow on the dielectric layer surfaces; the dielectric layer surfaces are used for limiting the semiconductor material from growing on a certain direction in the selective growth process. The special-structured substrate is combined with the selective growth, so that spread of dislocation and other shortcomings in the semiconductor material growth process can be effectively restrained, so as to dramatically improve the quality of the semiconductor material.
Description
Technical field
The present invention relates to microelectronics technology, particularly relate to a kind of method of Semiconductor substrate and selective growth semi-conducting material.
Background technology
III nitride semiconductor, especially gallium nitride and alloy semiconductor thereof are causing increasing concern, it is together with SiC and be called third generation wide bandgap semiconductor, its special character may be used for the semiconductor device manufacturing various superior performance, and is widely used in the fields such as power electronic device, light-emitting diode, laser diode, microwave device, high-frequency element.But the intrinsic substrate of many semi-conducting materials is difficult to obtain, and can only grow in the single crystal substrates of other materials.For GaN, because GaN intrinsic substrate is difficult to obtain, GaN grows usually on other materials substrate, as sapphire, SiC, silicon etc.Wherein, silicon substrate uses for many years in CMOS technology, and its single-chip manufacturing technology relative maturity, can obtain the monocrystalline silicon piece of large-size high-quality, cheap, and CMOS technology supporting is with it also very ripe.Therefore, preparing GaN is on a silicon substrate the optimal selection reducing GaN device cost.
The process of the another kind of different monocrystal material of the above-mentioned superficial growth at a kind of monocrystal material is called heteroepitaxy, under normal circumstances, all there is two problems in the heteroepitaxy of all semi-conducting materials, namely the lattice mismatch between different semi-conducting material and thermal mismatching, above-mentioned lattice mismatch and the quality of thermal mismatching on semiconductor epitaxial layers have very important impact, epitaxial layer quality may be caused too low and cannot make semiconductor device time serious.For GaN in Si surface extension, owing to there is larger lattice mismatch and thermal mismatching between GaN and Si, in preparation and temperature-fall period, produce very large stress.These stress can cause a large amount of defects in crystal, and epitaxial film even can be made to ftracture.Meanwhile, the substrate warpage that stress causes makes the techniques such as follow-up photoetching to carry out.And high density of defects can affect the performance of device, such as the current GaN base LED component light emission rate prepared on Si is much smaller than the GaN base LED component prepared on sapphire.In order to avoid this situation, usual way uses patterned substrate and epitaxial lateral overgrowth, the method deposits one deck dielectric layer on a si substrate, dielectric layer outputs window, then by selective growth growing GaN in the window, continuous film is formed finally by the epitaxial lateral overgrowth on dielectric layer.The shortcoming of this method is when epitaxial lateral overgrowth forms continuous film, the defect concentration of film merging place is very high, the GaN in these regions cannot be used for device preparation, in addition, after continuous film is formed, do not have dielectric layer to stop during film continued growth, dislocation can continue to propagate along with film growth, can not reduce defect concentration further.
Also there is same problem in other heteroepitaxy, such as grows III-compound semiconductor (GaAs etc.) at Si, Si grows IV race semiconductor (Ge etc.)
Therefore, for the problems referred to above and improve one's methods, be necessary to propose a kind of Novel substrate structure and semiconductor making method.
Summary of the invention
The object of the invention is to for the deficiencies in the prior art, a kind of method of Semiconductor substrate and selective growth semi-conducting material is provided.
The object of the invention is to be achieved through the following technical solutions: a kind of Semiconductor substrate, described substrate comprises one and is positioned at the suprabasil crystal growth plane for semiconductor material growing of dielectric layer and is positioned at crystal growth plane both sides with two and the dielectric layer surface be connected with crystal growth plane, two dielectric layer surface, to external expansion, form funnel-shaped structure with crystal growth plane; Described crystal growth plane contains a single facet be made up of monocrystalline.
Further, described substrate can also comprise the dielectric layer surface that is positioned at the top of crystal growth plane and dielectric layer side, and described dielectric layer surface is relative with dielectric layer substrate.
Further, described crystal growth plane can also contain one or more dielectric layer surface.
Further, span up and down and the left and right span of described crystal growth plane are all less than 100 μm, are preferably less than 1 μm, more preferably below 100nm.
Further, described monocrystalline is selected from Si, SiGe, Ge, GaN, GaAs, InP, InN, AlGaAs, AlGaN, InPGaN etc.
Further, described dielectric layer surface is by SiO
2, one or more in the material such as SiN or HfO form.
A method for selective growth semi-conducting material, the method adopts above-mentioned substrate, realizes selective growth by technological means such as MOCVD, MBE, HVPE.
Further, the presoma used in described selective growth process is TMGa, TEGa, NH
3, AsH
3, PH
3, SiH
4, GeH
4, SiH
2cl
2, TMAl, TBAs etc.
Further, described selective growth adopts etching gas, and described etching gas is Cl
2, HCl etc.
Further, the semi-conducting material that described selective growth method grows is Si, SiGe, Ge, GaN, GaAs, InP, InN, AlGaAs, AlGaN, InPGaN etc.
Beneficial effect of the present invention is, first, single-crystal surface size for inducing semiconductor materials growth is very little, document is had to show, undersized epitaxial growth plane contributes to reducing defect concentration, small size single-crystal surface in the present invention just can suppress the generation of defect at the Material growth initial stage, thus reduces defect concentration.Secondly, be dielectric layer surface in the both sides of aufwuchsplate, the growth of dielectric layer surface to semi-conducting material plays effect of contraction, when the dislocation propagation in semi-conducting material stops to during dielectric layer surface, cannot continue to propagate, thus reduce defect concentration.Finally, in the present invention, the method for growing semiconductor material used is selective growth, and when using this growing method, semi-conducting material cannot can only grow at dielectric layer surface in plane of crystal growth, in conjunction with the structure of above-mentioned substrate, realize the growth at small size single-crystal surface.When making in this way, the Main Function of dielectric layer is, restriction semi-conducting material growth in a certain direction on the one hand, guides it to grow on other required direction on the other hand.Meanwhile, due to dielectric layer surface and dielectric layer surface and form abducent funnel-shaped structure for the surface 1 of crystal growth, this structure effectively guided from surface-borne heteroepitaxial semiconductor material out along with growth area increasing.
Accompanying drawing explanation
Fig. 1 is substrate 45 degree of schematic top plan view of a kind of micro-nano technology.
Fig. 2 is substrate 45 degree of schematic top plan view of a kind of embodiment.
Fig. 3 is substrate 45 degree of schematic top plan view of a kind of embodiment.
Fig. 4 is substrate 45 degree of schematic top plan view of embodiment 1.
Fig. 5 is the substrate vertical view of embodiment 1.
Fig. 6 is substrate 45 degree of schematic top plan view of embodiment 2.
Fig. 7 is the substrate vertical view of embodiment 2.
Fig. 8 is substrate 45 degree of schematic top plan view of embodiment 3.
Fig. 9 is the substrate vertical view of embodiment 3.
Figure 10 is substrate 45 degree of schematic top plan view of embodiment 4.
Figure 11 is the substrate vertical view of embodiment 4.
Figure 12 is substrate 45 degree of schematic top plan view of embodiment 5.
Figure 13 is the substrate vertical view of embodiment 5.
Figure 14 is substrate 45 degree of schematic top plan view of embodiment 6.
Figure 15 is the substrate vertical view of embodiment 6.
The circumscribed circle schematic diagram of Figure 16 crystal growth plane, in figure, dash area represents the bottom surface in hole.
Wherein, 1 is crystal growth plane, and 2 is first medium layer surface, and 3 is second dielectric layer surface, and 4 is the 3rd dielectric layer surface, and 5 is the 4th dielectric layer surface, and 11 is single-crystal surface, and 12 is the 5th dielectric layer surface.
Embodiment
In the present invention, term used " dielectric layer surface " refers in particular to when semi-conducting material selective growth, the surface that semi-conducting material cannot grow thereon.The Performance comparision of dielectric layer material is special, and semi-conducting material cannot in its surperficial forming core or growth, or forming core speed and growth rate very slow, compare with the forming core speed of semi-conducting material at single-crystal surface can ignore with growth rate.Under normal circumstances, dielectric layer material is amorphous insulating material, as SiO
2, SiN, HfO etc.
In the heteroepitaxy process of the another kind of different semi-conducting material of a kind of superficial growth of single-crystal semiconductor material, due to the lattice mismatch existed between two kinds of semi-conducting materials, result in the formation of stress in material.Semi-conducting material can reduce the stress in whole semi-conducting material by defects such as formation dislocations, above-mentioned dislocation has certain direction, after generation, can propagate along with the growth of semi-conducting material along fixing direction.The thermal coefficient of expansion existed between semi-conducting material inconsistent, can the formation of aggravation stress and crystal defect further when variations in temperature.In this heteroepitaxial structure, if reduced for the length and width size of the mother crystal aufwuchsplate of heteroepitaxial growth, then the stress in the another kind of material grown out thereon also will reduce thereupon, and defect also reduces thereupon.When enough hour (being called critical dimension) of length and width size of mother crystal aufwuchsplate, then the dislocation defects in the another kind of material grown out thereon will disappear completely.On the other hand, as the length and width size of mother crystal aufwuchsplate than critical dimension large and produce dislocation defects time, when dislocation runs into block media layer in the propagation direction, dislocation will stop propagating, thus significantly promotes the quality of semi-conducting material.
Based on above principle, the present invention proposes a kind of micro-nano technology substrate (Fig. 1 and Fig. 2) and prepares fabricating low-defect-density semi-conducting material, described substrate comprises the crystal growth plane 1 be positioned in dielectric layer substrate 4, and is positioned at first medium layer surface 2, the second dielectric layer surface 3 of crystal growth plane 1 both sides; First medium layer surface 2 and second dielectric layer surface 3, to external expansion, form funnel-shaped structure with crystal growth plane 1; Described crystal growth plane 1 is containing a single-crystal surface be made up of monocrystalline, and namely crystal growth plane 1 can be all be made up of monocrystalline, also can be that wherein part is monocrystalline.Crystal growth plane 1 is for the growth of induced semiconductor crystal; Semi-conducting material cannot be grown directly upon on first medium layer surface 2, second dielectric layer surface 3 and the 3rd dielectric layer surface 4, the propagation that the present invention utilizes first medium layer surface 2, the barrier effect on second dielectric layer surface 3 suppresses defect, utilizes undersized crystal growth plane 1 to reduce the defect concentration in semi-conducting material simultaneously.
As shown in Figure 3, above-mentioned substrate can also comprise the 4th dielectric layer surface 5 be positioned at above crystal growth plane 1, first medium layer surface 2, second dielectric layer surface 3, and described 4th dielectric layer surface 5 is relative with the 3rd dielectric layer surface 4.Described 4th dielectric layer surface 5 can limit the growth of crystal from another direction.
Described crystal growth plane 1 can be made up of a kind of monocrystalline, and namely whole crystal growth plane is all be made up of a kind of monocrystalline, also can be made up of with arbitrary proportion a single-crystal surface and one or more dielectric layer surface.
The size of single-crystal surface can affect the defect concentration of semi-conducting material at the extension initial stage, under normal circumstances, single-crystal surface is the smaller the better, and in the present invention, the span up and down of crystal growth plane and left and right span are all less than 100 μm, be preferably less than 1 μm, more preferably below 100nm.Span up and down in the application and left and right span can represent with external diameter of a circle, (dash area is crystal growth plane as shown in figure 16, outside circle is circumscribed circle), namely, the external diameter of a circle of crystal growth plane is less than 100 μm, preferably be less than 1 μm, be more preferably less than 100nm.
The orientation of single-crystal surface can affect the quality of semi-conducting material, different crystal orientations have different thermal coefficient of expansions and and symmetry, choose suitable crystal face and can improve the matching degree with grown semi-conducting material, thus lifting crystal mass, for extension GaN on Si, optimal Si crystal face is Si(111).
Adopt the semi-conducting material above-mentioned substrate can being prepared fabricating low-defect-density, growing method is selective growth, comprises MOCVD, HVPE, MBE etc.The material grown comprises Si, SiGe, Ge, GaN, GaAs, InP, AlN, AlGaN, AlGaAs etc.
The present invention is further illustrated below in conjunction with embodiment and Figure of description.The object of embodiment content is to illustrate thinking of the present invention further and provides a kind of feasible implementation method; it does not limit the present invention, and the structure that those skilled in the art do for basis with the embodiment in the present invention, method or adjustment are functionally all in protection scope of the present invention.
Embodiment 1:
As shown in Figure 4, a kind of micro-nano technology substrate, comprise first medium layer surface 2 and second dielectric layer surface 3 that crystal growth plane 1, two is positioned at crystal growth plane 1 both sides, crystal growth plane 1, first medium layer surface 2 and second dielectric layer surface 3 are all constructed on the 3rd dielectric layer surface 4.Crystal growth plane 1 is monocrystalline silicon (111) surface, and first medium layer surface 2, second dielectric layer surface 3 and the 3rd dielectric layer surface 4 are formed by silica.
In order to further describe substrat structure, position relationship particularly between crystal growth plane and the dielectric layer surface of its both sides, Fig. 5 is the substrate vertical view of the present embodiment, crystal growth plane and the dielectric layer surface being positioned at crystal growth plane both sides is only shown in figure, the dielectric layer surface be positioned at below it does not show, and figure comprises the first medium layer surface 2, the second dielectric layer surface 3 that are positioned at crystal growth plane both sides for crystal growth plane 1, two.Crystal growth plane 1 is made up of monocrystalline silicon, and first medium layer surface 2 and second dielectric layer surface 3 are formed by silica.
The above-mentioned substrate prepared is placed in MOCVD device, utilizes selective growth technique growing semiconductor material.Above-mentioned MOCVD temperature is 970-1050 degree Celsius, and pressure is 30-400 holder, and presoma used is: ammonia 1340-312500 micromole/minute, TMGa134-3100 micromole/minute.Can be used for growing high-quality GaN.
Embodiment 2:
As shown in Figure 6, a kind of micro-nano technology substrate, comprise first medium layer surface 2 and second dielectric layer surface 3 that crystal growth plane 1, two is positioned at crystal growth plane both sides, be positioned at crystal growth plane 1, first medium layer surface 2 and the 4th dielectric layer surface 5 relative with the 3rd dielectric layer surface 4 above second dielectric layer surface 3, crystal growth plane 1, first medium layer surface 2 and second dielectric layer surface 3 are all constructed on the 3rd dielectric layer surface 4.Crystal growth plane 1 is monocrystalline silicon surface, first medium layer surface 2, and second dielectric layer surface the 3, three dielectric layer surface 4 and the 4th dielectric layer surface 5 are formed by silica.The effect of the 4th dielectric layer surface 5 is the growth in an upward direction of restriction semi-conducting material, to promote the quality of semi-conducting material.
In order to further describe substrat structure, position relationship particularly between crystal growth plane and the dielectric layer surface of its both sides, Fig. 7 is the substrate vertical view of the present embodiment, crystal growth plane and the dielectric layer surface being positioned at crystal growth plane both sides is only shown in figure, the dielectric layer surface of the side of being located thereon and below does not show, and figure comprises the first medium layer surface 2 and the second dielectric layer surface 3 that are positioned at crystal growth plane 1 both sides for crystal growth plane 1, two.Crystal growth plane 1 is made up of monocrystalline silicon, and first medium layer surface 2 and second dielectric layer surface 3 are formed by silica.
The above-mentioned substrate prepared is placed in MOCVD device, utilizes selective growth technique growing semiconductor material.Above-mentioned MOCVD temperature is 970-1050 degree Celsius, and pressure is 30-400 holder, and presoma used is: ammonia 1340-312500 micromole/minute, TMGa134-3100 micromole/minute.Can be used for growing high-quality GaN.
Embodiment 3:
As shown in Figure 8, a kind of micro-nano technology substrate, comprise first medium layer surface 2 and second dielectric layer surface 3 that crystal growth plane 1, two is positioned at crystal growth plane both sides, crystal growth plane 1, first medium layer surface 2 and second dielectric layer surface 3 are all constructed on the 3rd dielectric layer surface 4.Crystal growth plane 1 is made up of single-crystal surface 11 and the 5th dielectric layer surface 12, and single-crystal surface is silicon (111).First medium layer surface 2, second dielectric layer surface 3, the 3rd dielectric layer surface 4, the 4th dielectric layer surface 5 and the 5th dielectric layer surface 12 are formed by silica.In the present embodiment, the formation of crystal growth plane is made up of two parts, single-crystal surface 11 and the 5th dielectric layer surface 12 respectively, in selective growth process, this aufwuchsplate be made up of multiple surface can't affect the growth of material, also little on the impact of fault in material density, only comprise a single-crystal surface as long as meet in aufwuchsplate.
In order to further describe substrat structure, position relationship particularly between crystal growth plane and the dielectric layer surface of its both sides, Fig. 9 is the substrate vertical view of the present embodiment, crystal growth plane and the dielectric layer surface being positioned at crystal growth plane both sides is only shown in figure, the dielectric layer surface be positioned at below it does not show, figure comprises for crystal growth plane 1, crystal growth plane 1 is made up of single-crystal surface 11 and the 5th dielectric layer surface 12, two first medium layer surfaces 2 and second dielectric layer surface 3 being positioned at crystal growth plane 1 both sides.First medium layer surface 2, second dielectric layer surface 3 and the 5th dielectric layer surface 12 are formed by silica.
The above-mentioned substrate prepared is placed in MOCVD device, utilizes selective growth technique growing semiconductor material.Above-mentioned MOCVD temperature is 970-1050 degree Celsius, and pressure is 30-400 holder, and presoma used is: ammonia 1340-312500 micromole/minute, TMGa134-3100 micromole/minute.Can be used for growing high-quality GaN.
Embodiment 4:
As shown in Figure 10, a kind of micro-nano technology substrate, comprise first medium layer surface 2 and second dielectric layer surface 3 that crystal growth plane 1, two is positioned at crystal growth plane both sides, be positioned at crystal growth plane 1, first medium layer surface 2 and the 4th dielectric layer surface 5 relative with the 3rd dielectric layer surface 4 above second dielectric layer surface 3, crystal growth plane 1, first medium layer surface 2 and second dielectric layer surface 3 are all constructed on the 3rd dielectric layer surface 4.Crystal growth plane 1 is made up of single-crystal surface 11 and the 5th dielectric layer surface 12, and single-crystal surface 11 is Si (111); First medium layer surface 2, second dielectric layer surface 3, the 3rd dielectric layer surface 4, the 4th dielectric layer surface 5 and the 5th dielectric layer surface 12 are formed by silica.
In order to further describe substrat structure, position relationship particularly between crystal growth plane and the dielectric layer surface of its both sides, Figure 11 is the substrate vertical view of the present embodiment, crystal growth plane and the dielectric layer surface being positioned at crystal growth plane both sides is only shown in figure, the dielectric layer surface of the side of being located thereon and below does not show, figure comprises for crystal growth plane 1, two first medium layer surfaces 2 and second dielectric layer surface 3 being positioned at crystal growth plane 1 both sides, wherein crystal growth plane 1 is made up of single-crystal surface 11 and the 5th dielectric layer surface 12, first medium layer surface 2, second dielectric layer surface 3 and the 5th dielectric layer surface 12 are formed by silica.
The above-mentioned substrate prepared is placed in MOCVD device, utilizes selective growth technique growing semiconductor material.Above-mentioned MOCVD temperature is 970-1050 degree Celsius, and pressure is 30-400 holder, and presoma used is: ammonia 1340-312500 micromole/minute, TMGa134-3100 micromole/minute.Can be used for growing high-quality GaN.
Embodiment 5:
As shown in figure 12, a kind of micro-nano technology substrate, comprise first medium layer surface 2 and second dielectric layer surface 3 that crystal growth plane 1, two is positioned at crystal growth plane both sides, crystal growth plane 1, first medium layer surface 2 and second dielectric layer surface 3 are all constructed on the 3rd dielectric layer surface 4.Crystal growth plane 1 is single-crystal surface, and concrete material is Si (111); First medium layer surface 2, second dielectric layer surface 3 and the 3rd dielectric layer surface 4 are formed by silica.
In order to further describe substrat structure, position relationship particularly between crystal growth plane and the dielectric layer surface of its both sides, Figure 13 is the substrate vertical view of the present embodiment, crystal growth plane and the dielectric layer surface being positioned at crystal growth plane both sides is only shown in figure, the dielectric layer surface be positioned at below it does not show, and figure comprises the first medium layer surface 2 and the second dielectric layer surface 3 that are positioned at crystal growth plane both sides for crystal growth plane 1, two.Crystal growth plane 1 is made up of monocrystalline silicon, and first medium layer surface 2 and second dielectric layer surface 3 are formed by silica.In the present embodiment, the first medium layer surface 2 of crystal growth plane 1 both sides and second dielectric layer surface 3 are irregular surface, different from the plane in embodiment 1, but above-mentioned concave plane is little to semi-conducting material growth effect, as long as meet in plan structure to external expansion.
The above-mentioned substrate prepared is placed in MOCVD device, utilizes selective growth technique growing semiconductor material.Above-mentioned MOCVD temperature is 970-1050 degree Celsius, and pressure is 30-400 holder, and presoma used is: ammonia 1340-312500 micromole/minute, TMGa134-3100 micromole/minute.Can be used for growing high-quality GaN.
Embodiment 6:
As shown in figure 14, a kind of micro-nano technology substrate, comprise first medium layer surface 2 and second dielectric layer surface 3 that crystal growth plane 1, two is positioned at crystal growth plane both sides, be positioned at crystal growth plane 1, first medium layer surface 2 and the 4th dielectric layer surface 5 relative with the 3rd dielectric layer surface 4 above second dielectric layer surface 3, crystal growth plane 1, first medium layer surface 2 and second dielectric layer surface 3 are all constructed on the 3rd dielectric layer surface 4.Crystal growth plane 1 is made up of single-crystal surface 11 and the 5th dielectric layer surface 12, and first medium layer surface the 2, the 3rd dielectric layer surface 3, the 3rd dielectric layer surface 4, the 4th dielectric layer surface 5 and the 5th dielectric layer surface 12 are formed by silica.
In order to further describe substrat structure, position relationship particularly between crystal growth plane and the dielectric layer surface of its both sides, Figure 15 is the substrate vertical view of the present embodiment, crystal growth plane and the dielectric layer surface being positioned at crystal growth plane both sides is only shown in figure, the dielectric layer surface of the side of being located thereon and below does not show, figure comprises for crystal growth plane 1, two first medium layer surfaces 2 and second dielectric layer surface 3 being positioned at crystal growth plane 1 both sides, wherein crystal growth plane 1 is made up of single-crystal surface 11 and the 5th dielectric layer surface 12, single-crystal surface 11 is Si (111), first medium layer surface 2, second dielectric layer surface 3 and the 5th dielectric layer surface 12 are formed by silica.In the present embodiment, the first medium layer surface 2 of crystal growth plane 1 both sides and second dielectric layer surface 3 are irregular surface, different from the plane in embodiment 4, but above-mentioned concave plane is little to semi-conducting material growth effect, as long as meet in plan structure to external expansion.
The above-mentioned substrate prepared is placed in MOCVD device, utilizes selective growth technique growing semiconductor material.Above-mentioned MOCVD temperature is 970-1050 degree Celsius, and pressure is 30-400 holder, and presoma used is: ammonia 1340-312500 micromole/minute, TMGa134-3100 micromole/minute.Can be used for growing high-quality GaN.
Above-mentioned 6 embodiments are all for extension GaN on Si, and in the substrate course of processing, soi wafer can be used to be initial processing, and SOI is a kind of substrate that can be mass-produced, and price is relatively low, use stand CMOS can obtain corresponding structure.In addition, in 6 embodiments, all select MOCVD as the method for selective growth, be because MOCVD is a kind of GaN growth technique of relative maturity, be used widely in industrial quarters, be suitable for very much preparing low cost GaN on a large scale.In 6 embodiments, MOCVD technique is all using hydrogen as presoma carrier gas, and when using hydrogen as carrier gas, the growth of GaN has sufficiently high selectivity to silica and monocrystalline silicon, therefore without the need to additionally using etching gas to increase selectivity.6 embodiments all can use HVPE to substitute MOCVD, and do not need to modify to substrate, and unique difference is may need in growth course to use etching gas to increase selectivity, prevents GaN growth on dielectric layer surface.For the substrat structure of embodiment 1, embodiment 3, embodiment 5, owing to not having dielectric layer end face, MBE also can be used as selective growth method.
Claims (10)
1. a Semiconductor substrate, it is characterized in that, described substrate comprises one and is positioned at the suprabasil crystal growth plane for semiconductor material growing of dielectric layer and is positioned at crystal growth plane both sides with two and the dielectric layer surface be connected with crystal growth plane, two dielectric layer surface, to external expansion, form funnel-shaped structure with crystal growth plane; Described crystal growth plane contains a single facet be made up of monocrystalline.
2. substrate according to claim 1, is characterized in that, described substrate can also comprise the dielectric layer surface that is positioned at the top of crystal growth plane and dielectric layer side, and described dielectric layer surface is relative with dielectric layer substrate.
3. substrate according to claim 1, is characterized in that, described crystal growth plane can also contain one or more dielectric layer surface.
4. substrate according to claim 1, is characterized in that, span up and down and the left and right span of described crystal growth plane are all less than 100 μm, is preferably less than 1 μm, more preferably below 100nm.
5. substrate according to claim 1, is characterized in that, described monocrystalline is selected from Si, SiGe, Ge, GaN, GaAs, InP, InN, AlGaAs, AlGaN, InPGaN etc.
6. the substrate according to claim 1,2 or 3, is characterized in that, described dielectric layer surface is by SiO
2, one or more in the material such as SiN or HfO form.
7. a method for selective growth semi-conducting material, is characterized in that, the method adopts substrate according to claim 1, realizes selective growth by technological means such as MOCVD, MBE, HVPE.
8. method according to claim 7, is characterized in that, the presoma used in described selective growth process can be TMGa, TEGa, NH
3, AsH
3, PH
3, SiH
4, GeH
4, SiH
2cl
2, TMAl or TBAs etc.
9. method according to claim 7, is characterized in that, described selective growth adopts etching gas, and described etching gas is Cl
2, HCl etc.
10. method according to claim 7, is characterized in that, the semi-conducting material that described selective growth method grows is Si, SiGe, Ge, GaN, GaAs, InP, InN, AlGaAs, AlGaN or InPGaN etc.
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