CN105137331B - A kind of integrated circuit test system digital channel signal alignment schemes and device - Google Patents
A kind of integrated circuit test system digital channel signal alignment schemes and device Download PDFInfo
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- CN105137331B CN105137331B CN201510442178.6A CN201510442178A CN105137331B CN 105137331 B CN105137331 B CN 105137331B CN 201510442178 A CN201510442178 A CN 201510442178A CN 105137331 B CN105137331 B CN 105137331B
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Abstract
The invention discloses a kind of integrated circuit test system digital channel signal alignment schemes and device, it is to be realized by a spring needle spy plate and time deviation compensator, the digital channel to be measured output of multiple integrated circuits, which is introduced to, to be visited on plate, and digital channel to be measured inputs a clock；The alignment schemes include determining digital channel output signal time deviation step and time deviation compensation output step to be measured；The present invention solves integrated circuit testing digital channel signal using minimum device and alignd, and compared with traditional test circuit, has test automation degree high, fault rate is few, overcomes the problem of distributed constant influences each other, easily controllable, and measurement accuracy is high.
Description
Technical field
The present invention relates to integrated circuit testing field, and in particular to a kind of integrated circuit test system digital channel signal pair
Neat method and device.
Background technology
Along with IC design and manufacturing development, integrated circuit test system is widely applied.
The links such as integrated circuit development, production and application will carry out repeated multiple times electricity ginseng with integrated circuit test system to it
Number test, so as to ensure the product quality of integrated circuit and reliability.And transmission delay in integrated circuit electric parameters testing, build
Between immediately, the measurement of the alternating-current parameter such as retention time, it is desirable to integrated circuit test system possesses good timing accuracy, i.e. system
Each digital channel output signal is alignd in time, and the measurement of above alternating-current parameter otherwise can be caused inaccurate.Ensure test system
System digital channel output signal align in time, it is necessary first to detect in system it is each numeral between multi-channel output signal it is initial
Time deviation, conventional method can directly be observed by oscillograph, be observed in this way initial between individual output signals up to a hundred
Time deviation, workload is big and is easily influenceed by human factor.Also a kind of method is with relay matrix that multiple numerals are logical
Road is switched to measuring unit and detected one by one, and this largely reduces workload and avoids human intervention, but this
Kind of method needs huge relay matrix, and cost is higher and need to take larger space, more seriously measuring unit simultaneously with
Multiple relays are connected, and are surveyed even if synchronization only has a relay closure to be sent into a certain railway digital multi-channel output signal
Unit is measured, other relays being connected in measuring unit, which also result in bigger distributed constant, influences measurement accuracy, meanwhile,
Also resulting in signal transmission path impedance discontinuity using relay influences signal integrity, also can influence time measurement accuracy.
The content of the invention
Present invention aims at a kind of integrated circuit test system digital channel signal alignment schemes and device is provided, can drop
The interference that the low artificial workload and human factor introduce, meanwhile, can avoid reflection in the signals transmission and
Measurement error caused by the otherness of transmission path, so as to improve measurement accuracy.
To achieve these goals, the solution of the present invention is：
A kind of integrated circuit test system digital channel signal alignment schemes, it is inclined by a spring needle spy plate and time
What poor compensator was realized, the digital channel to be measured output of multiple integrated circuits, which is introduced to, to be visited on plate, digital channel input one to be measured
Individual clock；The alignment schemes include determining digital channel output signal time deviation step and time deviation compensation output to be measured
Step；
It is described to determine that digital channel output signal time deviation step to be measured is：
The first step：Passage on the basis of any one digital channel to be measured is selected, the output of reference channel is coaxial with one
Cable guides to the input A of a time difference measuring apparatus, is connected using a mobile probe by another coaxial cable
In another input B of time difference measuring apparatus；
Second step：Mobile probe is moved into other numerals to be measured on spy plate one by one using a triaxial driving apparatus to lead to
Road output point, each digital channel output to be measured and reference channel output time offset are recorded, records digital channel to be measured
Numbering and corresponding output time offset；
The time deviation compensation, which exports step, is：
The first step：Using time offset less than fiducial time maximum offset point corresponding to digital channel as the time pair
Qi Dian, time offset of other digital channels relative to the time unifying point is calculated, further according to time deviation compensator
The delay time of minimum delay unit, which calculates other digital channels, to be needed by how many minimum delay units ability and time
Snap point aligns, and will calculate gained delay cell quantity and be stored in a memory；
Second step：Each digital channel output to be measured is connected to the input of time deviation compensator circuit, by the time
Final tested output of the output of deviation compensator circuit as digital channel to be measured；
3rd step：Time deviation compensator reads delay unit corresponding in memory first for digital channel to be measured
Quantity N, digital channel to be measured export after N number of minimum delay unit, realize and eliminate the digital channel output signal and time pair
The time offset put together, the like finally realize each digital channel time unifying.
Scheme is further：The time deviation compensator uses FPGA circuitry, and the FPGA circuitry contains realization
Circuit needed for delay.
Scheme is further：Two coaxial cables be impedance for 50 ohm, same model and equal length it is coaxial
Cable.
Scheme is further：The time difference measuring apparatus is by a phase-detection chip and the voltage measurement being attached thereto
Module forms, described to record digital channel to be measured output and the method for reference channel output time offset and be：Phase-detection core
The phase deviation of output is converted to DC voltage compared with piece exports each digital channel with reference channel, then by voltage measurement module
The measurement to DC voltage is completed, and is converted to corresponding time offset.
Scheme is further：The delay time of the minimum delay unit is the clock week of IODELAY modules inside FPGA
60 a quarters of phase.
A kind of integrated circuit test system digital channel signal alignment test device, including a spring needle visit plate, are visiting
Distribution is provided with digital channel exports test point to be measured on plate, and a triaxial coordinate transmission device drives a probe in the spy
Test point described in moving contact on plate, wherein, described device also includes time difference measurements device and time deviation compensator, when described
Between difference measurer have two inputs, respectively a reference channel input and a comparison path input, reference channel
Input connects a selected test point, compares path input and connects the probe, the output of time difference measurements device passes through
One processor Connection Time deviation compensator, delay circuit is provided with time deviation compensator, and the input of delay circuit connects
Original digital channel output to be measured is connect, the output of delay circuit is the final digital channel output to be measured of time unifying.
Scheme is further：The time difference measurements device is by a phase-detection chip and the voltage measurement mould being attached thereto
Block forms, and the phase-detection chip has two inputs, respectively described reference channel input and compares path input,
The phase deviation of output is converted to DC voltage compared with phase-detection chip exports each relatively passage with reference channel, then by electricity
Press measurement module to complete the measurement to DC voltage, and be converted to corresponding time offset；The time deviation compensator bag
Include a subtracter, impulse generator, counter and delay circuit, subtracter connects the processor, during by subtracter pair
Between 1 corresponding impulse generator of offset minus just produce a CLK pulse, then by counter CLK is carried out counting to get N, counted
The input of number device control delay circuit exports again after the delay of N number of delay unit, finally realizes that digital channel time unifying is defeated
Go out.
Scheme is further：The time deviation compensator uses FPGA circuitry.
Scheme is further：The test point is original digital channel output to be measured.
Scheme is further：The test point is final digital channel output to be measured.
The present invention solves integrated circuit testing digital channel signal using minimum device and alignd, with traditional test electricity
Road is compared, and has test automation degree high, and fault rate is few, overcomes the problem of distributed constant influences each other, easily controllable, surveys
Accuracy of measurement is high.
The present invention is described in detail with reference to the accompanying drawings and examples.
Brief description of the drawings
Fig. 1 illustrates for apparatus of the present invention frame structure；
Fig. 2 is time difference measuring apparatus circuit structure schematic block diagram of the present invention；
Fig. 3 is a kind of scenario-frame schematic block diagram of time deviation compensator circuit of the present invention；
Fig. 4 is time deviation compensator circuit another kind scenario-frame schematic block diagram of the present invention.
Embodiment
Embodiment 1：
A kind of integrated circuit test system digital channel signal alignment schemes, as shown in figure 1, being visited by a spring needle
What plate 1 and time deviation compensator 2 were realized, the digital channel to be measured output of multiple integrated circuits, which is introduced to, to be visited on plate, number to be measured
Word path input inputs a clock, and output end exports a clock therewith；Wherein, it is to be measured to include determination for the alignment schemes
Digital channel output signal time deviation step and time deviation compensation output step；
It is described to determine that digital channel output signal time deviation step to be measured is：
The first step：Any one digital channel test point to be measured is selected as reference channel on plate is visited, such as Fig. 1 and Fig. 2
It is shown, the output of reference channel is guided to the input A of a time difference measuring apparatus 4 with a coaxial wire 3, uses one
Individual mobile probe 5 is connected to another input B of time difference measuring apparatus by another coaxial cable 6, and setting benchmark leads to
Time on the basis of road output；
Second step：Mobile probe is moved to one by one using a triaxial driving apparatus 7 and visits other numerals to be measured on plate
Passage output point, each digital channel output to be measured and reference channel output time offset are recorded, is recorded in a processor 8
Digital channel numbering to be measured and corresponding output time offset；
The time deviation compensation, which exports step, is：
The first step：Using time offset less than fiducial time maximum offset point corresponding to digital channel as the time pair
Qi Dian, time offset of other digital channels relative to the time unifying point is calculated, further according to time deviation compensator
The delay time of minimum delay unit, which calculates other digital channels, to be needed by how many minimum delay units ability and time
Snap point aligns, and the memory that will calculate gained delay cell quantity deposit processor（FLASH）In；
Second step：Each digital channel to be measured output is connected to the input C of the circuit of time deviation compensator 2, by when
Between the output of deviation compensator circuit export D as the final tested of digital channel to be measured；
3rd step：Corresponding in memory prolong is read first for digital channel to be measured after electricity on time deviation compensator
Slow element number N,（Compensator is assigned to a subtracter 201 as initial value, and after subtracter is started working, subtracter is every
Subtract 1, corresponding impulse generator 202 just produces a CLK pulse, then by a counter 203 CLK is carried out counting to get N
Individual delay unit,）Time deviation compensator controls digital channel to be measured to be exported after N number of minimum delay unit, realizes to eliminate and is somebody's turn to do
Digital channel output signal and the time offset of time unifying point, the like, other digital channels can pass through the side
Method eliminates the time migration with time unifying point, finally realizes each digital channel time unifying.
In embodiment：The time deviation compensator can use the different model chip for having this function to realize delay work(
Can, the present embodiment preferably uses FPGA（Programmable logic device）Circuit, the FPGA circuitry contains to be compiled using FPGA circuitry
Volume realize the circuit needed for delay, example subtracter, impulse generator, counter etc. as mentioned.
In embodiment：Influenced each other to reduce distributed constant, two coaxial cables be impedance for 50 ohm, it is identical
The coaxial cable of model and length.
In embodiment：The time difference measuring apparatus is by a phase-detection chip（That its model is selected is AD8302）With
The accurate voltage measurement module composition being attached thereto, it is described to record digital channel output to be measured and the skew of reference channel output time
The method of amount is：The phase deviation of output is converted to direct current compared with phase-detection chip exports each digital channel with reference channel
Voltage, then the measurement to DC voltage is completed by voltage measurement module, and be converted to corresponding time offset.
In embodiment：The delay time of the minimum delay unit is IODELAY inside FPGA（IO is delayed）Module when
60 a quarters in clock cycle, are 80PS.
Embodiment 2：
A kind of integrated circuit test system digital channel signal alignment test device for realizing the methods described of embodiment 1, such as
Shown in Fig. 1,2,3,4, including a spring needle visits plate 1, is distributed on plate is visited and is provided with digital channel exports test point to be measured, and one
Individual triaxial coordinate transmission device drives a probe test point described in moving contact, described device time difference on the spy plate to survey
Measuring device and time deviation compensator, the time difference measurements device have two inputs, a respectively reference channel input and
One comparison path input, reference channel input connect a selected original digital channel output C to be measured, compare passage
Input connects the probe, and the output of time difference measurements device is inclined by a processor Connection Time deviation compensator, time
Delay circuit is provided with poor compensator, the input of delay circuit connects the test point as digital channel to be measured output, delay
The output of circuit is the final digital channel output D to be measured of time unifying, and the present embodiment and the difference of embodiment 1 are in figure
C is original digital channel output to be measured, and D is final digital channel output to be measured.Therefore, there are two kinds of testing scheme knots in test
Structure：
The first testing scheme structure is：The test point is original digital channel output to be measured, under this configuration, first
The measurement of time difference measurements device is first carried out, the result of measurement is sent into processor and calculated, by time offset less than fiducial time
Digital channel corresponding to maximum offset point calculates other digital channels relative to the time unifying point as time unifying point
Time offset, calculate other digital channels further according to the delay time of the minimum delay unit of time deviation compensator and need
To pass through how many minimum delay units could align with time unifying point, and will calculate the deposit processing of gained delay cell quantity
In the memory of device；Then, data in memory are set into Time Compensator, Time Compensator is to original digital channel to be measured
Signal carries out the final digital channel signal of output time alignment after time bias.
Second of testing scheme structure be：As shown in figure 4, the test point is final digital channel output to be measured, this knot
Structure is that time deviation compensator string has been connected between original digital channel output to be measured and test point；Under this configuration, together
Sample carries out the measurement of time difference measurements device first, during test, is delayed and is arranged to " 0 " in time deviation compensator（It is namely of no help
Repay）, the result deposit processor of measurement calculates, by time offset less than numeral corresponding to the maximum offset point of fiducial time
Passage calculates time offset of other digital channels relative to the time unifying point as time unifying point, further according to when
Between the delay time of minimum delay unit of deviation compensator calculate other digital channels and need by how many minimum delays
Unit could align with time unifying point, and by the memory for calculating gained delay cell quantity deposit processor；Then, will
Gained delay cell quantity sets angle of incidence deviation compensator, the test point now can output time alignment final numeral
Channel signal.
In embodiment：The time deviation compensating unit includes a time difference measurements device and time deviation compensator, institute
Time difference measurements device is stated by a phase-detection chip（That its model is selected is AD8302）401 and the voltage measurement that is attached thereto
Module 402 forms, and the phase-detection chip has two inputs, two inputs be respectively the reference channel input and
Compare path input, the phase deviation of output is converted to compared with phase-detection chip exports each relatively passage with reference channel
DC voltage, then the measurement to DC voltage is completed by voltage measurement module, and be converted to corresponding time offset；When described
Between deviation compensator include a subtracter, impulse generator, counter and delay circuit, subtracter connects the processor,
Subtracting 1 to time offset by subtracter, corresponding impulse generator just produces a CLK pulse, then CLK is entered by counter
Row counts to get N, and the input of counter controls delay circuit exports again after the delay of N number of delay unit, final to realize numeral
Channel time alignment output.
In embodiment：The time deviation compensator preferably uses FPGA circuitry.
The following describe the motion process of triaxial coordinate transmission device：
Triaxial coordinate transmission device, time difference measuring apparatus in the present apparatus are all fixed on PCB pins and visited on plate, choose first
First digit channel C H1 is as reference channel in system, and thinks spring pin hole corresponding to CH1 for X, the coordinate reference of Y-axis
Zero point（0,0）, before and after, probe can return to dead-center position for measurement, by second coaxial cable 3 by first
Individual digital channel C H1 output signal is connected to the input A of time measurement device, then the first coaxial electrical that will be connected with probe
Cable 6 is connected to the input B of time measurement device.
Triaxial coordinate transmission device in the present apparatus is made up of three groups of mechanical devices in X-axis, Y-axis and Z-direction arrangement.
The mechanical device includes a controllor for step-by-step motor and driver, an a stepper motor and roller screw.Three groups of machines
Tool device together constitutes the program-controlled mechanical device of three coordinates.Controllor for step-by-step motor and driver Driving Stepping Motor, stepping
Motor is connected by shaft coupling with ball-screw, and roller screw changes into the rotational displacement of stepper motor in X, Y, Z respectively
Linear displacement on three directions of axle.Probe loading attachment is fixed on Z axis ball-screw by feed screw nut, therefore probe can be with
Moved by Z axis ball-screw is lower in the Z-axis direction, while Z axis ball screw can be by X-axis and Y-axis ball-screw in X-axis
Moved horizontally with Y direction, so as to which probe can flexibly moves in X-axis, Y-axis and Z axis on three directions.
Motion control device part in described device have selected the roller screw of model 1204, i.e. every turn of stepper motor
360 ° of linear displacements that can change into roller screw 4mm on X, Y, Z axis direction are moved, then by setting stepper motor driver pair
The pulse signal of input carries out 4 frequency dividings, then each pulse signal can only Driving Stepping Motor rotate 0.25 °, drive ball-screw
Produce about 0.0028mm linear displacement.Spring needle visits the spacing between spring pin hole corresponding to digital channel to be measured on plate
2.54mm, then need 907 pulse signal Driving Stepping Motors to rotate 226.75 °, produce 2.5396mm's in X or Y direction
Displacement, positioning precision can reach 0.1%.
The probe is from plating Au probe, to reduce the contact resistance of probe and gold plating spring pin hole on spring needle spy plate；
Exported and believed as digital channel from the first coaxial cable and the second coaxial cable that two isometric characteristic impedances are 50 ohm
Number transmission cable, can not only ensure that two digital multi-channel output signals pass through isometric transmission path measurements of arrival time list
Member, and the requirement of the ohms impedance match of time measuring unit input 50 has been better met, while can also effectively reduce
Reflection in signals transmission.
Realize that digital channel signal aligns in time in system, it is necessary first to measure between each digital channel signal
Time offset, time bias is carried out to each digital channel further according to the time offset.The second digit from system below
Channel C H2 starts to measure, it is known that CH2 coordinate is X=0.0mm, Y=2.54mm, then we need to make probe from dead-center position to Y
The positive mobile 2.54mm of axle, software send two control signals to y-axis stepper motor driver, and a control signal is lasting
High level, stepper motor rotation direction is represented, another control signal is continuous 907 pulse signals, Driving Stepping Motor
226.75 ° are rotated, so that probe reaches coordinate X=0.0mm, Y=2.54mm, software is again to Z to the positive mobile 2.54mm of Y-axis
Shaft step motor driver sends corresponding control signal, and control probe moves down 10mm in Z-direction, and probe is properly inserted
Spring pin hole.
Now digital channel CH1 and CH2 output signal passes through first coaxial cable and the second coaxial cable respectively
It is connected to two inputs of time measurement device.As shown in Fig. 2 time measuring unit uses directional coupler ADC-20-4+
By input phase detection chip after CH1 and CH2 signal attenuation, phase-detection chip selects AD8302, and it is by CH1's and CH2
Time deviation is converted to DC voltage amount.The DC voltage is measured by the accurate voltage measuring circuit again, software passes through one
The DC voltage is converted to time offset and preserved by fixed algorithm.
After completing measurement, software control probe is lifted up 10mm in Z-direction, and continues positive mobile to Y-axis
2.54mm, is moved to coordinates of targets X=0.0mm, Y=5.08mm, and probe is inserted into spring pin hole and starts to measure.By that analogy, directly
This, which is moved to, to probe arranges last digital channel to be measured, coordinate is X=0.0mm, Y=48.26mm, and completes to measure,
Control probe to lift again, and to the positive mobile 2.54mm of X-axis, reach coordinate X=2.54mm, Y=48.26mm, probe insertion spring
Pin hole starts to measure, and measurement controls probe to move 2.54mm to Y-axis negative sense again after terminating, reach coordinate X=2.54mm, Y=
45.72mm, probe push and start measurement.The like, each digital channel to be measured is measured successively, you can is obtained successively in system
The relative time offset with CH1 of each digital channel signal.
Claims (8)
1. a kind of integrated circuit test system digital channel signal alignment schemes, it is that plate and time deviation are visited by a spring needle
What compensator was realized, the digital channel to be measured output of multiple integrated circuits, which is introduced to, to be visited on plate, and digital channel to be measured exports one
Clock；Characterized in that, the alignment schemes include determining that digital channel output signal time deviation step to be measured and time are inclined
Difference compensation output step；
It is described to determine that digital channel output signal time deviation step to be measured is：
The first step：Passage on the basis of any one digital channel to be measured is selected, by the output of reference channel with a coaxial cable
The input A of a time difference measuring apparatus is guided to, when being connected to using a mobile probe by another coaxial cable
Between difference measuring device another input B；
Second step：Using a triaxial driving apparatus by mobile probe one by one be moved to visit plate on other digital channels to be measured it is defeated
Go out a little, record each digital channel output to be measured and reference channel output time offset, record digital channel numbering to be measured
With corresponding output time offset；
The time deviation compensation, which exports step, is：
The first step：Using time offset less than fiducial time maximum offset point corresponding to digital channel as time unifying
Point, time offset of other digital channels relative to the time unifying point is calculated, further according to time deviation compensator most
The delay time of small delay unit calculates that other digital channels need could be with the time pair by how many minimum delay units
Neat point alignment, and gained delay cell quantity will be calculated and be stored in a memory；
Second step：Each digital channel output to be measured is connected to the input of time deviation compensator circuit, by time deviation
Final tested output of the output of compensator circuit as digital channel to be measured；
3rd step：Time deviation compensator reads delay unit quantity corresponding in memory first for digital channel to be measured
N, digital channel to be measured export after N number of minimum delay unit, realize and eliminate the digital channel output signal and time unifying point
Time offset, the like finally realize each digital channel time unifying.
2. according to the method for claim 1, it is characterised in that the time deviation compensator uses FPGA circuitry,
The FPGA circuitry contains the circuit realized needed for delay.
3. according to the method for claim 1, it is characterised in that two coaxial cables be impedance for 50 ohm, it is identical
The coaxial cable of model and equal length.
4. according to the method for claim 1, it is characterised in that the time difference measuring apparatus is by a phase-detection chip
It is described to record digital channel output to be measured and reference channel output time offset with the voltage measurement module composition being attached thereto
Method be：The phase deviation of output is converted to direct current compared with phase-detection chip exports each digital channel with reference channel
Pressure, then the measurement to DC voltage is completed by voltage measurement module, and be converted to corresponding time offset.
5. according to the method for claim 2, it is characterised in that the delay time of the minimum delay unit is inside FPGA
60 a quarters of the clock cycle of IODELAY modules.
The test device 6. a kind of integrated circuit test system digital channel signal aligns, including a spring needle visit plate, are visiting plate
Upper distribution is provided with test point, and a triaxial coordinate transmission device drives the survey described in moving contact on the spy plate of a probe
Pilot, it is characterised in that described device also includes time difference measurements device and time deviation compensator, and the time difference measurements device has
Two inputs, respectively a reference channel input and a comparison path input, reference channel input connection one
Individual selected test point, compare path input and connect the probe, the output of time difference measurements device is connected by a processor
Time deviation compensator is connect, delay circuit is provided with time deviation compensator, the input of delay circuit connects original number to be measured
Word passage exports, and the output of delay circuit is the final digital channel output to be measured of time unifying.
7. alignment test device according to claim 6, it is characterised in that the time difference measurements device is examined by a phase
Chip and the voltage measurement module being attached thereto composition are surveyed, the phase-detection chip has two inputs, respectively described base
Quasi- path input compares output compared with passage exports with reference channel with path input, phase-detection chip is compared by each
Phase deviation is converted to DC voltage, then completes the measurement to DC voltage by voltage measurement module, and when being converted to corresponding
Between offset；The time deviation compensator includes subtracter, impulse generator, counter and delay circuit, subtracter connection
The processor, subtracting 1 to time offset by subtracter, corresponding impulse generator just produces a CLK pulse, then by counting
Number device carries out counting to get N to CLK, and the input of counter controls delay circuit exports again after the delay of N number of delay unit, most
Realize that digital channel time unifying exports eventually.
8. alignment test device according to claim 7, it is characterised in that the time deviation compensator uses
FPGA circuitry.
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| CN106896309B (en) * | 2015-12-17 | 2019-08-06 | 上海和辉光电有限公司 | Signal processing apparatus and method, signal offset detection system and method |
| CN113779778B (en) * | 2021-08-24 | 2024-04-05 | 中国舰船研究设计中心 | Ship system task channel test point optimization method |
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| US5974057A (en) * | 1997-09-30 | 1999-10-26 | Motorola, Inc. | Method and apparatus for correcting a measured round-trip delay time in a wireless communication system |
| CN1402444A (en) * | 2001-08-23 | 2003-03-12 | 三星电子株式会社 | Method for sending data and compensating propagation delay in point-to-point communication network |
| CN101515831A (en) * | 2008-02-22 | 2009-08-26 | 杭州华三通信技术有限公司 | Method, system and device for time synchronous transfer |
| CN102468898A (en) * | 2010-11-19 | 2012-05-23 | 中兴通讯股份有限公司 | Method, equipment and system for achieving time synchronization in time division multiplexing network |
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| US7595629B2 (en) * | 2004-07-09 | 2009-09-29 | Formfactor, Inc. | Method and apparatus for calibrating and/or deskewing communications channels |
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| US5974057A (en) * | 1997-09-30 | 1999-10-26 | Motorola, Inc. | Method and apparatus for correcting a measured round-trip delay time in a wireless communication system |
| CN1272268A (en) * | 1997-09-30 | 2000-11-01 | 摩托罗拉公司 | Method and apparatus for correcting measured round-trip delay time in wireless communication system |
| CN1402444A (en) * | 2001-08-23 | 2003-03-12 | 三星电子株式会社 | Method for sending data and compensating propagation delay in point-to-point communication network |
| CN101515831A (en) * | 2008-02-22 | 2009-08-26 | 杭州华三通信技术有限公司 | Method, system and device for time synchronous transfer |
| CN102468898A (en) * | 2010-11-19 | 2012-05-23 | 中兴通讯股份有限公司 | Method, equipment and system for achieving time synchronization in time division multiplexing network |
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