CN105117358B - A kind of DMA data transfer method and device - Google Patents
A kind of DMA data transfer method and device Download PDFInfo
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- CN105117358B CN105117358B CN201510508011.5A CN201510508011A CN105117358B CN 105117358 B CN105117358 B CN 105117358B CN 201510508011 A CN201510508011 A CN 201510508011A CN 105117358 B CN105117358 B CN 105117358B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0024—Peripheral component interconnect [PCI]
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Abstract
The embodiment of the invention discloses a kind of DMA data transfer method and devices, the time for solving traditional mono- frames of DMA takes the summation for being taken with DDR reading image data and sending image data with PCI E and take equal to reading chained list, caused by DMA poor efficiency, the technical issues of directly affecting the frame per second of video.DMA data transfer method of the embodiment of the present invention includes：The linked list data read from DDR is cached to preset linked list data buffer area and will read from DDR, and the video data carried out by preset alignment thereof after registration process is cached to preset video data buffer area；When preset linked list data buffer area is non-null states and preset video data buffer area meets a burst transfer condition, then video data is sent to the TX ends of PCI E according to preset mode.
Description
Technical field
The present invention relates to technical field of data processing more particularly to a kind of DMA data transfer method and devices.
Background technology
PCI-E (PCI Express) is bus interface of new generation, is usually connected with data collecting card, DMA (Direct
Memory Access, direct memory access) data copy to another address space by transmission from an address space.When
CPU initializes this transmission action, and transmission action is carried out and completed by dma controller in itself.Typical example is exactly to move
The block of an external memory is moved to the faster memory field of chip internal.Seem that such operation does not allow processor work to be dragged
Prolong, can be gone to handle other work instead by scheduling again.DMA transfer is for high-effect embedded system algorithm and network
Critically important.
In the existing processor capture card based on PCI-E, the DMA for employing linked list type carries out the biography of video data
Defeated, video data is handled by frame, i.e., a DMA is opened, and is completed a frame data and is terminated for DMA.
Traditional DMA processes, usually first read linked list data, image pixel origin coordinates further according to linked list data,
DMA length and destination address carry out data address registration process in DDR, then read video data, finally by video data transmitting
Send and treat TX ends, therefore, whole process since DMA unlatching after timing, from DDR read chained list take, then further according to linked list data
It is taken again from DDR reading images specific data, TX is finally sent to until host memory takes again according to linked list data.And these
It is cumulative again to take, and reads chained list and take to take with DDR reading image data and PCI-E so that the time of mono- frames of DMA is equal to
The technical issues of sending the summation that image data takes, and resulting in the poor efficiency of DMA, directly affect the frame per second of video.
The content of the invention
An embodiment of the present invention provides a kind of DMA data transfer method and device, solves the time of traditional mono- frames of DMA
Equal to reading chained list and take to take with DDR reading image data to send the summation that takes of image data with PCI-E, caused by DMA
Poor efficiency, the technical issues of directly affecting the frame per second of video.
A kind of DMA data transfer method provided in an embodiment of the present invention, including：
The linked list data read from DDR is cached to preset linked list data buffer area and will read from the DDR
, and cached by the video data after preset alignment thereof progress registration process to preset video data buffer area；
When the preset linked list data buffer area meets once for non-null states and the preset video data buffer area
During burst transfer condition, then the video data is sent to the TX ends of PCI-E according to preset mode.
Preferably, the linked list data read from DDR is cached to preset linked list data buffer area and will be from described
It is read in DDR, and is cached to preset video data and cached by the video data after preset alignment thereof progress registration process
It is further included before area：
Get the DMA open commands so that the DMA, which is opened, carries out next frame and chained list selection.
Preferably, the linked list data read from DDR is cached to preset linked list data buffer area and will be from described
It is read in DDR, and is cached to preset video data and cached by the video data after preset alignment thereof progress registration process
It is further included before area：
The linked list data read from the DDR is stored in the first linked list data memory block and will be from the DDR
The video data of middle reading is stored in the first video data storage region；
Judge whether the first linked list data memory block and first video data storage region are in non-null states,
If so, corresponding coordinate, DMA length and destination address are read according to the first linked list data memory block；
The data address registration process of video data is carried out according to the preset alignment thereof；
Wherein, the preset alignment thereof be according to the coordinate of reading, the DMA length and the destination address into
The registration process of the row video data.
Preferably, the linked list data read from DDR is cached to preset linked list data buffer area and will be from described
It is read in DDR, and is cached to preset video data and cached by the video data after preset alignment thereof progress registration process
Area specifically includes：
The linked list data read from the first linked list data memory block is cached to the preset linked list data and is delayed
Deposit area；
And it will be delayed by the video data after the preset alignment thereof progress data address registration process
It deposits to the preset video data buffer area.
Preferably, when the preset linked list data buffer area is non-null states and the preset video data buffer area
When meeting a burst transfer condition, then the video data is sent to the TX ends of PCI-E according to preset mode and specifically included：
When the preset linked list data buffer area meets for the non-null states and the preset video data buffer area
During burst transfer condition, then the linked list data is read from the preset linked list data buffer area；
The coordinate, the DMA length in the linked list data carry out the data address registration process；
The video data is read out from the preset video data buffer area according to the destination address, and is sent
To the TX ends of the PCI-E.
A kind of DMA data transfer device provided in an embodiment of the present invention, including：
Buffer unit, for caching the linked list data read from DDR to preset linked list data buffer area and will be from
It reads in the DDR, and is cached by the video data after preset alignment thereof progress registration process to preset video data
Buffer area；
Transmitting element, for working as the preset linked list data buffer area for non-null states and the preset video data
When buffer area meets a burst transfer condition, then the video data is sent to the TX ends of PCI-E according to preset mode.
Preferably, the DMA data transfer device further includes：
Command acquisition unit, for getting the DMA open commands so that the DMA, which is opened, carries out next frame and chain
Table selects.
Preferably, the DMA data transfer device further includes：
First reading unit, the linked list data for will be read from the DDR are stored in the storage of the first linked list data
Area and by the video data read from the DDR be stored in the first video data storage region；
Second reading unit, for judging that the first linked list data memory block and first video data storage region be
It is no to be in non-null states, if so, reading corresponding coordinate, DMA length and mesh according to the first linked list data memory block
Address；
Registration process unit, for carrying out the data address registration process of video data according to the preset alignment thereof；
Wherein, the preset alignment thereof be according to the coordinate of reading, the DMA length and the destination address into
The registration process of the row video data.
Preferably, buffer unit specifically includes：
Linked list data caches subelement, for the linked list data read from the first linked list data memory block to be delayed
It deposits to the preset linked list data buffer area；
Video data caches subelement, for that will carry out the data address registration process by the preset alignment thereof
The video data afterwards is cached to the preset video data buffer area.
Preferably, transmitting element specifically includes：
Subelement is read, for working as the preset linked list data buffer area for the non-null states and described preset regarding
When frequency data buffer area meets a burst transfer condition, then the chain is read from the preset linked list data buffer area
Table data；
Align subelement, in the linked list data the coordinate, the DMA length with carrying out the data
Location registration process；
Transmission sub-unit, for according to the destination address by the video data from the preset video data buffer area
In read out, and be sent to the TX ends of the PCI-E.
As can be seen from the above technical solutions, the embodiment of the present invention has the following advantages：
A kind of DMA data transfer method and device provided in an embodiment of the present invention, wherein, DMA data transfer method includes：
The linked list data read from DDR is cached to preset linked list data buffer area and will read from DDR, and is passed through pre-
The video data after alignment thereof progress registration process is put to cache to preset video data buffer area；When preset linked list data caches
When area is non-null states and a preset video data buffer area burst transfer condition of satisfaction, then it will be regarded according to preset mode
Frequency is according to the TX ends for being sent to PCI-E.In the present embodiment, by being cached to linked list data to preset linked list data buffer area, with
And the video data that will be carried out by preset alignment thereof after registration process is cached to preset video data buffer area and then incited somebody to action
Video data, which is sent, to the TX ends of PCI-E, just realizes conventional reading linked list data process, reading video data process and hair
Send parallel processing of the video data to the process at TX ends so that the time of mono- frames of DMA is taken for reading chained list or reading image data consumption
When or PCI-E send image data take in maximum take effect, so as to which the time for solving traditional mono- frames of DMA is equal to
Read chained list and take to take with DDR reading image data to send the summation that takes of image data with PCI-E, caused by DMA it is poorly efficient
Rate, the technical issues of directly affecting the frame per second of video.
Description of the drawings
It in order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention, for those of ordinary skill in the art, without having to pay creative labor, may be used also
To obtain other attached drawings according to these attached drawings.
Fig. 1 is a kind of flow diagram of one embodiment of DMA data transfer method provided in an embodiment of the present invention；
Fig. 2 is a kind of flow diagram of another embodiment of DMA data transfer method provided in an embodiment of the present invention；
Fig. 3 is a kind of structure diagram of one embodiment of DMA data transfer device provided in an embodiment of the present invention；
Fig. 4 is a kind of structure diagram of another embodiment of DMA data transfer device provided in an embodiment of the present invention.
Specific embodiment
An embodiment of the present invention provides a kind of DMA data transfer method and device, solves the time of traditional mono- frames of DMA
Equal to reading chained list and take to take with DDR reading image data to send the summation that takes of image data with PCI-E, caused by DMA
Poor efficiency, the technical issues of directly affecting the frame per second of video.
Goal of the invention, feature, advantage to enable the present invention is more apparent and understandable, below in conjunction with the present invention
Attached drawing in embodiment is clearly and completely described the technical solution in the embodiment of the present invention, it is clear that disclosed below
Embodiment be only part of the embodiment of the present invention, and not all embodiment.Based on the embodiments of the present invention, this field
All other embodiment that those of ordinary skill is obtained without making creative work, belongs to protection of the present invention
Scope.
Referring to Fig. 1, a kind of one embodiment of DMA data transfer method provided in an embodiment of the present invention includes：
101st, the linked list data read from DDR is cached to preset linked list data buffer area and will read from DDR
, and cached by the video data after preset alignment thereof progress registration process to preset video data buffer area；
When need the processor capture card based on PCI-E using linked list type DMA carry out video data transmission when, it is necessary to
The linked list data read from DDR is cached to preset linked list data buffer area and will read from DDR, and is passed through pre-
The video data after alignment thereof progress registration process is put to cache to preset video data buffer area.
102nd, when preset linked list data buffer area meets a secondary burst for non-null states and preset video data buffer area
During transmission conditions, then video data is sent to the TX ends of PCI-E according to preset mode.
When the linked list data read from DDR cached to preset linked list data buffer area and is read from DDR,
And the video data that will be carried out by preset alignment thereof after registration process cache to after preset video data buffer area, it is necessary to
When preset linked list data buffer area is non-null states and preset video data buffer area meets a burst transfer condition,
Then video data is sent to the TX ends of PCI-E according to preset mode.
It should be noted that condition of the foregoing burst transfer condition for a conveying length, i.e. Burst burst length
Degree, burst (Burst) refer to the week that storage unit adjacent in the same row is carried out continuously the mode of data transmission, continuously transmits
Issue is exactly burst-length (Burst Lengths, abbreviation BL), and Burst burst-lengths are known to the skilled person technology,
Details are not described herein again.
In the present embodiment, by being cached to linked list data to preset linked list data buffer area and will be by preset alignment
Mode carry out the video data after registration process cache to preset video data buffer area and then by video data send to
The TX ends of PCI-E just realize conventional reading linked list data process, reading video data process and send video data to TX
The parallel processing of the process at end so that the time of mono- frames of DMA, chained list took or reading image data take or PCI-E transmission figures to read
The time-consuming effect of maximum in being taken as data is equal to so as to solve the time of traditional mono- frames of DMA and reads chained list and take and DDR
Reading image data take sends the summation that takes of image data with PCI-E, caused by DMA poor efficiency, directly affect and regard
The technical issues of frame per second of frequency.
The above is the description of the process progress to DMA data transfer method, below by the chained list number to will be read from DDR
It will be read according to caching to preset linked list data buffer area and from DDR, and pass through preset alignment thereof and carry out registration process
Video data afterwards is cached to the detailed process of preset video data buffer area and is described in detail, referring to Fig. 2, of the invention
A kind of another embodiment for DMA data transfer method that embodiment provides includes：
201st, DMA open commands are got so that DMA, which is opened, carries out next frame and chained list selection；
When the processor capture card based on PCI-E is needed to carry out the transmission of video data using the DMA of linked list type, first
It needing to get DMA open commands so that DMA, which is opened, carries out next frame and chained list selection, such as DMA is enabled, and DMA is opened, under
The selection of one frame, chained list selection.
202nd, the linked list data read from DDR is stored in the first linked list data memory block and will be read from DDR
Video data is stored in the first video data storage region；
When getting DMA open commands so that DMA, which is opened, to carry out after next frame and chained list selection, it is necessary to will be from DDR
The linked list data of reading is stored in the first linked list data memory block and the video data read from DDR is stored in the first video
Data storage area.
Such as linked list data deposit FIFO_LIST0 is read, it is read from FIFO_LIST0, does chained list verification, mainly table
Head, list item and length error, detection pixel origin coordinates (x, y), DMA length and destination address, and video counts are read from DDR
According to deposit FIFO_DATA0.
203rd, judge whether the first linked list data memory block and the first video data storage region are in non-null states, if
It is then to perform step 204 and step 206；
It is regarded when by the linked list data read from DDR the first linked list data memory block of deposit and by what is read from DDR
Frequency is according to the first video data storage region of deposit afterwards, it is necessary to judge that the first linked list data memory block and the first video data store
Whether area is in non-null states, if so, performing step 204 and step 206, such as judges FIFO_LIST0 and FIFO_
Whether DATA0 meets non-empty condition.
204th, corresponding coordinate, DMA length and destination address are read according to the first linked list data memory block；
When judging whether the first linked list data memory block and the first video data storage region are in non-null states to be,
Corresponding coordinate, DMA length and destination address are then read according to the first linked list data memory block, such as read according to FIFO_LIST0
Coordinate (x, y), DMA length and the destination address gone out.
205th, the data address registration process of video data is carried out according to preset alignment thereof；
, it is necessary to press while corresponding coordinate, DMA length and destination address is read according to the first linked list data memory block
The data address registration process of video data is carried out according to preset alignment thereof.
Preset alignment thereof is that the registration process of video data is carried out according to the coordinate of reading, DMA length and destination address.
Such as coordinate (x, y), DMA length and the destination address read according to FIFO_LIST0 is carried out in FIFO_DATA0
Video data address is alignd.
206th, the linked list data read from the first linked list data memory block is cached to preset linked list data buffer area；
When judging whether the first linked list data memory block and the first video data storage region are in non-null states to be,
It then needs to cache the linked list data read from the first linked list data memory block to preset linked list data buffer area.
Such as the linked list data deposit FIFO_LIST1 that FIFO_LIST0 is read.
207th, will be cached by the video data after preset alignment thereof progress data address registration process to preset video
Data buffer area；
It, it is necessary to will be logical after step 205 carries out the data address registration process of video data according to preset alignment thereof
The video data crossed after preset alignment thereof progress data address registration process is cached to preset video data buffer area.
And FIFO_DATA1 is stored according to obtained required video data.
208th, when preset linked list data buffer area meets a secondary burst for non-null states and preset video data buffer area
During transmission conditions, then linked list data is read from preset linked list data buffer area；
Step 206 and 207 after, it is necessary to when preset linked list data buffer area be non-null states and preset video
When data buffer area meets a burst transfer condition, then linked list data is read from preset linked list data buffer area, such as when
When FIFO_LIST1 meets non-empty condition and FIFO_DATA1 satisfactions enough burst transfer conditions, then read from FIFO_LIST1
Go out chained list.
It should be noted that condition of the foregoing burst transfer condition for a conveying length, i.e. Burst burst length
Degree, burst (Burst) refer to the week that storage unit adjacent in the same row is carried out continuously the mode of data transmission, continuously transmits
Issue is exactly burst-length (Burst Lengths, abbreviation BL), and Burst burst-lengths are known to the skilled person technology,
Details are not described herein again.
209th, the coordinate in linked list data, DMA length carry out data address registration process；
When preset linked list data buffer area meets a burst transfer for non-null states and preset video data buffer area
During condition, and read from preset linked list data buffer area after linked list data, it is necessary to coordinate, DMA in linked list data
Length carries out data address registration process, such as carries out data address alignment according to coordinate (x, y), DMA length.
210th, video data is read out from preset video data buffer area according to destination address, and is sent to PCI-E
TX ends.
When in linked list data coordinate, DMA length carry out data address registration process while or after, according to mesh
Address video data is read out from preset video data buffer area, and be sent to the TX ends of PCI-E, such as according to purpose
Address reads video data from FIFO_DATA1, is sent toward TX ends.
In the present embodiment, by being cached to linked list data to preset linked list data buffer area and will be by preset alignment
Mode carry out the video data after registration process cache to preset video data buffer area and then by video data send to
The TX ends of PCI-E just realize conventional reading linked list data process, reading video data process and send video data to TX
The parallel processing of the process at end so that the time of mono- frames of DMA, chained list took or reading image data take or PCI-E transmission figures to read
The time-consuming effect of maximum in being taken as data is equal to so as to solve the time of traditional mono- frames of DMA and reads chained list and take and DDR
Reading image data take sends the summation that takes of image data with PCI-E, caused by DMA poor efficiency, directly affect and regard
The technical issues of frame per second of frequency and, linked list data is cached to preset linked list data buffer area and video data and is cached to pre-
It puts video data buffer area to handle simultaneously, further improves the high efficiency of caching process process.
Referring to Fig. 3, a kind of one embodiment of the DMA data transfer device provided in the embodiment of the present invention includes：
Buffer unit 301, for caching the linked list data read from DDR to preset linked list data buffer area and
It will be cached from DDR, and by the video data after preset alignment thereof progress registration process to preset video data buffer area；
Transmitting element 302, for working as preset linked list data buffer area for non-null states and preset video data buffer area
When meeting a burst transfer condition, then video data is sent to the TX ends of PCI-E according to preset mode.
In the present embodiment, linked list data is cached by buffer unit 301 to preset linked list data buffer area and will led to
The video data crossed after preset alignment thereof progress registration process is cached to preset video data buffer area, transmitting element
Video data is sent to the TX ends of PCI-E, just realize conventional reading linked list data process, reading video data again by 302
Process and the parallel processing of transmission video data to the process at TX ends so that the time of mono- frames of DMA takes or interprets blueprints to read chained list
As data take or PCI-E send image data take in maximum take effect, so as to solve traditional mono- frames of DMA
Time is equal to reading chained list and takes the summation for being taken with DDR reading image data and sending image data with PCI-E and take, caused by
The poor efficiency of DMA, the technical issues of directly affecting the frame per second of video.
The above is that each unit of DMA data transfer device is described in detail, below will be to extra cell and son
Unit is described in detail, referring to Fig. 4, another of a kind of DMA data transfer device provided in the embodiment of the present invention
Embodiment includes：
Command acquisition unit 401, for getting DMA open commands so that DMA, which is opened, carries out next frame and chained list choosing
It selects.
First reading unit 402, for the linked list data read from DDR to be stored in the first linked list data memory block, with
And the video data read from DDR is stored in the first video data storage region；
Second reading unit 403, for judging whether the first linked list data memory block and the first video data storage region are equal
In non-null states, if so, reading corresponding coordinate, DMA length and destination address according to the first linked list data memory block；
Registration process unit 404, for carrying out the data address registration process of video data according to preset alignment thereof；
Wherein, preset alignment thereof is that the alignment of video data is carried out according to the coordinate of reading, DMA length and destination address
Processing.
Buffer unit 405, for caching the linked list data read from DDR to preset linked list data buffer area and
It will be cached by the video data after preset alignment thereof progress registration process to preset video data buffer area；
Further, buffer unit 405 specifically includes：
Linked list data cache subelement 4051, for by the linked list data read from the first linked list data memory block cache to
Preset linked list data buffer area；
Video data caches subelement 4052, for it will carry out data address registration process by preset alignment thereof after
Video data is cached to preset video data buffer area.
Transmitting element 406, for working as preset linked list data buffer area for non-null states and preset video data buffer area
When meeting a burst transfer condition, then video data is sent to the TX ends of PCI-E according to preset mode.
Further, transmitting element 406 specifically includes：
Subelement 4061 is read, is delayed for working as preset linked list data buffer area for non-null states and preset video data
When depositing area's burst transfer condition of satisfaction, then linked list data is read from preset linked list data buffer area；
Align subelement 4062, in linked list data coordinate, DMA length carry out data address registration process；
Transmission sub-unit 4063, for being read video data from preset video data buffer area according to destination address
Go out, and be sent to the TX ends of PCI-E.
In the present embodiment, linked list data is cached by buffer unit 405 to preset linked list data buffer area and will led to
The video data crossed after preset alignment thereof progress registration process is cached to preset video data buffer area, transmitting element
Video data is sent to the TX ends of PCI-E, just realize conventional reading linked list data process, reading video data again by 406
Process and the parallel processing of transmission video data to the process at TX ends so that the time of mono- frames of DMA takes or interprets blueprints to read chained list
As data take or PCI-E send image data take in maximum take effect, so as to solve traditional mono- frames of DMA
Time is equal to reading chained list and takes the summation for being taken with DDR reading image data and sending image data with PCI-E and take, caused by
The poor efficiency of DMA, the technical issues of directly affecting the frame per second of video and, linked list data caches subelement 4051 by chained list
Data buffer storage to preset linked list data buffer area and video data caching 4052 video data of subelement is cached to preset video counts
It is handled simultaneously according to buffer area, further improves the high efficiency of caching process process.
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description,
The specific work process of device and unit may be referred to the corresponding process in preceding method embodiment, and details are not described herein.
In several embodiments provided herein, it should be understood that disclosed system, apparatus and method can be with
It realizes by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the unit
Division is only a kind of division of logic function, can there is other dividing mode, such as multiple units or component in actual implementation
It may be combined or can be integrated into another system or some features can be ignored or does not perform.It is another, it is shown or
The mutual coupling, direct-coupling or communication connection discussed can be the indirect coupling by some interfaces, device or unit
It closes or communicates to connect, can be electrical, machinery or other forms.
The unit illustrated as separating component may or may not be physically separate, be shown as unit
The component shown may or may not be physical location, you can be located at a place or can also be distributed to multiple
In network element.Some or all of unit therein can be selected to realize the mesh of this embodiment scheme according to the actual needs
's.
In addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, it can also
That unit is individually physically present, can also two or more units integrate in a unit.Above-mentioned integrated list
The form that hardware had both may be employed in member is realized, can also be realized in the form of SFU software functional unit.
If the integrated unit is realized in the form of SFU software functional unit and is independent production marketing or use
When, it can be stored in a computer read/write memory medium.Based on such understanding, technical scheme is substantially
The part to contribute in other words to the prior art or all or part of the technical solution can be in the form of software products
It embodies, which is stored in a storage medium, is used including some instructions so that a computer
Equipment (can be personal computer, server or the network equipment etc.) performs the complete of each embodiment the method for the present invention
Portion or part steps.And foregoing storage medium includes：USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only
Memory), random access memory (RAM, Random Access Memory), magnetic disc or CD etc. are various can store journey
The medium of sequence code.
The above, the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although with reference to before
Embodiment is stated the present invention is described in detail, it will be understood by those of ordinary skill in the art that：It still can be to preceding
The technical solution recorded in each embodiment is stated to modify or carry out equivalent substitution to which part technical characteristic；And these
Modification is replaced, and the essence of appropriate technical solution is not made to depart from the spirit and scope of various embodiments of the present invention technical solution.
Claims (8)
- A kind of 1. DMA data transfer method, which is characterized in that including：The linked list data read from DDR is stored in the first linked list data memory block and the video that will be read from the DDR Data are stored in the first video data storage region；Judge whether the first linked list data memory block and first video data storage region are in non-null states, if It is that corresponding coordinate, DMA length and destination address are then read according to the first linked list data memory block；The data address registration process of video data is carried out according to preset alignment thereof；Wherein, the preset alignment thereof carries out institute for the coordinate, the DMA length and the destination address according to reading State the registration process of video data；The linked list data read from the DDR is cached to preset linked list data buffer area and will be from the DDR It reads, and is cached to preset video data and cached by the video data after the preset alignment thereof progress registration process Area；When the preset linked list data buffer area meets a secondary burst for non-null states and the preset video data buffer area During transmission conditions, then the video data is sent to the TX ends of PCI-E according to preset mode.
- 2. DMA data transfer method according to claim 1, which is characterized in that the chain that will be read from the DDR Table data buffer storage is to preset linked list data buffer area and will be read from the DDR, and is carried out by preset alignment thereof Video data after registration process further includes before caching to preset video data buffer area：Get DMA open commands so that DMA, which is opened, carries out next frame and chained list selection.
- 3. DMA data transfer method according to claim 2, which is characterized in that delay the linked list data read from DDR It deposits to preset linked list data buffer area and specifically includes：The linked list data read from the first linked list data memory block is cached to the preset linked list data buffer area.
- 4. DMA data transfer method according to claim 3, which is characterized in that when the preset linked list data buffer area It, then will according to preset mode when meeting a burst transfer condition for non-null states and the preset video data buffer area The video data sends to the TX ends of PCI-E and specifically includes：When the preset linked list data buffer area is described in the non-null states and the preset video data buffer area satisfaction During burst transfer condition, then the linked list data is read from the preset linked list data buffer area；The coordinate, the DMA length in the linked list data carry out the data address registration process；The video data is read out from the preset video data buffer area according to the destination address, and is sent to institute State the TX ends of PCI-E.
- 5. a kind of DMA data transfer device, which is characterized in that including：First reading unit, for the linked list data read from DDR to be stored in the first linked list data memory block and will be from institute It states the video data read in DDR and is stored in the first video data storage region；Second reading unit, for judging whether the first linked list data memory block and first video data storage region are equal In non-null states, if so, reading corresponding coordinate, DMA length and destination according to the first linked list data memory block Location；Registration process unit, for carrying out the data address registration process of video data according to preset alignment thereof；Wherein, the preset alignment thereof carries out institute for the coordinate, the DMA length and the destination address according to reading State the registration process of video data；Buffer unit, for caching the linked list data read from the DDR to preset linked list data buffer area and It is cached by what is read from the DDR, and by the video data after the preset alignment thereof progress registration process to preset Video data buffer area；Transmitting element, for working as the preset linked list data buffer area for non-null states and the preset video data caching When area meets a burst transfer condition, then the video data is sent to the TX ends of PCI-E according to preset mode.
- 6. DMA data transfer device according to claim 5, which is characterized in that the DMA data transfer device also wraps It includes：Command acquisition unit, for getting DMA open commands so that DMA, which is opened, carries out next frame and chained list selection.
- 7. DMA data transfer device according to claim 6, which is characterized in that buffer unit specifically includes：Linked list data cache subelement, for by the linked list data read from the first linked list data memory block cache to The preset linked list data buffer area.
- 8. DMA data transfer device according to claim 7, which is characterized in that transmitting element specifically includes：Subelement is read, for working as the preset linked list data buffer area for the non-null states and the preset video counts When meeting a burst transfer condition according to buffer area, then the chained list number is read from the preset linked list data buffer area According to；Align subelement, in the linked list data the coordinate, the DMA length carry out the data address pair Neat processing；Transmission sub-unit, for being read the video data from the preset video data buffer area according to the destination address It takes out, and is sent to the TX ends of the PCI-E.
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| EP0803819A2 (en) * | 1996-04-26 | 1997-10-29 | Texas Instruments Incorporated | Method of assigning a data packet to a channel in a IEEE 1394 communications system |
| CN104123250A (en) * | 2013-04-25 | 2014-10-29 | 上海联影医疗科技有限公司 | Data transmission method based on DMA |
| CN104184542A (en) * | 2013-05-23 | 2014-12-03 | 重庆重邮信科通信技术有限公司 | Uplink control method, system and terminal |
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| EP0803819A2 (en) * | 1996-04-26 | 1997-10-29 | Texas Instruments Incorporated | Method of assigning a data packet to a channel in a IEEE 1394 communications system |
| CN104123250A (en) * | 2013-04-25 | 2014-10-29 | 上海联影医疗科技有限公司 | Data transmission method based on DMA |
| CN104184542A (en) * | 2013-05-23 | 2014-12-03 | 重庆重邮信科通信技术有限公司 | Uplink control method, system and terminal |
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