CN105116314B - A kind of thyristor protection detection trigger method - Google Patents

A kind of thyristor protection detection trigger method Download PDF

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Publication number
CN105116314B
CN105116314B CN201510377161.7A CN201510377161A CN105116314B CN 105116314 B CN105116314 B CN 105116314B CN 201510377161 A CN201510377161 A CN 201510377161A CN 105116314 B CN105116314 B CN 105116314B
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pulse
thyristor
trigger
detection
window
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CN105116314A (en
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刘争艳
罗海云
刘轲
王小强
任小静
胡鑫明
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China XD Electric Co Ltd
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China XD Electric Co Ltd
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Abstract

The present invention discloses a kind of thyristor protection detection trigger method, pass through the time interval before judgement control pulse CP between the last one forward voltage marker pulse IP and CP, if greater than certain time, a thyristor protection detection trigger window is generated in trigger pulse FP failing edges, if receiving thyristor return signal in this window, it is determined that thyristor protection triggers, otherwise, thyristor protection detection trigger window is not generated then, the thyristor return signal received is judged as forward voltage marker pulse, it efficiently solves recurrent in Practical Project, it is too small in trigger angle, IP it is discrete it is excessive in the case of thyristor protection trigger protection malfunction the problem of, by the inspection and comparison of Practical Project, it proves highly effective.

Description

A kind of thyristor protection detection trigger method
【Technical field】
The present invention relates to DC transmission system field more particularly to a kind of thyristor protection detection trigger methods.
【Background technology】
One of the phenomenon that thyristor protection triggering is common in DC transmission system, it directly affects DC power transmission system The stability of system, therefore, thyristor protection detection trigger method are very important.
When thyristor both end voltage is more than certain value, thyristor control unit TCU sends out forward voltage marker pulse IP Monitoring device is controlled to valve, shows that thyristor has been set up forward voltage, can be switched at any time, controls what is sent when receiving pole When controlling pulse CP, valve control monitoring device sends triggering command FP triggering thyristors to TCU immediately, and thyristor is made to start to lead It is logical, if thyristor could not be triggered normally by FP, the thyristor both end voltage will be caused anxious since other thyristors are begun to turn on Play raising, when reaching positive protectiveness triggering level, for the thyristor is protected not damaged by overvoltage, TCU sends out positive protection Property trigger pulse PF by the IGBT group, while beam back the number of notifying to valve control monitoring device, valve control monitoring device according to This return signal does the fault detect of thyristor.
Valve controls monitoring device, if receiving the signal of TCU feedbacks, to be determined as in a period of time after FP failing edges Thyristor protection triggers.If in a change of current valve arm, when thyristor protection shot number reaches certain amount, valve control Monitoring device processed can send out tripping request, and cancel the ready signal of this system immediately.Pole control system is detecting the ready letter Number disappear after, can immediately activation system switch.If another system also differentiates thyristor protection, triggering is out-of-limit, can also remove The ready signal of this system is sold, pole control system starts direct-current emergency stoppage in transit when detecting that two systems are not ready.
But with the difference of the straight-flow system method of operation, the relationship between IP and CP is not always ideal, IP signals The feedback moment be can be discrete.The dispersion degree of IP signals has very big relationship with the method for operation of converter valve.Under FP Edge is dropped, to turn on thyristors, in this gap, if due to the discreteness of IP, can still there are IP signals to return there are one gap Report, detection method routinely will be judged as thyristor protection triggering, cause malfunction.Malfunction number reaches certain journey When spending, system alarm or tripping are will result in, seriously affects the stable operation of system.
【Invention content】
Present invention aims at a kind of thyristor protection detection trigger method is provided, it is brilliant to solve existing DC transmission system The problem of easily there is malfunction, influences transmission system stable operation in brake tube protectiveness triggering method.
A kind of thyristor protection detection trigger method, protection system include thyristor control unit TCU, valve control monitoring Equipment, signal rising edge and failing edge detection module, forward voltage marker pulse IP with control pulse CP interval calculations module and Timer module;
When generating thyristor protection detection trigger window, by between forward voltage marker pulse IP and control pulse CP The distance between the last one forward voltage marker pulse IP and control pulse CP before computing module calculates control pulse CP;
If more than setting time, thyristor protection detection trigger window is generated in trigger pulse FP failing edges, in this window The valve return signal determining received in mouthful is positive protectiveness trigger pulse PF;Trigger pulse FP and thyristor protection triggering inspection Window pulse width is surveyed to calculate using timer module;
Otherwise thyristor protection detection trigger window is not generated, and the thyristor return signal determining received is forward voltage Marker pulse IP.
Further, the signal rising edge and failing edge detection module realize signal rising edge using the method for clapping delay is beaten With the detection of failing edge.
Further, timer module uses the trigger FDCE enabled in FPGA with asynchronous reset and clock and counter mould Block is realized.
Further, it based on FPGA, is realized using Verilog HDL language.
The thyristor protection detection trigger method of the present invention, the last one is positive before controlling pulse CP arrivals by judgement If greater than certain time, one is generated in trigger pulse FP failing edges for time interval between voltage marker pulse IP and CP Thyristor protection detection trigger window, if thyristor return signal is received, it is determined that thyristor is protected in this window The triggering of shield property, otherwise, does not then generate thyristor protection detection trigger window, and the thyristor return signal received is judged as just To voltage marker pulse, by detecting the time interval before CP between the last one forward voltage marker pulse IP and CP, if Interval is more than certain time, can just generate thyristor protection detection trigger window, avoids excessive just receiving back because IP is discrete The number of notifying causes protectiveness to trigger malfunction, influences system worked well.By the inspection and comparison of Practical Project, it was demonstrated that very Effectively, it ensure that the reliable and stable operation of system.
【Description of the drawings】
Fig. 1 is the sequence diagram of the present invention
The realization block diagram of Fig. 2 present invention
【Specific embodiment】
Embodiments of the present invention are further described below in conjunction with attached drawing.
As depicted in figs. 1 and 2, the present invention is in direct-current transmission valve control monitoring device (VCM, also known as valve base electronic device) A kind of detection method of completely new converter valve thyristor protectiveness triggering is devised, first determines whether the last one before control pulse CP Time interval between forward voltage marker pulse IP and CP, if greater than certain time, which is set by the user, and is triggering Pulse FP failing edges generate a thyristor protection detection trigger window, if receiving thyristor return letter in this window Number, it is determined that thyristor protection triggers, otherwise, then thyristor protection detection trigger window is not generated, the brilliant lock received Pipe return signal is judged as forward voltage marker pulse.
Trigger angle is too small, IP it is discrete it is excessive in the case of, by detecting the last one forward voltage indicator vein before CP The time interval between IP and CP is rushed, if interval is more than certain time, can just generate thyristor protection detection trigger window, Avoid because IP it is discrete it is excessive just receive return signal, cause protectiveness trigger malfunction, influence system worked well.
The problem of thyristor protection trigger protection malfunction, by the inspection and comparison of Practical Project, it was demonstrated that highly effective.
The present invention is based on FPGA, are realized using Veriog HDL language.
Signal rising edge, failing edge detection mode are realized by the way of bat delay is played.
Timer is realized by the trigger FDCE and counter module that are enabled in FPGA with asynchronous reset and clock.
FDCE interfaces are as follows:
Counter module interface is as follows:
Wherein:COUNT_WIDTH and COUNT_NUM determines the width of timer, in the rising edge of start by set date condition C When, set output data Q, counter starts counting up, and when the value of counter is COUNT_NUM, one flag bit CLR is to Q for output It is zeroed out, Q is the pulse of timer output, when the width and start by set date condition that need to change timer, only needs to change COUNT_WIDTH, COUNT_NUM and C.
IP is realized with CP interval calculations module
Workflow is as follows:
Detect CP failing edges, reseting register;
After detecting CP failing edges, whether the forward voltage indicator register for detecting corresponding change of current valve arm is high, if it is height, Next step is performed, if being not height, is continued waiting for until CP rising edges;
Start counter, if being received again by IP in CP low levels section, counter O reset restarts counter;
Third step is repeated, until CP rising edges arrive;
When CP rising edges arrive, meter reading is judged, if the time interval before CP between the last one IP and CP More than certain time, otherwise set register, is failure to actuate.

Claims (4)

  1. A kind of 1. thyristor protection detection trigger method, it is characterised in that:Protection system include thyristor control unit TCU, Valve control monitoring device, signal rising edge and failing edge detection module, forward voltage marker pulse IP and control pulse CP intervals Computing module and timer module;
    When generating thyristor protection detection trigger window, first, pass through forward voltage marker pulse IP and control pulse CP Interval calculation module calculates the distance between the last one forward voltage marker pulse IP and control pulse CP before control pulse CP;
    Then, judge if more than setting time, thyristor protection detection trigger window is generated in trigger pulse FP failing edges, The valve return signal determining received in this window is positive protectiveness trigger pulse PF;Trigger pulse FP and thyristor protection touch Detection window pulse width is sent out to calculate using timer module;
    Otherwise thyristor protection detection trigger window is not generated, and the thyristor return signal determining received is indicated for forward voltage Pulse IP.
  2. 2. detection method according to claim 1, it is characterised in that:The signal rising edge and failing edge detection module are adopted With the detection for beating the method for clapping delay realization signal rising edge and failing edge.
  3. 3. detection method according to claim 1, it is characterised in that:Timer module use FPGA in band asynchronous reset and The trigger FDCE and counter module that clock enables are realized.
  4. 4. according to claim 1-3 any one of them detection methods, it is characterised in that:Based on FPGA, using Verilog HDL Language is realized.
CN201510377161.7A 2015-06-30 2015-06-30 A kind of thyristor protection detection trigger method Active CN105116314B (en)

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Publication number Priority date Publication date Assignee Title
CN110954799A (en) * 2018-09-26 2020-04-03 国网江苏省电力有限公司南京供电分公司 TBS valve bank thyristor level online state detection method in UPFC
CN111208366B (en) * 2020-01-09 2022-03-29 南京南瑞继保电气有限公司 Method for judging electrification of high-voltage valve bank

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Publication number Priority date Publication date Assignee Title
CN101710159A (en) * 2009-12-04 2010-05-19 中国电力科学研究院 Novel direct-current converter valve test unit
CN102035188A (en) * 2010-09-14 2011-04-27 中国电力科学研究院 Novel thyristor overvoltage protection method
CN103149484A (en) * 2013-03-01 2013-06-12 南京南瑞继保电气有限公司 Detection method for current converter trigger control device function
CN103592544A (en) * 2013-11-21 2014-02-19 中国第一汽车股份有限公司 Feedback signal collecting method of power equipment by adopting thyristor as power switch

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8339272B2 (en) * 2009-08-07 2012-12-25 Fluke Corporation Circuit breaker locator

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101710159A (en) * 2009-12-04 2010-05-19 中国电力科学研究院 Novel direct-current converter valve test unit
CN102035188A (en) * 2010-09-14 2011-04-27 中国电力科学研究院 Novel thyristor overvoltage protection method
CN103149484A (en) * 2013-03-01 2013-06-12 南京南瑞继保电气有限公司 Detection method for current converter trigger control device function
CN103592544A (en) * 2013-11-21 2014-02-19 中国第一汽车股份有限公司 Feedback signal collecting method of power equipment by adopting thyristor as power switch

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