CN105097684B - A kind of manufacturing method of semiconductor devices - Google Patents
A kind of manufacturing method of semiconductor devices Download PDFInfo
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- CN105097684B CN105097684B CN201410163931.3A CN201410163931A CN105097684B CN 105097684 B CN105097684 B CN 105097684B CN 201410163931 A CN201410163931 A CN 201410163931A CN 105097684 B CN105097684 B CN 105097684B
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Abstract
The present invention provides a kind of manufacturing method of semiconductor devices, is related to technical field of semiconductors.The manufacturing method of the semiconductor devices of the present invention, by after the step of stress closes on technical finesse is carried out, increase the step of removal is formed in the protrusion of the first side wall apical lateral, clearance filling capability can be improved, ensure the normal sedimentation of interlayer dielectric layer, so as to improve the yield of entire semiconductor devices.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of manufacturing method of semiconductor devices.
Background technology
In technical field of semiconductors, for advanced technology, since the space between adjacent grid is smaller, in forming layer
Between dielectric layer (ILD) when gap filling become very difficult, therefore, generally require carry out stress close on technology (SPT) processing
To improve the surplus of space stuffing techniques.Improving channel stress in addition, stress closes on technology and improving carrier mobility side
Face also plays an important role.
When progress stress closes on technology (SPT) processing, wet etching and dry etching may be utilized, wherein, wet method
SPT is widely adopted due to small to metal silicide (NiSi) loss.During wet method SPT, based on to wall films
Different demands, side wall silicon nitride (SiN) can be removed completely or partially.Normally, side wall is removed completely is conducive to layer
Between dielectric layer gap filling and MMOS stress improve；But for high-k/metal gate technology, to protect titanium nitride
(TiN) and protection offset side wall is to avoid there is the problem of metal gates raised (protrusion), needs to retain a part
Major side wall.It, can be wet using the major side wall of sull and the silicon nitride film positioned at outside including being located inside
The part removal of major side wall is realized after method SPT (oxide skin(coating) is retained).Usual nitrogen oxides shielding layer side wall (PSR
Spacer) it is unfavorable for the growth of germanium silicon, therefore, shielding layer side wall (PSR spacer) is usually using nitridation as offset side wall
Silicon, and wet method SPT is then widely used in high k with nitrogen oxides major side wall (that is, major side wall includes oxide skin(coating) and silicon nitride layer)
To realize the reservation of part major side wall in metal gate technique.But since the isotropic etching of wet method SPT is by major side wall
Oxide skin(coating) stopped, anisotropic etching will be become in vertical direction to the wet etching of shielding layer side wall (silicon nitride),
Therefore, apparent protrusion (overhang) will be formed since etching is uneven in the apical lateral of shielding layer side wall, and this will
The filling capacity of interlayer dielectric layer is caused to be deteriorated.Even if using high-aspect-ratio (HARP) fill process, in interlevel dielectric deposition
Later, it still can be formed in interlayer dielectric layer empty (void).These cavities will influence subsequent interlayer dielectric layer CMP, puppet
Grid removes the techniques such as the formation with contact hole, and the yield for eventually leading to semiconductor devices declines.
It can be seen that in the manufacturing method of existing semiconductor devices, close on technology (SPT) in wet method stress and handle it
Afterwards, the apical lateral of shielding layer side wall is readily formed protrusion (overhang), and the gap that this will influence interlayer dielectric layer
Filling capacity, the yield for eventually leading to semiconductor devices decline.Therefore, it is to solve problem above, it is necessary to propose a kind of new
The manufacturing method of semiconductor devices.
Invention content
In view of the deficiencies of the prior art, the present invention provides a kind of manufacturing method of semiconductor devices, including：
Step S101：Semiconductor substrate is provided, formation includes dummy grid on the semiconductor substrate and dummy grid is covered firmly
The dummy gate structure of film, and form the first side wall in the both sides of the dummy gate structure；
Step S102：Second sidewall is formed in the outside of the first side wall, wherein, the second sidewall includes being located at interior
The oxide skin(coating) of side and the silicon nitride layer positioned at outside；
Step S103：It carries out stress and closes on technical finesse, wherein, close on technical finesse, the puppet grid by the stress
Extremely hard mask is removed with the silicon nitride layer in the second sidewall, and the first side wall apical lateral formed it is prominent
Go out object；
Step S104：Removal is formed in the protrusion of the apical lateral of the first side wall；
Step S105：Interlayer dielectric layer is formed on the semiconductor substrate.
Optionally, in the step S104, the method for removing the protrusion includes SiCoNi etchings or dry etching.
Optionally, in the step S104, the method that the dry etching uses includes the dry method of low bias low-power
It etches (soft etch).
In the step S104, the advantage of the SiCoNi is while protrusion is removed to the metal of source-drain area
The loss of silicide (nisiloy) is smaller.
Optionally, in the step S103, the stress closes on technical finesse and closes on technical finesse for wet method stress.
Optionally, in the step S103, etching liquid includes phosphorus used by the wet method stress closes on technical finesse
Acid.
Optionally, in the step S104, the SiCoNi etchings include original position SiCoNi etchings or ex situ
SiCoNi is etched.
Optionally, in the step S105, the method for forming the interlayer dielectric layer is sedimentation, and the sedimentation makes
Equipment with having the function of SiCoNi etchings in situ, can be before depositing operation be carried out using described in original position SiCoNi etching removals
Protrusion.
Optionally, in the step S105, the method for forming the interlayer dielectric layer is high-aspect-ratio completion method.
Optionally, step S1045 is further included between the step S104 and step S105：Form contact hole etching blocking
Layer.
Optionally, in the step S101, the material of the first side wall includes silicon nitride.
Optionally, in the rapid S101, the first side wall includes offset side wall and/or germanium silicon shielding layer side wall.
The manufacturing method of the semiconductor devices of the present invention, by after the step of stress closes on technical finesse is carried out, increasing
The step of removal is added to be formed in the protrusion of the first side wall apical lateral, can improve clearance filling capability, ensure interlayer dielectric
The normal sedimentation of layer, so as to improve the yield of entire semiconductor devices.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Figure 1A to Fig. 1 F is showing for the structure that the correlation step of the manufacturing method of semiconductor devices proposed by the present invention is formed
Meaning property sectional view；
Fig. 2 is a kind of flow chart of the manufacturing method of semiconductor devices proposed by the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.Disclosure will be made thoroughly and complete, and will fully convey the scope of the invention on the contrary, providing these embodiments
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or during layer, then there is no elements or layer between two parties.It should be understood that although it can make
Various elements, component, area, floor and/or part are described with term first, second, third, etc., these elements, component, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish an element, component, area, floor or part with it is another
One element, component, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and be used so as to describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention, which further includes, to be made
With the different orientation with the device in operation.For example, if the device overturning in attached drawing, then, is described as " under other elements
Face " or " under it " or " under it " elements or features will be oriented to other elements or features " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
Number, step, operation, the presence of element and/or component, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, component and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
It describes to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the variation of shown shape.Therefore,
The embodiment of the present invention should not necessarily be limited to the specific shape in area shown here, but including due to for example manufacturing caused shape
Shape deviation.For example, it is shown as the injection region of rectangle usually has circle at its edge or bending features and/or implantation concentration ladder
Degree rather than the binary from injection region to non-injection regions change.Equally, the disposal area can be led to by injecting the disposal area formed
Some injections in area between the surface passed through during injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical scheme of the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiment.
In the following, the manufacturing method one that semiconductor devices proposed by the present invention is described with reference to Figure 1A to Fig. 1 F and Fig. 2 is shown
The detailed step of example property method.Wherein, Figure 1A to Fig. 1 F shows the phase of the manufacturing method of semiconductor devices proposed by the present invention
The schematic cross sectional views for the structure that step is formed are closed, Fig. 2 is a kind of flow chart of the manufacturing method of semiconductor devices of the present invention.
Step A1：Semiconductor substrate 100 is provided, is formed in the Semiconductor substrate 100 and includes what is be laminated from bottom to top
Boundary layer (IL) 101, high k dielectric layer 101102, the dummy gate structure of dummy grid 103 and the hard mask 104 of dummy grid；Then, exist
The both sides of the dummy gate structure form the first side wall 105, as shown in Figure 1A.
Wherein, the dummy gate structure includes the dummy gate structure of NMOS and the dummy gate structure of PMOS, as shown in Figure 1A.
Certainly, the semiconductor devices of the present embodiment can also only include NMOS or PMOS, not be defined herein.
Wherein, the material of high k dielectric layer 102 can be hafnium oxide (HfO2) or other suitable materials.Boundary layer (IL)
101 material can be oxide or other suitable materials.The material of dummy grid 103 is generally polysilicon or amorphous silicon.
The material of the hard mask 104 of dummy grid is generally silicon nitride (SiN).
In the present embodiment, the first side wall 105 can be offset side wall (offset spacer), can be that germanium silicon covers
Layer side wall (PSR spacer), or offset side wall and the germanium silicon shielding layer side wall (abbreviation positioned at outside positioned inside
Shielding layer side wall) structure that collectively forms.The material of the first side wall 105 can be silicon nitride or other suitable materials.
When the first side wall 105 is offset side wall (offset spacer), in this step, after offset side wall is formed,
LDD processing can also be carried out to Semiconductor substrate 100.When the first side wall 105 is germanium silicon shielding layer side wall, hidden forming germanium silicon
After covering layer side wall, the step of can also including forming germanium silicon layer.
Illustratively, Semiconductor substrate 100 selects monocrystalline substrate.It can also include shallow ridges in the Semiconductor substrate 100
The structures such as slot isolation, well region, are not defined herein.
Step A2：Second sidewall 106 is formed in the outside of the first side wall 105, wherein, second sidewall 106 includes being located at interior
The oxide skin(coating) 1061 of side and the silicon nitride layer 1062 positioned at outside, as shown in Figure 1B.
Illustratively, second sidewall 106 can be major side wall.Wherein, using the oxide skin(coating) 1061 including being located inside
With the second sidewall 106 of the silicon nitride layer 1062 positioned at outside, effect is：Oxide skin(coating) 1061 positioned inside can be
The first side wall 105 on its inside is protected in SPT techniques, and high k dielectric layer can be protected.
Step A3：It carries out wet method stress and closes on technology (SPT) processing, wherein, the hard mask 104 of dummy grid and second sidewall
Silicon nitride layer 1062 in 106 is removed in SPT processing procedures, also, after wet method SPT processing, meeting is first
The apical lateral of side wall 105 forms protrusion (overhang) 1056, as shown in Figure 1 C.
Wherein, protrusion 1056 by the oxide skin(coating) 1061 in the first side wall 105 and second sidewall 106 tip portion
It is formed in wet method SPT processing procedures, main material includes silicon nitride and oxide (silica).
Since the isotropic etching of wet method SPT is stopped by the oxide skin(coating) 1061 in second sidewall 106, in SPT processing
The wet etching of the first side wall 105 will be become in vertical direction (referring to perpendicular to the direction of the upper surface of Semiconductor substrate 100)
Anisotropic etching therefore, because etching is uneven, will cause the apical lateral in the first side wall 105 to form protrusion
(overhang) 1056, as shown in Figure 1 C.Wherein, ridge 1056 is mainly by the oxygen in the first side wall 105 and second sidewall 106
The tip portion of compound layer 1061 is etched to define.Conventionally, as the apical lateral in the first side wall 105 forms
Protrusion (overhang) 1056, ridge 1056 can stop carries out gap filling, therefore often lead to space below
The clearance filling capability of interlayer dielectric layer is deteriorated；In general, even if interlayer dielectric is carried out using high-aspect-ratio (HARP) fill process
The deposition of layer, still can be in the part between adjacent grid of interlayer dielectric layer after interlayer dielectric layer is formed
Inside is formed empty (void).And these cavities will influence subsequent interlayer dielectric layer CMP, dummy grid removal and contact hole
The techniques such as formation, the yield for eventually leading to semiconductor devices decline.
Illustratively, etching liquid is phosphoric acid used by wet method SPT processing.Also, used technological temperature can be with
It is 100-160 DEG C.
Step A4：Removal is located at the protrusion (overhang) 1056 of the apical lateral of the first side wall 105, such as Fig. 1 D institutes
Show.
Wherein, the step of removal protrusion (overhang) 1056, is not available in the prior art, which also may be used
To be referred to as " rear stress closes on technological processing craft " (post-SPT), main purpose is to remove by the first side wall 105 and the
The ridge 1056 that the tip portion of oxide skin(coating) 1061 in two side walls 106 is formed.By this step, interlayer can be based on and be situated between
The needs of electric layer gap filling adjust the pattern after removal protrusion (overhang) 1056 well.
Optionally, the method for removing protrusion 1056 can be SiCoNi etchings or dry etching etc..Wherein, it is carrying out
When SiCoNi is etched, SiCoNi etchings in situ or ex situ SiCoN can be selected to etch silicon of making a return journey, while reduce to source
The damage of drain region nisiloy.In dry etching, common dry etching may be used；Etching intensity can also be controlled, using low inclined
The dry etching (soft dry etch) of power is forced down, to avoid to the first side wall 105 and metal silicide, germanium silicon layer etc.
Cause excessive etching.
Since relative to the prior art, the present embodiment is due to increasing removal positioned at the apical lateral of the first side wall 105
The step of protrusion 1056, therefore the clearance filling capability when forming interlayer dielectric layer can be improved, ensure interlayer dielectric layer
Normal sedimentation (cavity will not be formed), and then ensure the shape of subsequent interlayer dielectric layer CMP, dummy grid removal and contact hole
Into etc. techniques, finally improve the yield of entire semiconductor devices.
Step A5：Contact hole etching barrier layer (CESL) 107 is formed on a semiconductor substrate 100, as referring to figure 1E.
Since the protrusion 1056 for the apical lateral for being located at the first side wall 105 is removed, forming contact hole etching
Be not in contact hole etching barrier layer (CESL) 107 on the top of the both sides of dummy gate structure after barrier layer (CESL) 107
Protrusion, as referring to figure 1E.
Step A6：Interlayer dielectric layer 108 is formed on contact hole etching barrier layer (CESL) 107, as shown in fig. 1F.
Since the protrusion of contact hole etching barrier layer (CESL) 107 being not present on the top of the both sides of dummy gate structure, because
This, the gap filling when forming interlayer dielectric layer will not be stopped, can improve clearance filling capability, ensure interlayer dielectric
The normal sedimentation (cavity will not be formed) of layer 108, and then ensure subsequent interlayer dielectric layer CMP, dummy grid removal and contact
The techniques such as the formation in hole finally improve the yield of entire semiconductor devices.
Wherein, the method for forming interlayer dielectric layer 108, can be sedimentation or other suitable methods；Further, shape
Method into the interlayer dielectric layer 108 is high-aspect-ratio (HARP) completion method.The material of interlayer dielectric layer 108 can be oxygen
Compound, silicon nitride or other suitable materials.Illustratively, the method for the interlayer dielectric layer is formed as sedimentation, and institute
Equipment of the material (material for referring mainly to be used to form interlayer dielectric layer) of deposition using having the function of SiCoNi etchings in situ, can
To use original position SiCoNi reative cells before deposition materials.Further to remove the projection portion positioned at 105 outside of the first side wall
(for example, remaining protrusion 1056), to improve clearance filling capability.
In addition, after step A 6, it can also include the following steps：
Step A7：CMP (chemically mechanical polishing) is carried out to interlayer dielectric layer 108.
Step A8：Form metal gates.That is, removal dummy grid, metal gates are formed in the original position of dummy grid.
Step A9：Form contact hole (CT) and interconnection structure.
So far, the introduction of the committed step of the manufacturing method of the semiconductor devices of the present embodiment is completed, can be joined later
The manufacture of entire semiconductor devices is completed according to each method of the prior art, details are not described herein again.In the present embodiment, it walks
Rapid A5 can be omitted.Also, among each step of step A1 to A9 and between adjacent step, existing skill can also be included
Other processing steps in art, are not defined herein.
The manufacturing method of the semiconductor devices of the embodiment of the present invention, by carry out stress close on technical finesse the step of it
Afterwards, the step of increasing protrusion 1056 of apical lateral that removal is formed in the first side wall 105, can improve and form interlayer Jie
Clearance filling capability during electric layer ensures the normal sedimentation (will not form cavity) of interlayer dielectric layer, improves entire semiconductor device
The yield of part.
With reference to Fig. 2, a kind of typical method in the manufacturing method of semiconductor devices proposed by the present invention is shown
Flow chart, for schematically illustrating the flow of entire manufacturing process.It specifically includes：
Step S101：Semiconductor substrate is provided, formation includes dummy grid on the semiconductor substrate and dummy grid is covered firmly
The dummy gate structure of film, and form the first side wall in the both sides of the dummy gate structure；
Step S102：Second sidewall is formed in the outside of the first side wall, wherein the second sidewall is included positioned at interior
The oxide skin(coating) of side and the silicon nitride layer positioned at outside；
Step S103：It carries out stress and closes on technical finesse, wherein, close on technical finesse, the puppet grid by the stress
Extremely hard mask is removed with the silicon nitride layer in the second sidewall, and the first side wall apical lateral formed it is prominent
Go out object；
Step S104：Removal is formed in the protrusion of the apical lateral of the first side wall；
Step S105：Interlayer dielectric layer is formed on the semiconductor substrate.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (11)
1. a kind of manufacturing method of semiconductor devices, which is characterized in that the method includes：
Step S101：Semiconductor substrate is provided, is formed include dummy grid and the hard mask of dummy grid on the semiconductor substrate
Dummy gate structure, and form the first side wall in the both sides of the dummy gate structure；
Step S102：Second sidewall is formed in the outside of the first side wall, wherein, the second sidewall is included positioned inside
Oxide skin(coating) and the silicon nitride layer positioned at outside；
Step S103：It carries out stress and closes on technical finesse, wherein, technical finesse is closed on by the stress, the dummy grid is hard
Mask is removed with the silicon nitride layer in the second sidewall, and forms protrusion in the apical lateral of the first side wall
Object；
Step S104：Stress closes on technological processing craft after execution, and removal is formed in the institute of the apical lateral of the first side wall
Protrusion is stated, to reduce the damage to source-drain area, metal silicide and germanium silicon layer in Semiconductor substrate；
Step S105：Interlayer dielectric layer is formed on the semiconductor substrate.
2. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that in the step S104, removal
The method of the protrusion includes SiCoNi etchings or dry etching.
3. the manufacturing method of semiconductor devices as claimed in claim 2, which is characterized in that described in the step S104
The method that dry etching uses includes the dry etching of low bias low-power.
4. the manufacturing method of semiconductor devices as claimed in claim 2, which is characterized in that described in the step S104
SiCoNi etchings include original position SiCoNi etchings or ex situ SiCoNi etchings.
5. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that described in the step S103
Stress closes on technical finesse and closes on technical finesse for wet method stress.
6. the manufacturing method of semiconductor devices as claimed in claim 5, which is characterized in that described in the step S103
Etching liquid includes phosphoric acid used by wet method stress closes on technical finesse.
7. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that in the step S105, formed
The method of the interlayer dielectric layer is sedimentation, and the sedimentation uses the equipment for having the function of that SiCoNi in situ is etched, into
Before row depositing operation the protrusion is removed using original position SiCoNi etchings.
8. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that in the step S105, formed
The method of the interlayer dielectric layer is high-aspect-ratio completion method.
9. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that in the step S104 and step
Step S1045 is further included between S105：Form contact hole etching barrier layer.
10. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that described in the step S101
The material of the first side wall includes silicon nitride.
11. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that in the rapid S101, described
One side wall includes offset side wall and/or germanium silicon shielding layer side wall.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101740338A (en) * | 2008-11-24 | 2010-06-16 | 中芯国际集成电路制造(北京)有限公司 | Method for removing film |
| CN102983075A (en) * | 2011-09-07 | 2013-03-20 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device applying stress approaching technology |
| CN103515321A (en) * | 2012-06-28 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device side wall forming method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8697557B2 (en) * | 2011-06-07 | 2014-04-15 | Globalfoundries Inc. | Method of removing gate cap materials while protecting active area |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101740338A (en) * | 2008-11-24 | 2010-06-16 | 中芯国际集成电路制造(北京)有限公司 | Method for removing film |
| CN102983075A (en) * | 2011-09-07 | 2013-03-20 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device applying stress approaching technology |
| CN103515321A (en) * | 2012-06-28 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device side wall forming method |
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