CN105097510B - The forming method of transistor - Google Patents
The forming method of transistor Download PDFInfo
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- CN105097510B CN105097510B CN201410155750.6A CN201410155750A CN105097510B CN 105097510 B CN105097510 B CN 105097510B CN 201410155750 A CN201410155750 A CN 201410155750A CN 105097510 B CN105097510 B CN 105097510B
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Abstract
A kind of forming method of transistor, comprising: substrate is provided；Pseudo- grid structure is formed on the first region, and dummy gate structure includes pseudo- gate dielectric layer and dummy grid；Second grid structure is formed on the second area, the second grid structure includes the second gate dielectric layer and second grid, and less than the thickness of the second gate dielectric layer, the dummy grid flushes the thickness of the puppet gate dielectric layer with the top surface of second grid；Side wall is formed in pseudo- grid structure and second grid structure side wall surface；First medium layer is formed on the substrate；Dummy gate structure is removed, forms groove on the first region；First grid structure is formed in the groove, and the first grid structure includes the first gate dielectric layer positioned at the groove inner wall surface and the second grid structure positioned at the first grid dielectric layer surface and the full groove of filling.The performance of the transistor of core space can be improved in the method.
Description
Technical field
The present invention relates to technical field of semiconductors, the in particular to forming method of transistor.
Background technique
With the continuous improvement of semiconductor devices integrated level, the reduction of technology node, traditional gate dielectric layer is constantly thinning,
The problems such as transistor leakage amount increases therewith, causes semiconductor devices power wastage.To solve the above problems, the prior art provides
A kind of solution by metal gates substitution polysilicon gate.Wherein, " rear grid (gate last) " technique is to form high karat gold
Belong to a main technique of gridistor.
Simultaneously as the integrated level of chip is higher and higher, scale is also increasing, and core is normally comprised on one single chip
Transistor area and input/output (I/O) transistor area, the operating voltage of core logic transistor is generally lower, can drop
Low system power dissipation, and the operating voltage of input/output transistors is generally higher, it is ensured that higher driving capability and breakdown potential
Pressure.
The relatively thin high-K metal gate gated transistors of gate dielectric layer are generally formed using " rear grid " technique in the prior art, are used for
The lower core transistor region of operating voltage；And " front gate " technique is used to form the thicker polysilicon gate polar crystal of gate dielectric layer
Pipe is applied to the higher input/output of operating voltage (I/O) transistor area, to meet different zones transistor to work electricity
The requirement of pressure.
The performance of the transistor for the core space that the prior art is formed needs to be further improved.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of transistor, improves the performance of core space transistor.
To solve the above problems, the present invention provides a kind of forming method of transistor, comprising: provide substrate, the substrate
Including first area and second area；Pseudo- grid structure is formed on the first area, dummy gate structure includes being located at substrate
The pseudo- gate dielectric layer on surface and dummy grid positioned at the pseudo- gate dielectric layer surface；Second grid is formed on the second area
Structure, the second grid structure include the second gate dielectric layer and the second grid positioned at the second gate dielectric layer surface, institute
Thickness of the thickness less than the second gate dielectric layer of pseudo- gate dielectric layer is stated, the dummy grid is flushed with the top surface of second grid；
Side wall is formed in dummy gate structure and second grid structure side wall surface；First medium layer is formed over the substrate, it is described
The surface of first medium layer is flushed with the top surface of dummy gate structure and second grid structure；Dummy gate structure is removed,
Groove is formed on the first region, and the bottom portion of groove exposes the surface of section substrate；The first grid is formed in the groove
Pole structure, the first grid structure include positioned at first gate dielectric layer on the groove inner wall surface and positioned at the first grid
Dielectric layer surface and the second grid structure for filling the full groove.
Optionally, the method for forming dummy gate structure and second grid structure includes: to cover in substrate surface formation
The gate dielectric material layer of the first area and second area is covered, the thickness of the gate dielectric material layer on the first area is less than
The thickness of gate dielectric material layer on second area；Gate material layers are formed in the gate dielectric material layer surface；Described in etching
Gate dielectric material layer and gate material layers form pseudo- grid structure on the first region, form second grid knot on the second region
Structure.
Optionally, the method for forming the gate dielectric material layer includes: to form grid in homogeneous thickness in the substrate surface
Dielectric material film；The first mask layer is formed in the gate dielectric material film surface of second area, is exposed on first area
Gate dielectric material film；Using first mask layer as exposure mask, the gate dielectric material film on the first area is etched, is formed
Gate dielectric material layer makes the thickness of the gate dielectric material layer on the first area be less than the gate dielectric material layer on second area
Thickness.
Optionally, the pseudo- gate dielectric layer with a thickness of 0.5nm~2.5nm, second gate dielectric layer with a thickness of
10nm~20nm.
Optionally, the material of the gate dielectric material layer is silica.
Optionally, further includes: etch the first grid structure, make the top surface of the first grid structure lower than institute
State the top surface of first medium layer；Protective layer, the top surface of the protective layer are formed in the first grid structural top
It is flushed with the top surface of first medium layer.
Optionally, the thickness of the protective layer is less than 10nm.
Optionally, second medium is formed in the first medium layer surface, protective layer and second grid body structure surface
Layer.
Optionally, further includes: etch the second dielectric layer, form first in the second dielectric layer of first area and open
Mouthful, first open bottom exposes the surface of the partial protection layer in first grid structure, and second in second area is situated between
The second opening is formed in matter layer, second opening exposes the part of the surface of part second grid；Along the first opening etching institute
Protective layer is stated, the surface of part first grid is exposed, forms first through hole, while etching the second gate along the second opening
Pole, forms the second through-hole, and the bottom surface of second through-hole is located in the second grid.
Optionally, the etch rate of the protective layer is less than the etch rate of second grid.
Optionally, the etch rate of the second grid is 3 times or more of protective layer etch rate.
Optionally, the material of the protective layer is silicon nitride, and the material of the second grid is polysilicon.
Optionally, further includes: metal material is filled in the first through hole and the second through-hole, in the first grid table
Face forms the first metal plug, forms the second metal plug on the second grid surface.
Optionally, the second fin on substrate second area, and positioned at the separation layer of the substrate surface, it is described
Separation layer covers the partial sidewall of the first fin and the second fin, and the surface of the separation layer lower than first fin and
The top surface of second fin.
Optionally, the described first pseudo- grid structure is across first fin, and the first fin of covering part separation layer and part
Portion；The first grid structure is across second fin, and the second fin of covering part separation layer and part.
Optionally, the material of first gate dielectric layer is hafnium oxide, zirconium oxide, silicon hafnium oxide, silicon zirconium oxide, aluminium oxide
Or oxygen calorize hafnium.
Optionally, the material of the second grid is aluminium, copper, silver, gold, platinum, nickel, titanium, titanium nitride, tungsten or tungsten nitride.
Optionally, before forming the first grid structure, boundary layer is formed in the substrate surface of the bottom portion of groove.
Optionally, it is aoxidized using substrate surface of the oxidation technology to the bottom portion of groove, forms the boundary layer, institute
The material for stating boundary layer is silica.
Optionally, dummy gate structure is removed using wet-etching technology or non-plasma dry etch process.
Compared with prior art, technical solution of the present invention has the advantage that
Technical solution of the present invention, forms pseudo- grid structure on the first area of substrate, and dummy gate structure includes being located at
The pseudo- gate dielectric layer of substrate surface and dummy grid positioned at the pseudo- gate dielectric layer surface；Is formed on the second area of substrate
Two gate structures, the second grid structure include the second gate dielectric layer and the second gate positioned at the second gate dielectric layer surface
Pole, it is described puppet gate dielectric layer thickness less than the second gate dielectric layer thickness；Then first medium layer is formed over the substrate,
The surface of the first medium layer is flushed with the top surface of dummy gate structure and second grid structure；Remove the pseudo- grid knot
Structure forms groove on the first region, forms first grid structure in the groove.Due to the thickness of the pseudo- gate dielectric layer
It is smaller, the pseudo- gate dielectric layer can be performed etching using the lesser etching agent of concentration, and etch period is shorter, to etching
Process is easy to control, and can stop the etching technics in time after removing the pseudo- gate dielectric layer, with puppet in the prior art
For the thickness of gate dielectric layer compared with the thickness of the second gate dielectric layer is identical, technical solution of the present invention uses relatively thin pseudo- gate medium
Layer can cause biggish damage during removing the pseudo- gate dielectric layer to avoid to first medium layer and substrate surface,
So as to improve the performance of the transistor formed on the first area I.
Further, technical solution of the present invention etches the first grid after forming the first grid structure
Structure makes the top surface of the first grid structure lower than the top surface of the first medium layer；In the first grid knot
Protective layer is formed at the top of structure, the top surface of the protective layer is flushed with the top surface of first medium layer.The protective layer can
To protect the top surface of the first grid.It is subsequent to form second dielectric layer in the first medium layer surface, and etch
The second dielectric layer and first medium layer form the first opening for exposing protective layer and expose second grid surface
Second opening；Then continue to etch the protective layer along first opening, while etching the second grid.The protection
The etch rate of layer can be less than the etch rate of the second grid, so that the depth of finally formed second through-hole is greater than the
The depth of one through-hole is located at the second through-hole of part in first grid, subsequent is formed in second through-hole to improve
Contact area between second metal plug and second grid, to reduce between second metal plug and second grid
Contact resistance improves the performance of transistor.
Detailed description of the invention
Fig. 1 to Figure 14 is the structural schematic diagram of the forming process of transistor of the invention.
Specific embodiment
As described in the background art, the performance of the transistor for the core space that the prior art is formed needs to be further improved.
The prior art generally exists during forming the transistor and input/input area transistor of the core space
Semiconductor substrate surface, which forms while covering the pseudo- gate dielectric material floor of core space and input/output area and is located at the pseudo- grid, to be situated between
The dummy grid material layer of matter layer surface；Then the pseudo- gate dielectric material layer and dummy grid material layer are patterned, are formed
The dummy gate layer of dummy grid material layer and the dummy grid material surface on core space, and it is located at input/output
The gate dielectric layer on area surface and be located at the gate dielectric layer and grid layer so that it is described puppet gate dielectric layer thickness and gate dielectric layer
Thickness it is identical；Form the dielectric layer flushed with the dummy gate layer, grid layer surface on the semiconductor substrate again；Then
The pseudo- gate dielectric layer and dummy gate layer are removed, forms groove in the dielectric layer on the core space, then in the groove
Form high-K metal gate structure.
Since the thickness of the pseudo- gate dielectric layer of core space is identical as the thickness of gate dielectric layer on input/output area surface, institute
Larger with the thickness of the pseudo- gate dielectric layer, during removing the pseudo- gate dielectric layer, etching process is longer, the quarter of use
Lose agent concentration it is also larger, thus be easy biggish damage is caused to semiconductor substrate surface, simultaneously because the dielectric layer with
The etching of pseudo- gate dielectric layer is smaller, and certain loss can be also caused to dielectric layer while removing the pseudo- gate dielectric layer,
The quality of the dielectric layer is influenced, the performance so as to cause the transistor formed on core space is affected.
Particularly, when the above method is applied to the production of fin formula field effect transistor, since the size of the fin is smaller,
For planar transistor, the damage caused by fin portion surface is brilliant for the size of fin and the fin field effect of formation
The performance of body pipe can all cause bigger influence.
The embodiment of the present invention forms pseudo- grid structure on the core space surface of substrate, forms grid in input/output area
Structure, the pseudo- gate dielectric layer thickness for being greater than pseudo- grid structure of the gate dielectric layer thickness of the gate structure, thus in subsequent removal
During the puppet gate dielectric layer, the damage to substrate surface can reduce, so as to improve the crystalline substance on the core space
The performance of body pipe.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Referring to FIG. 1, providing substrate 100, the substrate 100 includes first area I and second area II, in the substrate
100 surfaces form gate dielectric material film 200 in homogeneous thickness.
The material of the substrate 100 includes the semiconductor materials such as silicon, germanium, SiGe, GaAs, and the substrate 100 can be with
It is that body material is also possible to composite construction such as silicon-on-insulator.Those skilled in the art can be according to forming on substrate 100
Semiconductor devices selects the type of the substrate 100, therefore the type of the substrate 100 should not limit protection model of the invention
It encloses.
It is subsequent on the first area I and second area II to be respectively formed the transistor with different operating voltage.This reality
It applies in example, is logic region in the first area I, it is subsequent to form the first transistor on the first area I；Described second
Region II is input/output region, subsequent to be used to form second transistor in the second area II；And the first crystal
The operating voltage of pipe is less than the threshold voltage of second transistor.The first area I and second area II can adjacent or not phase
It is adjacent.
In other embodiments of the invention, the substrate includes substrate, the first fin on the I of substrate first area
Portion, the second fin on substrate second area II, and positioned at the separation layer of the substrate surface, the separation layer covering
The partial sidewall of first fin and the second fin, and the surface of the separation layer is lower than first fin and the second fin
Top surface, it is subsequent to form fin formula field effect transistor over the substrate.The pseudo- grid structure being subsequently formed is across described first
Fin, the second grid structure being subsequently formed is across second fin.
The material of the gate dielectric material film 200 is the insulating dielectric materials such as silica or silicon oxynitride, can be used
Atom layer deposition process or chemical vapor deposition process form the gate dielectric material film 200.Positioned at the second area II
On gate dielectric material film 200 be used to form the second gate dielectric layer on second area II, so, the gate dielectric material is thin
The thickness of film 200 is identical as thickness required by the second gate dielectric layer of the second transistor on second area II to be formed,
Since the second transistor is located at input/output region, it is desirable that operating voltage with higher, so, the second gate is situated between
The thickness of matter layer is higher.In the present embodiment, the material of the gate dielectric material film 200 is silica, with a thickness of 10nm~
20nm。
Referring to FIG. 2,201 surface of gate dielectric material film on second area II forms the first mask layer 301, exposure
Gate dielectric material film 200 (please referring to Fig. 1) on the I of first area out；It is exposure mask with first mask layer 301, etches institute
The gate dielectric material film 200 on the I of first area is stated, gate dielectric material layer 201 is formed, the grid on the first area I is made to be situated between
The thickness of the material bed of material 201 is less than the thickness of the gate dielectric material layer 201 on second area II.
The material of first mask layer 301 is photoresist, and the method for forming first mask layer 301 includes: use
Spin coating proceeding forms photoresist layer in 200 film of gate dielectric material film；Development is exposed to the photoresist layer, is gone
Except the photoresist layer for 200 film of gate dielectric material film being located on the I of first area, first be located on second area II is formed
Mask layer 301.First mask layer 301 is used to protect the gate dielectric material film on second area II.
In other described examples of the invention, first mask layer 301 can also be silicon nitride, amorphous carbon etc. other
Mask material.
It is formed after first mask layer 301, is exposure mask with first mask layer 301, etch the gate medium material
Expect film 200, forms gate dielectric material layer 201.
The gate dielectric material film 200, the present embodiment can be etched using wet-etching technology or dry etch process
In, the gate dielectric material film 200 is etched using dry etch process, compared with wet-etching technology, using dry etching
Technique is easier to control the amount of the gate dielectric material film 200 etched away, makes the gate dielectric material layer 201 on the I of first area
Thickness is easier to control.After etching the gate dielectric material film 200, gate dielectric material layer 201, firstth area are formed
The thickness of gate dielectric material layer 201 on the I of domain is less than the thickness of the gate dielectric material layer 201 on second area II, the present embodiment
In, the grid with a thickness of 0.5nm~2.5nm, on the second area II of gate dielectric material layer 201 on the first area I
Layer of dielectric material 201 with a thickness of 10nm~20nm.
Referring to FIG. 3, removal first mask layer 301, forms grid material on 201 surface of gate dielectric material layer
Layer 202.
First mask layer 301 can be removed using cineration technics or wet-etching technology.
The material of the gate material layers 202 is polysilicon, and the gate material layers 202 are subsequently used for forming first area
The second grid on dummy grid and second area II on I.
The gate material layers 202 can be formed using chemical vapor deposition process, specifically in the gate dielectric material
201 surface of layer are formed after certain thickness grid material, are planarized to the grid material, and gate material layers are formed
202, flush the gate material layers 202 on the first area I with the surface of the gate material layers 202 on second area II.
Referring to FIG. 4, etching the gate dielectric material layer 201 (please referring to Fig. 3) and gate material layers 202 (please refer to figure
3) pseudo- grid structure, is formed on the I of first area, forms second grid structure on second area II, and dummy gate structure includes
Pseudo- gate dielectric layer 201a on the I of the first area and dummy grid 202a positioned at the puppet surface gate dielectric layer 201a, it is described
Second grid structure includes the second gate dielectric layer 201b on the second area II and is located at the second gate dielectric layer 201b
The second grid 202b on surface.
The gate material layers 202 and gate dielectric material can be sequentially etched using anisotropic dry etch process etching
Layer 201 forms dummy gate structure and second grid structure.
The gate dielectric material layer being less than on second area II due to the thickness of the gate dielectric material layer 201 on the I of first area
201 thickness, so etching the thickness for the pseudo- gate dielectric layer 201a that the gate dielectric material layer 201 is formed less than the second gate medium
The thickness of layer 201b.In the present embodiment, the puppet gate dielectric layer 201a with a thickness of 0.5nm~2.5nm, second gate medium
Layer 201b with a thickness of 10nm~20nm.Grid of the second grid structure as the second transistor formed on second area II
Pole structure, since the thickness of the second gate dielectric layer 201b is higher, so, the second transistor work electricity with higher
Pressure.
Due to the surface of the gate material layers 202 on the first area I and the gate material layers 202 on second area II
It flushes, so the top surface of the dummy grid 202a and second grid 202b flushes.
Referring to FIG. 5, forming side wall 203 in dummy gate structure and second grid structure side wall surface.
The material of the side wall 203 can be the dielectric materials such as silicon nitride or silica, for protecting pseudo- grid structure and
The side wall of two gate structures is injury-free in the subsequent process.
In the present embodiment, the material of the side wall 203 is silicon nitride, and the method for forming the side wall 203 includes: described
100 surface of substrate, pseudo- grid structure, second grid body structure surface form spacer material layer；Institute is etched using no mask etching technique
Spacer material layer is stated, removal is located at the side on 100 surface of substrate, dummy grid 202a top surface and second grid 202b top surface
The walling bed of material forms the side wall 203 for being located at pseudo- grid structure sidewall surfaces and second grid structure side wall surface.
It is formed after the side wall 203, forms in the first area I of the substrate 100 of the dummy gate structure two sides
One source-drain electrode (not shown) forms the second source in the second area II of the substrate 100 of second grid structure two sides
Drain (not shown), the thickness limit of the side wall 203 the distance between first source-drain electrode and dummy gate structure,
And second the distance between source-drain electrode and second grid structure.
Referring to FIG. 6, on the substrate 100 formed first medium layer 400, the surface of the first medium layer 400 with
The top surface of dummy gate structure and second grid structure flushes.
The material of the first medium layer 400 can be the dielectric materials such as silica, silicon oxide carbide or porous silica.Shape
Method at the first medium layer 400 includes: formation first medium material layer, the first medium on the substrate 100
Material layer covers dummy gate structure, second grid structure and side wall 203；With the dummy grid 202a and second grid 202b
Top surface as polish stop layer, the first medium material layer is planarized using chemical mechanical milling tech,
First medium layer 400 is formed, the surface of the first medium layer 400 and the top of the dummy grid 202a, second grid 202b are made
Portion surface flushes.
In the present embodiment, the material of the first medium layer 400 is silica.In other embodiments of the invention, institute
The material for stating first medium layer 400 can be low K or ultralow K dielectric material, to reduce parasitic capacitance.
It is to cover with second mask layer 302 referring to FIG. 7, forming the second mask layer 302 on the second area II
Film removes the pseudo- grid structure on the I of first area, and groove 401 is formed on the I of first area, and 401 bottom-exposed of groove goes out portion
Divide the surface of substrate 100.
First remove the dummy grid 202a and then etching removal pseudo- gate dielectric layer 201a.It can be carved using wet process
Etching technique or dry etch process remove the dummy grid 202a.In the present embodiment, the puppet is removed using wet-etching technology
The etching solution of grid 202a, the wet etching are potassium hydroxide solution, due to the first medium layer 400 and dummy grid
The material of 202a etching selection ratio with higher during the wet etching, so, compared with dry etch process, adopt
The first medium layer 400 will not be caused to damage during removing the dummy grid 202a with wet-etching technology.
After removing dummy grid 202a, institute can be removed using wet-etching technology or non-plasma dry etch process
State pseudo- gate dielectric layer 201a.In the present embodiment, using the wet-etching technology removal pseudo- gate dielectric layer 201a.Due to the puppet
The thickness of gate dielectric layer 201a is smaller, can be carved using the lesser etching solution of concentration to the puppet gate dielectric layer 201a
It loses, in the present embodiment, using the hydrofluoric acid solution etching pseudo- gate dielectric layer 201a, the concentration of the hydrofluoric acid solution is 1%
~10%, etch rate is lower, can preferably control the etching process to the pseudo- gate dielectric layer 201a, also, by institute
The thickness for stating pseudo- gate dielectric layer 201a is smaller, so the time of the wet etching process is shorter.Since the wet etching is molten
Liquid also has certain etch rate for the first medium layer 400, during removing the puppet gate dielectric layer 201a,
Also certain etching can be caused to the first medium layer 400, but since the concentration of the etching solution is smaller, etch period
It is shorter, so, the influence to the first medium layer 400 is little.
It in other embodiments of the invention, can also be using the dry etch process using non-plasma to the puppet
Gate dielectric layer 201a is performed etching, and the non-plasma dry etch process can be gas etching technique, by etching gas
The warm-up movement of body performs etching the puppet gate dielectric layer 201a, and the etching gas can be fluoro-gas, such as CF4、SF6
Or NF3Deng.Since the dry etch process gas is non-plasma state, etch rate is lower, and etching gas
Kinergety is lower, smaller to the etching injury on 400 surface of first medium layer in etching process, and can be to avoid removing
The surface of substrate 100 is caused to avoid influencing subsequent on the substrate 100 compared with macrolesion after the puppet gate dielectric layer 201a
The deposition quality of the first grid structure of formation.
Referring to FIG. 8, removal second mask layer 302 (please referring to Fig. 7), in the groove 401 (please referring to Fig. 7)
First grid structure is formed, the first grid structure includes the first gate dielectric layer 204 positioned at 401 inner wall surface of groove
With the first grid 205 for being located at 204 surface of the first gate dielectric layer and the full groove 401 of filling.
Second mask layer 302 can be removed using wet-etching technology or cineration technics.
The method for forming the first grid structure includes: the inner wall surface in first groove 401 (please referring to Fig. 7)
And the surface on the surface of side wall 203, first medium layer 400 forms first grid layer of dielectric material；In the first gate medium material
Bed of material surface forms first grid material layer, and the first grid material layer fills full first groove 401；With the medium
400 surface of layer are polish stop layer, using chemical mechanical milling tech to the first grid material layer and the first gate medium material
The bed of material is planarized, and is formed the first grid layer of dielectric material 204 being located in first groove 401, is located at the first grid
Fill the first grid 205 of full first groove 401 in 204 surface of layer of dielectric material.
The material of first gate dielectric layer 204 is hafnium oxide, zirconium oxide, silicon hafnium oxide, silicon zirconium oxide, aluminium oxide or oxygen
The high K dielectric material such as calorize hafnium.The material of the first grid 205 is aluminium, copper, silver, gold, platinum, nickel, titanium, titanium nitride, tungsten or nitrogen
Change the metal materials such as tungsten.
In other embodiments of the invention, it is formed in the groove 401 before the first grid structure, described
100 surface of substrate of 401 bottom of groove forms boundary layer.Can using oxidation technology to the substrate surface of the bottom portion of groove into
Row oxidation, forms the boundary layer, the material of the boundary layer can be silica.The boundary layer can be used as first grid Jie
Transition zone between 100 surface of matter layer 204 and substrate is avoided due to first gate dielectric layer 204 and the material before substrate 100
Material lattice mismatches the problem for causing the deposition quality of the first gate dielectric layer 204 poor, also, the boundary layer and substrate 100,
Higher adhesion strength is all had between first gate dielectric layer 204, the substrate 100, boundary layer and the first grid can be improved and be situated between
Interface quality between matter layer 204.
It is to cover with the third mask layer 303 referring to FIG. 9, forming third mask layer 303 on the second area II
Film etches the first grid structure, and the top surface of the first grid structure is made to be lower than the top of the first medium layer 400
Portion surface.
The material of the third mask layer 303 can be the mask materials such as silicon nitride, silica, described in the present embodiment
The material of third mask layer 303 is photoresist layer.Second mask layer 302 can protect the second gate in the subsequent process
Pole 202b.Due to Etch selectivity with higher between the first grid 205 and second grid 202b, in its of the invention
In his embodiment, the third mask layer 303 can not also be formed.In the present embodiment, the material of the third mask layer 303 is
Photoresist.
The first gate dielectric layer 204 of the first grid 205 and its two sides, the dry method are etched using dry etch process
The etching gas of etching is Cl2Or CF4, decline the height of the first grid structure, so that the top table of first grid structure
Face is lower than the surface of first medium layer 400, forms protection layer by layer in the first grid structural top so as to subsequent.
In the present embodiment, the first grid structure is etched, makes the first grid body structure surface lower than first medium layer
The thickness on 400 surfaces can be 5nm~10nm.
Referring to FIG. 10, after removing the third mask layer 303 (please referring to Fig. 9), on first grid structure top
Portion forms protective layer 206, and the top surface of the protective layer 206 is flushed with the top surface of first medium layer 400.
The third mask layer 303 can be removed using wet etching or cineration technics.
The method for forming the protective layer 206 includes: in first grid structural top surface and first medium layer
400 surfaces are formed after the protected material bed of material, using the surface of the first medium layer 400 as stop-layer, to the protection materials
Layer carries out planarization process, forms the protective layer 206 for being located at first grid structural top, make the surface of the protective layer 206 with
The surface of first medium layer 400 flushes.
The protective layer 206 is as the etching barrier layer for being subsequently formed first through hole.
Since the first area I is logic area, the device density of the logic area is larger, generally requires and passes through autoregistration
Technique forms the through-hole of the first source and drain pole surface of the first transistor on the first area I, and the protective layer can also be
As mask layer when forming the through-hole of the first source and drain pole surface using self-registered technology on the I of first area, the first grid is protected
Pole structure.
And since second area II is input/output region, device density is lower, does not need to be formed using self-registered technology
Positioned at the through-hole of the second source and drain pole surface, so, it does not need to form the protective layer in the second grid structural top.
The thickness of the protective layer 206 is less than 10nm, can be 5nm~10nm.The thickness of the protective layer 206 is protected enough
Protect the first grid structure.
The material of the protective layer 206 is different from the material of first medium layer 400, in the present embodiment, the protective layer 206
Material be silicon nitride.
Figure 11 is please referred to, in 400 surface of first medium layer, 206 surface of protective layer and the surface second grid 202b shape
At second dielectric layer 500.
The material of the second dielectric layer 500 can be the dielectric materials such as silica, silicon oxide carbide or porous silica.This
In embodiment, the material of the second dielectric layer 500 is identical as the material of first medium layer 400, is silica.Of the invention
In other embodiments, the material of the second dielectric layer 500 can also be low K or ultralow K dielectric material, to reduce parasitic electricity
Hold.
Figure 12 is please referred to, the second dielectric layer 500 is etched, forms first in the second dielectric layer 500 of first area I
Opening 501, first opening, 501 bottom-exposeds go out the surface of the partial protection layer 206 in first grid structure, in the secondth area
The second opening 502 is formed in the second dielectric layer 500 of domain II, second opening 502 exposes part second grid 202b's
Part of the surface.
The method for forming first opening 501 and the second opening 502 includes: in the 500 surface shape of second dielectric layer
At Patterned masking layer, the Patterned masking layer exposes the table with the part second dielectric layer 500 of 205 face of first grid
Face, and the surface with the part second dielectric layer 500 of second grid 202b face；It is carved by exposure mask of the Patterned masking layer
The second dielectric layer 500 is lost, the first opening 501 is formed in the second dielectric layer 500 on the first area I, second
Second medium on the II of region, which is surveyed in light 500, forms the second opening 502.The width of first opening 501 is less than or equal to institute
The width of first grid 205 is stated, the width of second opening 502 is less than the width of second grid 202b, so that described first
The part of the surface for the protective layer 206 that 501 bottom-exposeds that are open go out on first grid 205, second opening 502 expose second
The part of the surface of grid 202b.
Figure 13 is please referred to, continues to etch the protective layer 206 along first opening, 501 (please referring to Figure 12), forms the
One through-hole 511, the first through hole 511 expose the surface of part first grid 205；Etching the same of the protective layer 206
When, the second grid layer 202b is etched along the second 501 (please referring to Figure 12) of opening, forms the second through-hole 512, described second is logical
The bottom surface in hole 512 is located in the second grid 202b.
The protective layer 206 and second grid 202b are etched using dry etch process, the dry etch process is to institute
The etch rate of protective layer 206 is stated less than the etch rate to second grid 202b.The etching that the dry etch process uses
Gas can be CH3F or CH2F2Equal fluoro-gas, it is adjustable to described by adjusting the concentration and flow velocity of the etching gas
The etch rate of protective layer 206 and second grid 202b.
Since the etch rate of the protective layer 206 is less than the etch rate of first grid 202b, so described first is logical
Less than the depth of the second through-hole 512,512 part of the second through-hole is located in first grid 202b, improves the depth in hole 511
The area of the second grid 202b exposed, so as to reduce subsequent the second metal formed in second through-hole 512
Contact area between plug and second grid 202b, to reduce between second metal plug and second grid 202b
Contact resistance.And the material of the first grid 205 is metal, so the first through hole 511 only needs to expose first grid
205 part of the surface.
In the present embodiment, the etch rate of the second grid 202b is 3 times or more of 206 etch rate of protective layer, from
And it can make have enough contacts area between the second metal plug being subsequently formed and second grid 202b.
Figure 14 is please referred to, is filled out in the first through hole 511 (please referring to Figure 13) and the second through-hole 512 (please referring to Figure 13)
Metal material is filled, the first metal plug 521 is formed on 205 surface of first grid, in the surface second grid 202b shape
At the second metal plug 522.
The metal material can be W, Al, Cu or Au etc..It, can also be described the before filling the metal material
One through-hole 511,512 inner wall surface of the second through-hole formed diffusion barrier layer, the material of the diffusion barrier layer can be TiN or
TaN, the diffusion barrier layer can stop the metallic atom in the metal material of subsequent filling to diffuse into the second medium
In layer 500, the parasitic capacitance of device is influenced.The diffusion barrier layer can be formed using atom layer deposition process.
Since 512 part of the second through-hole is located in the second grid 202b, so that in second through-hole 512
522 part of the second metal plug formed is located in the second grid 202b, so that the bottom of second metal plug 522
Surface and partial sidewall surface are contacted with the second grid 202b, so as to reduce by second metal plug 522
With the contact resistance between second grid 202b, to improve the performance of the second transistor formed on second area II.
In other described examples of the invention, several the first adjacent grid structures are formed on the first area I, and
The first source-drain electrode is formed in substrate 100 between adjacent first grid structure.Due to the device density on the I of first area compared with
Greatly, the first medium layer between the second dielectric layer 500 and adjacent first grid is etched using self-registered technology, formation is located at
The source and drain through-hole of first source and drain pole surface, and source and drain plug is formed in the source and drain through-hole.Forming the source and drain through-hole
During, it is injury-free that the protective layer 206 can protect the first grid 205.
In conclusion pseudo- grid structure is formed under the embodiment of the present invention on the I of first area, while the shape on second area II
At second grid structure, also, the pseudo- gate dielectric layer thickness of dummy gate structure is less than the second gate medium of second grid structure
The thickness of layer, so that subsequent, etch period is shorter during removing the pseudo- gate dielectric layer, and the concentration of etching agent compared with
It is low, so as to reduce the damage in the etching process to first medium layer and substrate, to improve the shape on the I of first area
At the first transistor performance.
Also, the embodiment of the present invention also forms protective layer, and the protective layer on first grid structural top surface
Etch rate can be less than the etch rate of the second grid, due to expose the first grid etching protective layer formation
While the first through hole of pole surface, second grid structure is also performed etching, so that the depth of finally formed second through-hole
Greater than the depth of first through hole, it is located at the second through-hole of part in first grid, to improve subsequent in second through-hole
The contact area between the second metal plug and second grid formed, to reduce by second metal plug and second grid
Between contact resistance, improve the performance of transistor.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (18)
1. a kind of forming method of transistor characterized by comprising
Substrate is provided, the substrate includes first area and second area；
Pseudo- grid structure is formed on the first area, dummy gate structure includes the pseudo- gate dielectric layer and position positioned at substrate surface
Dummy grid in the pseudo- gate dielectric layer surface；
Second grid structure is formed on the second area, the second grid structure is including the second gate dielectric layer and is located at institute
State the second grid of second gate dielectric layer surface, the thickness of the puppet gate dielectric layer less than the second gate dielectric layer thickness, it is described
Dummy grid is flushed with the top surface of second grid；
Side wall is formed in dummy gate structure and second grid structure side wall surface；
First medium layer, the surface of the first medium layer and dummy gate structure and second grid knot are formed over the substrate
The top surface of structure flushes；
Dummy gate structure is removed, forms groove on the first region, the bottom portion of groove exposes the surface of section substrate；
First grid structure is formed in the groove, and the first grid structure includes positioned at the of the groove inner wall surface
One gate dielectric layer and positioned at the first grid dielectric layer surface and fill the first grid of the full groove；
Further include: the first grid structure is etched, makes the top surface of the first grid structure lower than the first medium
The top surface of layer；Protective layer, the top surface and first medium of the protective layer are formed in the first grid structural top
The top surface of layer flushes；Second is formed in the first medium layer surface, protective layer and second grid body structure surface to be situated between
Matter layer.
2. the forming method of transistor according to claim 1, which is characterized in that form dummy gate structure and second gate
The method of pole structure includes: to form the gate dielectric material layer of the covering first area and second area in the substrate surface,
The thickness of gate dielectric material layer on the first area is less than the thickness of the gate dielectric material layer on second area；In the grid
Dielectric material layer surface forms gate material layers；The gate dielectric material layer and gate material layers are etched, on the first region shape
At pseudo- grid structure, second grid structure is formed on the second region.
3. the forming method of transistor according to claim 2, which is characterized in that form the side of the gate dielectric material layer
Method includes: to form gate dielectric material film in homogeneous thickness in the substrate surface；In the gate dielectric material film of second area
Surface forms the first mask layer, exposes the gate dielectric material film on first area；Using first mask layer as exposure mask, carve
The gate dielectric material film on the first area is lost, gate dielectric material layer is formed, makes the gate medium material on the first area
The thickness of the bed of material is less than the thickness of the gate dielectric material layer on second area.
4. the forming method of transistor according to claim 2, which is characterized in that it is described puppet gate dielectric layer with a thickness of
0.5nm~2.5nm, second gate dielectric layer with a thickness of 10nm~20nm.
5. the forming method of transistor according to claim 2, which is characterized in that the material of the gate dielectric material layer is
Silica.
6. the forming method of transistor according to claim 1, which is characterized in that the thickness of the protective layer is less than
10nm。
7. the forming method of transistor according to claim 1, which is characterized in that further include: etch the second medium
Layer, forms the first opening in the second dielectric layer of first area, and first open bottom exposes in first grid structure
Partial protection layer surface, in the second dielectric layer of second area formed second opening, it is described second opening exposes portion
Divide the part of the surface of second grid；The protective layer is etched along the first opening, exposes the surface of part first grid, forms the
One through-hole, while the second grid is etched along the second opening, the second through-hole is formed, the bottom surface of second through-hole is located at
In the second grid.
8. the forming method of transistor according to claim 7, which is characterized in that the etch rate of the protective layer is less than
The etch rate of second grid.
9. the forming method of transistor according to claim 8, which is characterized in that the etch rate of the second grid is
3 times or more of protective layer etch rate.
10. the forming method of transistor according to claim 9, which is characterized in that the material of the protective layer is nitridation
Silicon, the material of the second grid are polysilicon.
11. the forming method of transistor according to claim 7, which is characterized in that further include: in the first through hole and
Metal material is filled in second through-hole, the first metal plug is formed on the first grid surface, on the second grid surface
Form the second metal plug.
12. the forming method of transistor according to claim 11, which is characterized in that the substrate includes substrate, is located at
The first fin on substrate first area, the second fin on substrate second area, and positioned at the substrate surface
Separation layer, the partial sidewall of separation layer covering first fin and the second fin, and the surface of the separation layer is lower than institute
State the top surface of the first fin and the second fin.
13. the forming method of transistor according to claim 12, which is characterized in that dummy gate structure is across described
One fin, and the first fin of covering part separation layer and part；The first grid structure is covered across second fin
The second fin of part separation layer and part.
14. the forming method of transistor according to claim 1, which is characterized in that the material of first gate dielectric layer
For hafnium oxide, zirconium oxide, silicon hafnium oxide, silicon zirconium oxide, aluminium oxide or oxygen calorize hafnium.
15. the forming method of transistor according to claim 14, which is characterized in that the material of the first grid is
Aluminium, copper, silver, gold, platinum, nickel, titanium, titanium nitride, tungsten or tungsten nitride.
16. the forming method of transistor according to claim 15, which is characterized in that forming the first grid structure
Before, boundary layer is formed in the substrate surface of the bottom portion of groove.
17. the forming method of transistor according to claim 16, which is characterized in that using oxidation technology to the groove
The substrate surface of bottom is aoxidized, and the boundary layer is formed, and the material of the boundary layer is silica.
18. the forming method of transistor according to claim 1, which is characterized in that using wet-etching technology or non-etc.
Gas ions dry etch process removes dummy gate structure.
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| US11942475B2 (en) * | 2019-10-18 | 2024-03-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | High voltage transistor structure |
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| CN1450600A (en) * | 2002-04-10 | 2003-10-22 | 台湾积体电路制造股份有限公司 | Method for mfg of double grid structure |
| CN102103992A (en) * | 2009-12-17 | 2011-06-22 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing gate oxide |
| CN103545186A (en) * | 2012-07-13 | 2014-01-29 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing metal gate semiconductor device |
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| CN1450600A (en) * | 2002-04-10 | 2003-10-22 | 台湾积体电路制造股份有限公司 | Method for mfg of double grid structure |
| CN102103992A (en) * | 2009-12-17 | 2011-06-22 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing gate oxide |
| CN103545186A (en) * | 2012-07-13 | 2014-01-29 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing metal gate semiconductor device |
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Effective date of registration: 20200312 Address after: 201203 5th floor, building 3, No. 18, Zhangjiang Road, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai Patentee after: Zhongxin Nanfang integrated circuit manufacturing Co., Ltd Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corp. |