CN105097025A - Electrically erasable programmable read-only memory - Google Patents
Electrically erasable programmable read-only memory Download PDFInfo
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- CN105097025A CN105097025A CN201410166937.6A CN201410166937A CN105097025A CN 105097025 A CN105097025 A CN 105097025A CN 201410166937 A CN201410166937 A CN 201410166937A CN 105097025 A CN105097025 A CN 105097025A
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- programmable read
- eeprom
- electrically erasable
- erasable programmable
- bit lines
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Abstract
The present invention provides an electrically erasable programmable read-only memory. According to the new bit line layout method of the present invention, the vertical distance between the adjacent bit lines is increased so as to reduce the capacitance between the adjacent bit lines, and the bit lines are respectively tied to different metal layers to reduce the charging and discharging stray capacitance so as to reduce the electricity consumption, reduce the noise between the bit lines, and improve the performance and the reliability.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of EEPROM (Electrically Erasable Programmable Read Only Memo) structure.
Background technology
Storer and reservoir technology are one of key technology areas promoting information age development.Along with the fast development of the Internet, wireless telephone, personal digital assistant, digital camera, digital hand-held camera, digital music player, computing machine, network etc., people constantly require better memory and memory technology.A kind of typical storer is nonvolatile memory.Even if when removing power supply, nonvolatile memory also to keep in its storage perhaps store status, and the type of some erasable non-volatile programmable memories comprises flash memory, EEPROM, EPROM, MRAM, FRAM, ferroelectric and magnetic store.
EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM, ElectricallyErasableProgrammableRead-OnlyMemory) is the storage chip that after a kind of power down, data are not lost; It on computers or specialized equipment can be wiped existing information, reprogramming.EEPROM is nonvolatile memory, and flash-EEPROM development wherein rapidly.
As shown in Figure 1, eeprom memory comprises wordline WL, bit line BL_odd, bit line BL_even and is positioned at the storage unit of wordline and bit line infall, in eeprom memory, the bearing of trend of wordline WL is vertical with the bearing of trend of bit line BL_odd, BL_even, such as, the bearing of trend of wordline WL is longitudinally, and so the bearing of trend of bit line BL_odd, bit line BL_even is laterally.Storage grid is connected with wordline WL, selects grid to be connected with other lines (not shown).
In existing EEPROM, all bit lines (BL_odd, BL_even) of this storage unit are produced in same metal level, select grid (SG) to be arranged in another metal level.But, existing hypotelorism between bit line BL_odd, BL_even, cause stray capacitance between the two excessive, and mean that this storer has little RC simultaneously and postpones and good readwrite performance for having low bit line parasitic capacitance eeprom memory.
Therefore, need to propose a kind of new eeprom memory topology layout, to solve the problem, obtain lower bit line parasitic capacitance.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of EEPROM (Electrically Erasable Programmable Read Only Memo), comprising: the wordline extended in a first direction; The odd bit lines that the second direction vertical with described first direction extends and even bitlines; Wherein adjacent described odd bit lines and described even bitlines are positioned on different surface levels.
Preferably, described odd bit lines is arranged in the first metal layer, and described even bitlines is arranged in the second metal level above described the first metal layer.Preferably, the selection grid extended along first direction is also comprised.Preferably, described selection grid is arranged in the 3rd metal level of described second metal layer.
Preferably, the electric erazable programmable read-only memory unit being positioned at described wordline and described odd bit lines and even bitlines infall is also comprised.Preferably, described electric erazable programmable read-only memory unit comprises a selection transistor and a memory transistor.Preferably, described memory transistor comprises the tunnel dielectric, floating boom, gate dielectric layer and the control gate that stack gradually.
In sum, according to the present invention, new bit line layout method is proposed, vertical range between adjacent bit lines increases, so the stray capacitance between adjacent bit lines will reduce, by bit line being formed at respectively in different metal layer, the stray capacitance reducing charging and discharging is reduced electric quantity consumption, reduces the noise between bit line and improve Performance And Reliability.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Fig. 1 is the structural representation of existing eeprom memory bit line and wordline layout;
Fig. 2 is the structural representation of the eeprom memory bit line layout according to an invention embodiment making;
Fig. 3 is the schematic diagram that the parasitic capacitance value of existing eeprom memory and eeprom memory of the present invention compares.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it will be apparent to one skilled in the art that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to illustrate that the present invention is how the problems of the prior art.Detailed being described below of obvious preferred embodiment of the present invention, but remove outside these detailed descriptions, the present invention can also have other embodiments.
Should give it is noted that term used here is only to describe specific embodiment, and be not intended to restricted root according to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative be also intended to comprise plural form.In addition, it is to be further understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.Should be understood that, providing these embodiments to be of the present inventionly disclose thorough and complete to make, and the design of these exemplary embodiments fully being conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerate the thickness in layer and region, and use the element that identical Reference numeral represents identical, thus will omit description of them.
As shown in Figure 2, be the structural representation of the eeprom memory bit line layout according to an invention embodiment making.
EEPROM (Electrically Erasable Programmable Read Only Memo) 200 comprises: the wordline extended in a first direction; The odd bit lines 201 (BL_odd) that the second direction vertical with described first direction extends and even bitlines (BL_even) 202; Wherein adjacent described odd bit lines 201 (BL_odd) and described even bitlines (BL_even) 202 are positioned on different surface levels, also comprise the selection grid (SG) 206 extended along first direction.
Exemplarily, described odd bit lines 201 (BL_odd) is arranged in the first metal layer (M1) 203, and described even bitlines (BL_even) 202 is arranged in the second metal level (M2) 204 above described the first metal layer (M1) 203.
Exemplarily, described selection grid (SG) 206 is arranged in the 3rd metal level (M3) 205 above described second metal level (M2) 204.
Exemplarily, EEPROM memory cell 200 also comprises the electric erazable programmable read-only memory unit being positioned at described wordline and described odd bit lines 201 (BL_odd) and even bitlines (BL_even) 202 infall.
In the present invention one specific embodiment, EEPROM memory cell comprises: Both primary storage devices, external memory part and word line control device; Wherein the source electrode of Both primary storage devices is connected to the main bit line 201 of EEPROM memory cell, the drain electrode of Both primary storage devices is connected to the source electrode of word line control device, the drain electrode of word line control device is connected to the source electrode of external memory part, and the drain electrode of external memory part is connected to the secondary bit line 202 of EEPROM memory cell.
Exemplarily, described electric erazable programmable read-only memory unit 200 comprises a selection transistor and a memory transistor.This selection transistor sometimes can be called as one and read transistor.A gate electrode for each selection transistor of bit line is connected to a different wordline.Memory transistor can be floating transistor.
Eeprom memory structure comprises, there is the substrate of surface region, the surface region of substrate is formed first module district and second unit district, the surface region of substrate is formed the gate dielectric layer of the first thickness, tunnel oxide is formed in part of grid pole dielectric in second unit district, gate-dielectric in first module district is formed and selects grid, the tunnel oxide in second unit district is formed floating boom, gate dielectric layer and control gate.
Exemplarily, described memory transistor 200 comprises the tunnel dielectric, floating boom, gate dielectric layer and the control gate that stack gradually.The material of gate dielectric layer can be monox or ONO, and the method for formation is thermal oxidation method, and the thickness of the gate dielectric layer usually formed is all right at tens Izods.
In the present invention one specific embodiment, adjacent bit line 201 and bit line 202 are arranged in different metal levels, bit line 201 adjacent in prior art and bit line 202 is replaced to be arranged in identical metal level, to add the vertical range of adjacent bit lines 201 and bit line 202, further reduce the electric capacity between bit line 201 and bit line 202.
Usual diffusion connects bit line.When select transistor be NMOS or N-channel transistor, this diffusion be n+ diffusion.In order to make resistance minimum, odd bit lines is connected to top-level metallic or has other conductors of the resistance lower than diffusion.In a specific embodiment of the present invention, even bitlines is connected to second layer metal.But for a person skilled in the art in integrated circuit technology, storer has much different bit lines and metal level, such as, can by two-layer or multiple layer metal in certain technique.
Each bit line has corresponding stray capacitance, also has stray capacitance between bit line.These electric capacity are distributed capacitance, are distributed on this bit line.
As shown in Figure 3, for the schematic diagram that the parasitic capacitance value of existing eeprom memory and eeprom memory of the present invention compares, be arranged in different metal layer by adjacent bit lines in the present invention to replace being arranged in identical metal level, the vertical range of bit line time increases, electric capacity between adjacent bit lines reduces, and the electric capacity of cell bit line reduces 20%.
In sum, according to the present invention, new bit line layout method is proposed, vertical range between adjacent bit lines increases, so the electric capacity between adjacent bit lines will reduce, by bit line being tied up respectively to different metal layer, the stray capacitance reducing charging and discharging is reduced electric quantity consumption, reduces the noise between bit line and improve Performance And Reliability.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (7)
1. an EEPROM (Electrically Erasable Programmable Read Only Memo), comprising:
The wordline extended in a first direction;
The odd bit lines that the second direction vertical with described first direction extends and even bitlines;
Wherein adjacent described odd bit lines and described even bitlines are positioned on different surface levels.
2. EEPROM (Electrically Erasable Programmable Read Only Memo) according to claim 1, is characterized in that, described odd bit lines is arranged in the first metal layer, and described even bitlines is arranged in the second metal level above described the first metal layer.
3. EEPROM (Electrically Erasable Programmable Read Only Memo) according to claim 2, is characterized in that, also comprises the selection grid extended along first direction.
4. EEPROM (Electrically Erasable Programmable Read Only Memo) according to claim 3, is characterized in that, described selection grid is arranged in the 3rd metal level of described second metal layer.
5. EEPROM (Electrically Erasable Programmable Read Only Memo) according to claim 1, is characterized in that, also comprises the electric erazable programmable read-only memory unit being positioned at described wordline and described odd bit lines and even bitlines infall.
6. EEPROM (Electrically Erasable Programmable Read Only Memo) according to claim 5, is characterized in that, described electric erazable programmable read-only memory unit comprises a selection transistor and a memory transistor.
7. EEPROM (Electrically Erasable Programmable Read Only Memo) according to claim 6, is characterized in that, described memory transistor comprises the tunnel dielectric, floating boom, gate dielectric layer and the control gate that stack gradually.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410166937.6A CN105097025A (en) | 2014-04-24 | 2014-04-24 | Electrically erasable programmable read-only memory |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410166937.6A CN105097025A (en) | 2014-04-24 | 2014-04-24 | Electrically erasable programmable read-only memory |
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| CN105097025A true CN105097025A (en) | 2015-11-25 |
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| CN201410166937.6A Pending CN105097025A (en) | 2014-04-24 | 2014-04-24 | Electrically erasable programmable read-only memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112837723A (en) * | 2019-11-22 | 2021-05-25 | 上海磁宇信息科技有限公司 | Magnetic random access memory array with staggered metal bit line routing |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6421267B1 (en) * | 2001-04-24 | 2002-07-16 | Macronix International Co., Ltd. | Memory array architecture |
| US20060244041A1 (en) * | 2005-04-28 | 2006-11-02 | Renesas Technology Corp. | Programmable nonvolatile memory and semiconductor integrated circuit device |
| CN102768857A (en) * | 2012-07-24 | 2012-11-07 | 上海宏力半导体制造有限公司 | Semiconductor memory |
| CN103745747A (en) * | 2014-01-09 | 2014-04-23 | 上海华虹宏力半导体制造有限公司 | Electrically erasable and programmable read-only memory and bit line wiring method |
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2014
- 2014-04-24 CN CN201410166937.6A patent/CN105097025A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6421267B1 (en) * | 2001-04-24 | 2002-07-16 | Macronix International Co., Ltd. | Memory array architecture |
| US20060244041A1 (en) * | 2005-04-28 | 2006-11-02 | Renesas Technology Corp. | Programmable nonvolatile memory and semiconductor integrated circuit device |
| CN102768857A (en) * | 2012-07-24 | 2012-11-07 | 上海宏力半导体制造有限公司 | Semiconductor memory |
| CN103745747A (en) * | 2014-01-09 | 2014-04-23 | 上海华虹宏力半导体制造有限公司 | Electrically erasable and programmable read-only memory and bit line wiring method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112837723A (en) * | 2019-11-22 | 2021-05-25 | 上海磁宇信息科技有限公司 | Magnetic random access memory array with staggered metal bit line routing |
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Application publication date: 20151125 |