CN105095610B - A kind of method and device of adjustment circuit simulation time step-length - Google Patents
A kind of method and device of adjustment circuit simulation time step-length Download PDFInfo
- Publication number
- CN105095610B CN105095610B CN201510614056.0A CN201510614056A CN105095610B CN 105095610 B CN105095610 B CN 105095610B CN 201510614056 A CN201510614056 A CN 201510614056A CN 105095610 B CN105095610 B CN 105095610B
- Authority
- CN
- China
- Prior art keywords
- node
- length
- cycle
- dervative
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004088 simulation Methods 0.000 title claims abstract description 80
- 238000000034 method Methods 0.000 title claims abstract description 26
- 230000033228 biological regulation Effects 0.000 claims abstract description 25
- 239000011159 matrix material Substances 0.000 claims abstract description 19
- 238000004422 calculation algorithm Methods 0.000 description 4
- 238000004364 calculation method Methods 0.000 description 3
- 238000004321 preservation Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 238000012935 Averaging Methods 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
Landscapes
- Management, Administration, Business Operations System, And Electronic Commerce (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention discloses a kind of method and device of adjustment circuit simulation time step-length, this method includes：Identify the cycle node in circuit node；The historical data of the complete cycle of the cycle node is recorded, is stored in historical information matrix；The second dervative of cycle node according to being calculated current time in the historical data；By the second dervative and the number of the cycle node, the step-length regulation coefficient of circuit-simulation time is determined；The step-length of subsequent time simulation time is adjusted by the step-length regulation coefficient and standard step-length.The application is adjusted using cycle node information to the simulation time step-length of circuit, the iterations of solution circuit equation group can effectively be reduced, reduce unnecessary step-length adjustment, the simulation velocity of circuit is greatly improved, and then accelerate verifying speed and the commercialization of chip.
Description
Technical field
The present invention relates to chip circuit simulation technical field, more particularly to a kind of side of adjustment circuit simulation time step-length
Method and device.
Background technology
With the drastically contradiction between expansion, and the demand of chip product of chip circuit scale, the emulation to circuit
Speed proposes higher requirement with precision.In order to meet the needs of chip circuit simulation velocity, each emulator producer utilizes the right side
The modes such as end item convergence detection improve the availability of time step, it is expected to improve the convergent speed of circuit equation group right-hand vector,
And then accelerate the simulation velocity of circuit.But due to having the presence of cycle node, the time step of selection, actual effect all the time can not
Satisfactory, the decline of time step forecasting efficiency, which further results in simulation velocity, to improve.
Therefore it provides a kind of method and device of adjustment circuit simulation time step-length, to improve the emulation of chip circuit speed
Degree is necessary.
The content of the invention
It is an object of the invention to provide a kind of method and device of adjustment circuit simulation time step-length, it is therefore intended that improves core
The simulation velocity of piece circuit.
In order to solve the above technical problems, the present invention provides a kind of method of adjustment circuit simulation time step-length, including：
Identify the cycle node in circuit node；
The historical data of the complete cycle of the cycle node is recorded, is stored in historical information matrix；
The second dervative of cycle node according to being calculated current time in the historical data；
By the second dervative and the number of the cycle node, the step-length adjustment for determining circuit-simulation time is
Number；
The step-length of subsequent time simulation time is adjusted by the step-length regulation coefficient and standard step-length.
Alternatively, the cycle node identified in circuit node includes：
The emulation historical information of combined circuit node, identify the cycle node in circuit node.
Alternatively, the second dervative bag of the cycle node according to being calculated current time in the historical data
Include：
According to current time and the emulation data of preceding preset number, the historical information matrix is matched, to current time
The section of the cycle node is judged；
With reference to the block information of the cycle node, the second dervative of cycle node described in current time is calculated.
Alternatively, the block information of the cycle node with reference to described in, cycle node described in current time is calculated
Second dervative includes：
If in the historical data exist with current time simulation value identical data, by two corresponding to identical data
Second dervative of the order derivative as the cycle node；Otherwise the second order of two data adjacent with current time simulation value is led
Second dervative of several average value as the cycle node.
Alternatively, it is described by the second dervative and the number of the cycle node, determine circuit-simulation time
Step-length regulation coefficient includes：
The value of the second dervative is judged with predetermined threshold value, when less than the predetermined threshold value, by second dervative
Algebraic value be entered as 1；Otherwise, the algebraic value of the second dervative is entered as 0；
Calculate the sum of the algebraic value of the second dervative of all cycle nodes；
By the algebraic value and with the number of the cycle node ratio, as the step-length regulation coefficient.
Present invention also offers a kind of device of adjustment circuit simulation time step-length, including：
Identification module, for identifying the cycle node in circuit node；
Historical information matrix is arrived in logging modle, the historical data of the complete cycle for recording the cycle node, storage
In；
Computing module, the second dervative for cycle node described in current time is calculated according to the historical data；
Determining module, for the number by the second dervative and the cycle node, determine circuit-simulation time
Step-length regulation coefficient；
Adjusting module, for the step-length by the step-length regulation coefficient and standard step-length to subsequent time simulation time
It is adjusted.
Alternatively, the identification module is used to identify that the cycle node in circuit node includes：
The identification module is specifically used for the emulation historical information of combined circuit node, identifies the cycle in circuit node
Node.
Alternatively, the computing module includes：
Judging unit, for the emulation data according to current time and preceding preset number, match the historical information square
Battle array, judges the section of cycle node described in current time；
Computing unit, for the block information with reference to the cycle node, cycle node described in current time is calculated
Second dervative.
Alternatively, the computing unit is used for the block information with reference to the cycle node, and current time institute is calculated
Stating the second dervative of cycle node includes：
If the computing unit be specifically used for the historical data in exist with current time simulation value identical data,
Second dervative using the second dervative corresponding to identical data as the cycle node；Otherwise will be with current time simulation value phase
Second dervative of the average value of the second dervative of two adjacent data as the cycle node.
Alternatively, the determining module includes：
Assignment unit, for the value of the second dervative to be judged with predetermined threshold value, when less than the predetermined threshold value
When, the algebraic value of second dervative is entered as 1；Otherwise, the algebraic value of the second dervative is entered as 0；
Computing unit, the sum of the algebraic value of the second dervative for calculating all cycle nodes；
Determining unit, for by the algebraic value and with the number of the cycle node ratio, as the step-length
Regulation coefficient.
The method and device of adjustment circuit simulation time step-length provided by the present invention, by identifying in circuit node
Cycle node, the historical information of the complete cycle of record period node, when circuit carries out the simulation calculation of subsequent time, utilize
The historical data of preservation, with reference to the operation values at moment before, extrapolate the time step of subsequent time.The application is tied using the cycle
Point information is adjusted to the simulation time step-length of circuit, can effectively be reduced the iterations of solution circuit equation group, be reduced
Unnecessary step-length adjustment, is greatly improved the simulation velocity of circuit, and then accelerate the verifying speed and product of chip
Change.
Brief description of the drawings
Fig. 1 is a kind of flow of embodiment of the method for adjustment circuit simulation time step-length provided by the present invention
Figure；
Fig. 2 is history in a kind of embodiment of the method for adjustment circuit simulation time step-length provided by the present invention
The schematic diagram of information matrix；
Fig. 3 is a kind of flow of embodiment of the method for adjustment circuit simulation time step-length provided by the present invention
Figure；
Fig. 4 is slope in a kind of embodiment of the method for adjustment circuit simulation time step-length provided by the present invention
Compare figure；
Fig. 5 is a kind of a kind of embodiment of the device of adjustment circuit simulation time step-length provided by the present invention
Structured flowchart.
Embodiment
The core of the present invention is to provide a kind of method and device of adjustment circuit simulation time step-length, mainly for chip electricity
Adjustment in the emulation of road to time step.
In order that those skilled in the art more fully understand the present invention program, with reference to the accompanying drawings and detailed description
The present invention is described in further detail.Obviously, described embodiment is only part of the embodiment of the present invention, rather than
Whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not making creative work premise
Lower obtained every other embodiment, belongs to the scope of protection of the invention.
A kind of flow chart of embodiment of the method for adjustment circuit simulation time step-length provided by the present invention is such as
Shown in Fig. 1, this method includes：
Step S101：Identify the cycle node in circuit node；
Specifically, the starting stage is emulated in chip circuit, can be with the emulation historical information of combined circuit node, analytical cycle
The characteristics of node, so as to be recognized accurately whether a certain node is cycle node from all nodes.
Step S102：The historical data of the complete cycle of the cycle node is recorded, is stored in historical information matrix；
The schematic diagram of specific embodiment of historical information matrix a kind of is as shown in Fig. 2 wherein, the NodeZ indication circuit cycles
Signal compiles the node for Z, and V* represents the * history value of some node, and Dx represents the absolute of x-th of second dervative of node
Value, the chained list length of each node is not necessarily.Historical information matrix is made up of multiple chained lists, is dynamically adapted, with suitable
Answer the emulation demand of different circuit scales.
Step S103：The second dervative of cycle node according to being calculated current time in the historical data；
Step S104：By the second dervative and the number of the cycle node, the step of circuit-simulation time is determined
Long regulation coefficient；
Step S105：The step-length of subsequent time simulation time is carried out by the step-length regulation coefficient and standard step-length
Adjustment.
The method of adjustment circuit simulation time step-length provided by the present invention, by identifying that the cycle in circuit node ties
Point；The historical information of the complete cycle of record period node, when circuit carries out the simulation calculation of subsequent time, utilize preservation
Historical data, with reference to the operation values at moment before, extrapolate the time step of subsequent time.The application utilizes cycle node information
The simulation time step-length of circuit is adjusted, can effectively reduce the iterations of solution circuit equation group, it is unnecessary to reduce
Step-length adjustment, the simulation velocity of circuit is greatly improved, and then accelerate verifying speed and the commercialization of chip.
On the basis of a upper embodiment, the another kind of the method for adjustment circuit simulation time step-length provided by the present invention
The flow chart of embodiment is as shown in figure 3, this method includes：
Step S201：The emulation historical information of combined circuit node, identify the cycle node in circuit node；
Step S202：The historical data of a complete cycle of the cycle node is recorded, historical information matrix is arrived in storage
In；
Step S203：According to current time and the emulation data of preceding preset number, the historical information matrix is matched, it is right
The section of cycle node is judged described in current time；
Specifically, when the cycle starts next time, four data Fx according to current time and beforetn、Fxtn-1、
Fxtn-2、Fxtn-3, historical data information matrix is matched, carries out interval selection, as shown in Fig. 4 slope ratios compared with figure, final choice area
Between interval ranges of the A as periodic knot described in current time.
Step S204：With reference to the block information of the cycle node, two of cycle node described in current time is calculated
Order derivative；
After selecting section, the second dervative at each node current time is calculated.If in the historical data
In the presence of with current time simulation value identical data, then using the second dervative corresponding to identical data as the cycle node
Second dervative；Otherwise the average value of the second dervative of two data adjacent with current time simulation value is tied as the cycle
The second dervative of point.
Specifically, pass through：
Calculate the second dervative at current time, wherein DXn-1、DXnRepresent currency pair
The absolute value of the second dervative in the section of historical information matrix is answered, if current time simulation value is equal to historical data using equal
Second dervative, otherwise two neighboring derivative be averaging.
Step S205：The value of the second dervative is judged with predetermined threshold value, will when less than the predetermined threshold value
The algebraic value of second dervative is entered as 1；Otherwise, the algebraic value of the second dervative is entered as 0；
Step S206：Calculate the sum of the algebraic value of the second dervative of all cycle nodes；
Step S207：By the algebraic value and with the number of the cycle node ratio, adjusted as the step-length
Coefficient；
By the ratio between the algebraical sum of the second dervative of all cycle nodes and cycle number of network nodes, then formula can be utilized：
Δtn+1=k* Δs tnAnd
The regulation coefficient k of step-length is obtained, wherein △ tn represent the time step at moment at that time.
It is pointed out that when the k values being calculated are less than or equal to 0.1, force k value being entered as 0.1.
Step S208：The step-length of subsequent time simulation time is carried out by the step-length regulation coefficient and standard step-length
Adjustment.
In a particular embodiment, the application circuit-simulation time step-length adjustment algorithm realizes that structure can include：Week
Phase node historical information matrix and adjustment algorithm；Wherein, cycle node historical information matrix is used for the complete of retention cycle node
The historical information of complete cycle, there is provided used to adjustment algorithm；Adjustment algorithm is used for the history of the node complete cycle according to reservation
Information, with reference to the operation values preserved in this cycle, reckoning obtains time step.
The device of adjustment circuit simulation time step-length provided in an embodiment of the present invention is introduced below, it is described below
The device of adjustment circuit simulation time step-length can mutually corresponding ginseng with the method for above-described adjustment circuit simulation time step-length
According to.A kind of a kind of structured flowchart of embodiment of the device of adjustment circuit simulation time step-length provided by the present invention is such as
Shown in Fig. 5, the device includes：
Identification module 100, for identifying the cycle node in circuit node；
Wherein, the identification module 100 is specifically used for the emulation historical information of combined circuit node, identifies circuit node
In cycle node.
Historical information square is arrived in logging modle 200, the historical data of the complete cycle for recording the cycle node, storage
In battle array；
Computing module 300, the second order for cycle node described in current time is calculated according to the historical data are led
Number；
Determining module 400, for the number by the second dervative and the cycle node, when determining circuit simulation
Between step-length regulation coefficient；
Adjusting module 500, for by the step-length regulation coefficient and standard step-length to subsequent time simulation time
Step-length is adjusted.
The device of adjustment circuit simulation time step-length provided by the present invention, by identifying that the cycle in circuit node ties
Point, the historical information of the complete cycle of record period node, when circuit carries out the simulation calculation of subsequent time, utilize preservation
Historical data, with reference to the operation values at moment before, extrapolate the time step of subsequent time.The application utilizes cycle node information
The simulation time step-length of circuit is adjusted, can effectively reduce the iterations of solution circuit equation group, it is unnecessary to reduce
Step-length adjustment, the simulation velocity of circuit is greatly improved, and then accelerate verifying speed and the commercialization of chip.
Specifically, above-mentioned computing module 300 may further include：
Judging unit 301, for the emulation data according to current time and preceding preset number, match the historical information
Matrix, the section of cycle node described in current time is judged；
Computing unit 302, for the block information with reference to the cycle node, cycle knot described in current time is calculated
The second dervative of point.
Wherein, if the computing unit is specifically used for existing and current time simulation value identical number in the historical data
According to the then second dervative using the second dervative corresponding to identical data as the cycle node；Otherwise will be imitated with current time
Second dervative of the average value of the second dervative of two adjacent data of true value as the cycle node.
Specifically, above-mentioned determining module 400 may further include：
Assignment unit 401, for the value of the second dervative to be judged with predetermined threshold value, when less than the default threshold
During value, the algebraic value of second dervative is entered as 1；Otherwise, the algebraic value of the second dervative is entered as 0；
Computing unit 402, the sum of the algebraic value of the second dervative for calculating all cycle nodes；
Determining unit 403, for by the algebraic value and with the number of the cycle node ratio, as the step
Long regulation coefficient.
The device of adjustment circuit simulation time step-length provided by the present invention is corresponding with the above method, no longer superfluous herein
State.
Each embodiment is described by the way of progressive in this specification, what each embodiment stressed be with it is other
The difference of embodiment, between each embodiment same or similar part mutually referring to.
The foregoing description of the disclosed embodiments, professional and technical personnel in the field are enable to realize or using the present invention.
A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope caused.
Claims (10)
- A kind of 1. method of adjustment circuit simulation time step-length, it is characterised in that including：Identify the cycle node in circuit node；The historical data of the complete cycle of the cycle node is recorded, is stored in historical information matrix；The second dervative of history value corresponding to the cycle node according to being calculated current time in the historical data；By the second dervative and the number of the cycle node, the step-length regulation coefficient of circuit-simulation time is determined；The step-length of subsequent time simulation time is adjusted by the step-length regulation coefficient and standard step-length.
- 2. the method for adjustment circuit simulation time step-length as claimed in claim 1, it is characterised in that described to identify circuit knot Cycle node in point includes：The emulation historical information of combined circuit node, identify the cycle node in circuit node.
- 3. the method for adjustment circuit simulation time step-length as claimed in claim 1 or 2, it is characterised in that described in the basis The second dervative that history value corresponding to cycle node described in current time is calculated in historical data includes：According to current time and the emulation data of preceding preset number, the historical information matrix is matched, to described in current time The section of cycle node is judged；With reference to the block information of the cycle node, the second order of history value corresponding to cycle node described in current time is calculated Derivative.
- 4. the method for adjustment circuit simulation time step-length as claimed in claim 3, it is characterised in that the cycle with reference to described in The block information of node, the second dervative of history value corresponding to cycle node described in current time, which is calculated, to be included：If in the historical data exist with current time simulation value identical data, the second order corresponding to identical data is led Second dervative of the number as history value corresponding to the cycle node；Otherwise by two data adjacent with current time simulation value Second dervative second dervative of the average value as history value corresponding to the cycle node.
- 5. the method for adjustment circuit simulation time step-length as claimed in claim 4, it is characterised in that described to pass through the second order The number of derivative and the cycle node, determining the step-length regulation coefficient of circuit-simulation time includes：The value of the second dervative is judged with predetermined threshold value, when less than the predetermined threshold value, by the generation of second dervative Numerical value is entered as 1；Otherwise, the algebraic value of the second dervative is entered as 0；Calculate the sum of the algebraic value of the second dervative of history value corresponding to all cycle nodes；By the algebraic value and with the number of the cycle node ratio, as the step-length regulation coefficient；When the value of the step-length regulation coefficient is less than or equal to 0.1, the value by the step-length regulation coefficient is forced to be entered as 0.1。
- A kind of 6. device of adjustment circuit simulation time step-length, it is characterised in that including：Identification module, for identifying the cycle node in circuit node；Logging modle, the historical data of the complete cycle for recording the cycle node, is stored in historical information matrix；Computing module, two for history value corresponding to cycle node described in current time is calculated according to the historical data Order derivative；Determining module, for the number by the second dervative and the cycle node, determine the step of circuit-simulation time Long regulation coefficient；Adjusting module, for being carried out by the step-length regulation coefficient and standard step-length to the step-length of subsequent time simulation time Adjustment.
- 7. the device of adjustment circuit simulation time step-length as claimed in claim 6, it is characterised in that the identification module is used for Identify that the cycle node in circuit node includes：The identification module is specifically used for the emulation historical information of combined circuit node, identifies the cycle knot in circuit node Point.
- 8. the device of adjustment circuit simulation time step-length as claimed in claims 6 or 7, it is characterised in that the computing module Including：Judging unit, for the emulation data according to current time and preceding preset number, the historical information matrix is matched, it is right The section of cycle node is judged described in current time；Computing unit, for the block information with reference to the cycle node, it is corresponding that cycle node described in current time is calculated History value second dervative.
- 9. the device of adjustment circuit simulation time step-length as claimed in claim 8, it is characterised in that the computing unit is used for With reference to the block information of the cycle node, the second dervative of history value corresponding to cycle node described in current time is calculated Including：If the computing unit be specifically used for the historical data in exist with current time simulation value identical data, by phase With second dervative of the second dervative corresponding to data as history value corresponding to the cycle node；Otherwise will be with current time Second dervative of the average value of the second dervative of two adjacent data of simulation value as history value corresponding to the cycle node.
- 10. the device of adjustment circuit simulation time step-length as claimed in claim 9, it is characterised in that the determining module bag Include：Assignment unit,, will when less than the predetermined threshold value for the value of the second dervative to be judged with predetermined threshold value The algebraic value of second dervative is entered as 1；Otherwise, the algebraic value of the second dervative is entered as 0；Computing unit, for calculating the sum of the algebraic value of the second dervative of history value corresponding to all cycle nodes；Determining unit, for by the algebraic value and with the number of the cycle node ratio, being adjusted as the step-length Coefficient；When the value of the step-length regulation coefficient is less than or equal to 0.1, the value by the step-length regulation coefficient is forced to be entered as 0.1。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510614056.0A CN105095610B (en) | 2015-09-23 | 2015-09-23 | A kind of method and device of adjustment circuit simulation time step-length |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510614056.0A CN105095610B (en) | 2015-09-23 | 2015-09-23 | A kind of method and device of adjustment circuit simulation time step-length |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105095610A CN105095610A (en) | 2015-11-25 |
| CN105095610B true CN105095610B (en) | 2018-04-10 |
Family
ID=54576035
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510614056.0A Active CN105095610B (en) | 2015-09-23 | 2015-09-23 | A kind of method and device of adjustment circuit simulation time step-length |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105095610B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115459897B (en) * | 2022-09-02 | 2024-06-04 | 南方电网科学研究院有限责任公司 | Step length synchronous calibration method and device in power real-time simulation and related equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101694675A (en) * | 2009-10-22 | 2010-04-14 | 中兴通讯股份有限公司 | Circuit simulation method and system |
| CN102411663A (en) * | 2011-12-31 | 2012-04-11 | 中国科学院微电子研究所 | Calculation multiplexing method, equipment and system for circuit fine tuning accelerating circuit simulation |
| CN102508984A (en) * | 2011-11-30 | 2012-06-20 | 中国科学院微电子研究所 | Simulation acceleration method, device and system for circuit fine adjustment |
| CN103034750A (en) * | 2011-09-30 | 2013-04-10 | 济南概伦电子科技有限公司 | Simulation method and system of repeat circuit |
-
2015
- 2015-09-23 CN CN201510614056.0A patent/CN105095610B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101694675A (en) * | 2009-10-22 | 2010-04-14 | 中兴通讯股份有限公司 | Circuit simulation method and system |
| CN103034750A (en) * | 2011-09-30 | 2013-04-10 | 济南概伦电子科技有限公司 | Simulation method and system of repeat circuit |
| CN102508984A (en) * | 2011-11-30 | 2012-06-20 | 中国科学院微电子研究所 | Simulation acceleration method, device and system for circuit fine adjustment |
| CN102411663A (en) * | 2011-12-31 | 2012-04-11 | 中国科学院微电子研究所 | Calculation multiplexing method, equipment and system for circuit fine tuning accelerating circuit simulation |
Non-Patent Citations (1)
| Title |
|---|
| 一种物理链路检测电路设计及仿真模型实现方法;李仁刚，王恩东等;《科学技术与工程》;20101231;第10卷(第35期);第8816-8821页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105095610A (en) | 2015-11-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20220129288A1 (en) | Method and apparatus for determining the capacity of an application cluster | |
| CN110287942A (en) | Training method, age estimation method and the corresponding device of age estimation model | |
| JP2011524126A5 (en) | ||
| US20160349992A1 (en) | Provisioning advisor | |
| CN104298541A (en) | Data distribution algorithm and data distribution device for cloud storage system | |
| CN104798049B (en) | operation management device and operation management method | |
| CN103309917A (en) | Path searching method and path search device | |
| CN104914862A (en) | Path planning algorithm based on target direction constraint | |
| US20200027013A1 (en) | Model estimation system, method, and program | |
| CN105095610B (en) | A kind of method and device of adjustment circuit simulation time step-length | |
| TW201732695A (en) | Method for processing machine abnormality, method for adjusting learning rate, and device | |
| CN111290699A (en) | Data migration method, device and system | |
| JP2022032964A5 (en) | ||
| CN106682414A (en) | Method and device for establishing timing sequence prediction model | |
| Kim et al. | A highly-accurate and low-overhead prediction model for transfer throughput optimization | |
| CN108804719A (en) | Digital circuit aging emulation mode and device | |
| CN102571423A (en) | Generalized stochastic high-level Petri net (GSHLPN)-based network data transmission modeling and performance analysis method | |
| CN106201655B (en) | Virtual machine distribution method and virtual machine distribution system | |
| CN107370149A (en) | Determine the method and system of power system load reduction | |
| US20060010411A1 (en) | Method for netlist path characteristics extraction | |
| CN104507095B (en) | Indoor AP dispositions methods based on user location distribution | |
| CN108259583B (en) | Data dynamic migration method and device | |
| CN108400907A (en) | A kind of link packet drop rate inference method under uncertain network environment | |
| CN104184674B (en) | A kind of network analog task load balance method under heterogeneous computing environment | |
| CN104657558B (en) | The method for extracting LOD effect models |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |