CN105093736A - IPS array substrate, manufacture method thereof and display device - Google Patents

IPS array substrate, manufacture method thereof and display device Download PDF

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Publication number
CN105093736A
CN105093736A CN201510412192.1A CN201510412192A CN105093736A CN 105093736 A CN105093736 A CN 105093736A CN 201510412192 A CN201510412192 A CN 201510412192A CN 105093736 A CN105093736 A CN 105093736A
Authority
CN
China
Prior art keywords
electrode
signal wire
array base
base palte
touch control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510412192.1A
Other languages
Chinese (zh)
Inventor
许睿
董学
陈小川
王磊
卢鹏程
李昌峰
丁小梁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Beijing BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201510412192.1A priority Critical patent/CN105093736A/en
Publication of CN105093736A publication Critical patent/CN105093736A/en
Priority to PCT/CN2015/098722 priority patent/WO2017008450A1/en
Priority to US15/305,016 priority patent/US10197837B2/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
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    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1362—Active matrix addressed cells
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Computer Hardware Design (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The invention relates to the technical field of touch-control display and discloses an IPS array substrate, a manufacture method thereof and a display device. Touch-control electrodes are reused as common electrodes of the IPS array substrate so that embedded touch control is realized and thickness of a touch display device is decreased. Signal lines are electrically connected with the touch-control electrodes in a one-to-one corresponding mode. During the time period for touch control in each frame for time display, variation in self capacitances of the touch-control electrodes is detected by corresponding signal lines in order to determine touch positions. Additionally, a touch-control electrode corresponding to a detection signal is obtained through each signal line due to the fact that the signal lines are in a one-to-one correspondence with the touch-control electrodes. Even if the multiple touch-control electrodes are touched simultaneously, multiple touch positions can be precisely determined so that ghost points disappear in self-capacitance touch-control detection in the prior art.

Description

IPS array base palte and preparation method thereof, display device
Technical field
The present invention relates to technical field of touch-control display, particularly relate to a kind of IPS array base palte and preparation method thereof, display device.
Background technology
In touch screen technology, relative to resistance type touch control screen, capacitance type touch control screen has that the life-span is long, transmittance is high, can support the advantages such as multi-point touch.Further, capacitance type touch control screen to noise and over the ground stray capacitance also have good inhibiting effect.Therefore, capacitance type touch control screen has become one of focus of nowadays touch screen manufacture.Capacitance type touch control screen comprises self-tolerant touch screen and mutual tolerance formula touch screen, because self-tolerant touch screen only needs one deck touch control electrode, by detecting whether the changing from visibly moved of touch control electrode, can realize touching and detecting, have structure simple, be convenient to the advantages such as realization.
In recent years, the thickness of display device is more and more thinner, In-cell touch panel display part is by being embedded in display screen inside by the touch control electrode of touch screen, reach the object of the thickness of thinning display device, greatly reduce again the manufacturing cost of touch display device simultaneously, be subject to the favor of Ge great panel producer.
Summary of the invention
The invention provides a kind of IPS array base palte and preparation method thereof, display device, in order to realize embedded touch display.
For solving the problems of the technologies described above, a kind of IPS array base palte is provided in the embodiment of the present invention, comprise viewing area and the non-display area being positioned at viewing area periphery, the viewing area of described array base palte comprises multiple pixel cell, each pixel cell comprises slit public electrode and slit pixel electrode, one frame picture display time of described array base palte comprises displaying time section and touch-control time period, described multiple public electrode is multiplexed with multiple touch control electrode, the public electrode of the corresponding multiple electric connection of each touch control electrode, described array base palte also comprises:
Many signal line, described signal wire and touch control electrode one_to_one corresponding are electrically connected, in the displaying time section of a frame picture display time, public voltage signal is transmitted to touch control electrode by the signal wire of correspondence, in the touch-control time period of a frame picture display time, whether the self-capacitance being detected touch control electrode by the signal wire of correspondence is changed.
Array base palte as above, preferably, described array base palte is thin-film transistor array base-plate, described array base palte comprises grid line and the data line of transverse and longitudinal cross-distribution, for limiting the region at described multiple pixel cell place, each pixel cell also comprises thin film transistor (TFT), and slit and the described data line of described public electrode and pixel electrode are almost parallel;
The gate electrode of described signal wire and described grid line and described thin film transistor (TFT) is for arrange with material with layer, or with the source electrode of described data line and described thin film transistor (TFT), leaking electricity very is arranged with material with layer.
Array base palte as above, preferably, is provided with insulation course between described signal wire and touch control electrode, and described touch control electrode is electrically connected with corresponding signal wire by the via hole in described insulation course.
Array base palte as above, preferably, described insulation course comprises gate insulation layer and passivation layer;
Described array base palte specifically comprises:
Underlay substrate;
Be arranged on the gate electrode of many grid lines on described underlay substrate, many signal line and thin film transistor (TFT), described grid line, signal wire and gate electrode are for arrange with material with layer;
Cover the gate insulation layer of described grid line, signal wire and gate electrode;
Be arranged on active layer pattern on described gate insulation layer, thin film transistor (TFT);
The source electrode of a plurality of data lines and thin film transistor (TFT), drain electrode, the source electrode of described data line and thin film transistor (TFT) is very arranged with material with layer with leaking electricity, and described source electrode and drain electrode are overlapped on the relative both sides of described active layer;
Be overlapped on the pixel electrode on described drain electrode;
Cover the passivation layer of described thin film transistor (TFT) and pixel electrode;
Be arranged on the multiple public electrodes on described passivation layer, the projection of described public electrode on described underlay substrate has overlapping region with the projection of corresponding signal wire on described underlay substrate, and described public electrode is electrically connected with corresponding signal wire by the via hole running through described gate insulation layer and passivation layer.
Array base palte as above, preferably, described touch control electrode is overlapped on corresponding signal wire, in electrical contact.
Array base palte as above, preferably, the part that described signal wire is positioned at viewing area be arranged in parallel with described grid line, or the part that described signal wire is positioned at viewing area be arranged in parallel with described data line.
Array base palte as above, preferably, described signal wire extends to non-display area from viewing area; Described array base palte is rectangular configuration, and described signal wire extends to the side, place, long limit of array base palte from viewing area.
A kind of method for making of IPS array base palte as above is also provided in the embodiment of the present invention, described array base palte comprises viewing area and is positioned at the non-display area of viewing area periphery, the viewing area that described method for making is included in array base palte forms the step of multiple pixel cell, each pixel cell comprises slit public electrode and slit pixel electrode, one frame picture display time of described array base palte comprises displaying time section and touch-control time period, described multiple public electrode is multiplexed with multiple touch control electrode, the public electrode of the corresponding multiple electric connection of each touch control electrode, described method for making also comprises:
Form many signal line, described signal wire and touch control electrode one_to_one corresponding are electrically connected, in the displaying time section of a frame picture display time, public voltage signal is transmitted to touch control electrode by the signal wire of correspondence, in the touch-control time period of a frame picture display time, whether the self-capacitance being detected touch control electrode by the signal wire of correspondence is changed.
Method for making as above, preferably, described array base palte is thin-film transistor array base-plate, described array base palte comprises grid line and the data line of transverse and longitudinal cross-distribution, for limiting the region at described multiple pixel cell place, each pixel cell also comprises thin film transistor (TFT), and slit and the described data line of described public electrode and pixel electrode are almost parallel;
The step forming many signal line is specially:
By forming the gate electrode of described signal wire, described grid line and described thin film transistor (TFT) to the patterning processes of same grid metal level, or, by forming source electrode, the drain electrode of described signal wire, described data line and described thin film transistor (TFT) to the patterning processes of same source and drain metal level.
Method for making as above, preferably, described method for making specifically comprises:
Form grid metal level, patterning processes is carried out to described grid metal level, form the pattern comprising described signal wire;
Form insulation course on the signal line, patterning processes is carried out to described insulation course, form via hole;
Described insulation course forms transparency conducting layer, carries out patterning processes to described transparency conducting layer, form multiple public electrode, described public electrode is electrically connected with corresponding signal wire by the via hole in described insulation course.
Method for making as above, preferably, described insulation course comprises gate insulation layer and passivation layer;
Described method for making specifically comprises:
One underlay substrate is provided;
Described underlay substrate is formed grid metal level, patterning processes is carried out to described grid metal level, form the gate electrode of many grid lines, many signal line and thin film transistor (TFT);
Form the gate insulation layer covering described grid line, signal wire and gate electrode;
Described gate insulation layer is formed the active layer pattern of thin film transistor (TFT);
Described active layer is formed source and drain metal level, patterning processes is carried out to described source and drain metal level, form source electrode, the drain electrode of a plurality of data lines and thin film transistor (TFT);
Form pixel electrode, described pixel electrode is overlapped on the pixel electrode on described drain electrode;
Form the passivation layer covering described thin film transistor (TFT) and pixel electrode;
Patterning processes is carried out to described passivation layer and gate insulation layer, forms via hole, expose described signal wire;
Described passivation layer forms multiple public electrode, the projection of described public electrode on described underlay substrate has overlapping region with the projection of corresponding signal wire on described underlay substrate, and described public electrode is electrically connected with corresponding signal wire by the via hole running through described gate insulation layer and passivation layer.
Method for making as above, preferably, described method for making specifically comprises:
Form grid metal level, patterning processes is carried out to described grid metal level, form the pattern comprising described signal wire;
Form transparency conducting layer, carry out patterning processes, form multiple public electrode to described transparency conducting layer, described touch control electrode is overlapped on corresponding signal wire, in electrical contact.
Also provide a kind of display device in the embodiment of the present invention, adopt IPS array base palte as above.
The beneficial effect of technique scheme of the present invention is as follows:
In technique scheme, the public electrode of IPS array base palte is multiplexed with touch control electrode, can embedded touch be realized, the thickness of thinning touch display part.Meanwhile, the ghost point phenomenon that self-tolerant touch control detection in prior art there will be can also be overcome, shorten detection time, improve touch-control sensitivity.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 represents the structural representation of IPS array base palte in the embodiment of the present invention;
Fig. 2 represents the structural representation one of a pixel cell of IPS array base palte in the embodiment of the present invention;
Fig. 3 represents the cut-open view one of Fig. 2 along A-A;
Fig. 4 represents the cut-open view one of Fig. 2 along B-B;
Fig. 5 represents the structural representation two of a pixel cell of IPS array base palte in the embodiment of the present invention;
Fig. 6 represents the cut-open view of Fig. 2 along B-B;
Fig. 7-Fig. 9 represents the manufacturing process schematic diagram of a pixel cell of IPS array base palte in the embodiment of the present invention;
Figure 10 represents the cut-open view two of Fig. 2 along A-A;
Figure 11 represents the cut-open view two of Fig. 2 along B-B;
Figure 12 represents the cut-open view two of Fig. 5 along B-B.
Embodiment
Before introducing technical scheme of the present invention in detail, first description below is carried out to the concept that the present invention relates to and principle of work:
Thin Film Transistor-LCD (ThinFilmTransistor-LiquidCrystalDisplay, be called for short TFT-LCD) agent structure be liquid crystal panel, liquid crystal panel comprises thin-film transistor array base-plate to box and color membrane substrates, and liquid crystal molecule is filled between array base palte and color membrane substrates.Array base palte comprises many grid lines and a plurality of data lines, for limiting the region at multiple pixel cell place, each pixel cell comprises thin film transistor (TFT), pixel electrode and public electrode, thin film transistor (TFT) is opened by grid line, pixel voltage on data line transfers to pixel electrode by thin film transistor (TFT), thus between public electrode and pixel electrode, form the electric field driving liquid crystal deflecting element special angle, realize GTG display.Filter layer on color membrane substrates is for realizing colored display.The features such as it is little that TFT-LCD has volume, low in energy consumption, radiationless, are developed rapidly, dominate in current flat panel display market in recent years.
Plane conversion (IPS, In-PlaneSwitching) display mode:
IPS display mode type uses nematic crystal, and its public electrode and pixel electrode are gap electrode, are all formed on array base palte, and the slit of public electrode and pixel electrode is crisscross arranged.The special feature of IPS technology is it is not become light transmission mode to liquid crystal molecular orientation in advance, but orientation becomes lighttight pattern, printing opacity number by by the electric field applied.When not applying electric field, liquid crystal alignment, in light tight state, increases the visual angle of black state, thus the visual angle of light dark ratio also becomes wide.IPS display mode have high resolving power, high permeability, low-power consumption, wide viewing angle, high aperture, low aberration, without advantages such as water of compaction ripples (pushMura).
Capacitance touching control detects: comprise self-tolerant touch control detection and mutual tolerance formula touch control detection, because self-tolerant touch control detection only needs one deck touch control electrode, whether changing by detecting the self-capacitance of touch control electrode, can realize touching and detecting, have structure simple, be convenient to the advantages such as realization.Wherein, the self-capacitance of touch control electrode is its ground capacitance.
Self-tolerant touch screen of the prior art, its touch control electrode is two-dimensional array distribution, touch detecting method can be: the self-capacitance change transmission charge utilizing single touch control electrode self, by one end ground connection, the excitation of another termination or sample circuit detect the change of self-capacitance.Be specially, detect horizontal and vertical touch control electrode array successively, determine lateral coordinates and the longitudinal coordinate of touch point according to the change touching front and back self-capacitance respectively, be combined into planimetric coordinates determination touch location.When touch point only has one, the coordinate after combination is also unique one, can accurately locate; But when touch point has two, horizontal and vertical have two coordinates respectively, occurs four groups of coordinates after combination of two, wherein only has two to be true touch point, and another two is exactly " the terrible point " that be commonly called as, cannot realize real multiple point touching.
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples for illustration of the present invention, but are not used for limiting the scope of the invention.
Figure 1 shows that the structural representation of IPS array base palte in the embodiment of the present invention.
As shown in Figure 1, a kind of IPS array base palte is provided in the embodiment of the present invention, comprise viewing area and the non-display area being positioned at viewing area periphery, the viewing area of described array base palte comprises multiple pixel cell, each pixel cell comprises slit public electrode 1 and slit pixel electrode 2, the slit of public electrode 1 and the slit of pixel electrode 2 are crisscross arranged, and coordinate the electric field being formed and drive liquid crystal deflecting element.Described multiple public electrode 1 is multiplexed with multiple touch control electrode 10, and the public electrode 1 of the corresponding multiple electric connection of each touch control electrode 10, realizes being embedded in display panel in touch-screen, the thickness of thinning touch display device.
Described array base palte also comprises many signal line 11, and described signal wire 11 is electrically connected with touch control electrode 10 one_to_one corresponding, as shown in Figure 1.One frame picture display time of described array base palte comprises displaying time section and touch-control time period.In the displaying time section of a frame picture display time, public voltage signal is transmitted to touch control electrode 10 by the signal wire 11 of correspondence, for public electrode 1 provides reference voltage, the electric field driving liquid crystal deflecting element special angle is formed, shown in composition graphs 1, Fig. 3 and Fig. 4 between public electrode 1 and pixel electrode 2; In the touch-control time period of a frame picture display time, whether the self-capacitance being detected touch control electrode 10 by the signal wire 11 of correspondence is changed, and determines touch location.In addition, due to signal wire 11 and touch control electrode 10 one_to_one corresponding, the unique corresponding touch control electrode 10 of the detection signal obtained by every signal line 11, even if multiple touch control electrode 10 is touched simultaneously, also accurately can determine described multiple touch location, overcome the ghost point phenomenon that self-tolerant touch control detection in prior art there will be.And the self-capacitance of all touch control electrode 10 can detect simultaneously, relative to detecting horizontal and vertical touch control electrode array in prior art successively, shortening detection time, improve touch-control sensitivity.
Wherein, the shape of described public electrode 1 can be regular shape, as: rectangle, rhombus, triangle, circle or oval, also can be irregularly shaped, not do concrete restriction.For the number of the public electrode 1 of each touch control electrode 10 correspondence, do not do concrete restriction yet, be as the criterion with the accuracy requirement meeting touch control detection.
IPS array base palte is specifically as follows thin-film transistor array base-plate, comprises many grid lines 20 and a plurality of data lines 30, and for limiting the region at multiple pixel cell place, described pixel cell also comprises thin film transistor (TFT).The slit of public electrode 1 and pixel electrode 2 and the bearing of trend of data line 30 almost parallel.Because each public electrode 1 is only positioned at the region at pixel cell place, not overlapping with grid line 20, data line 30, reduce public electrode 1 and the coupling capacitance of grid line 20, data line 30, when public electrode 1 is multiplexed with touch control electrode 10, reduce the response time touching and detect to greatest extent.
Preferably, the gate electrode of described signal wire 11 and described grid line 20 and described thin film transistor (TFT) is for arrange with material with layer, or with the source electrode 3 of described data line 30 and described thin film transistor (TFT), leaking electricity very is arranged with material with layer.Namely, described signal wire 11 passes through to be formed the patterning processes of same grid metal level with the gate electrode of described thin film transistor (TFT) simultaneously, or, the source electrode 3 of described signal wire 11 and described thin film transistor (TFT) and drain electrode are by being formed the patterning processes of same source and drain metal level simultaneously, the technique of default independent making signal wire 11 and material, reduce production cost.Resistivity due to transparent conductive material is greater than the resistivity of grid metal and source and drain metal, therefore, does not generally make described signal wire 11 by transparency conducting layer.Wherein, gate electrode and grid line 20 are structure as a whole, and do not illustrate in the accompanying drawings.
Because described signal wire 11 needs to extend to non-display area from viewing area, generally speaking, signal wire 11 should be uniformly distributed as far as possible, and cabling is as far as possible short, as far as possible narrow.Specifically can arranging described signal wire 11, to be positioned at the part of viewing area parallel with described grid line 20 or data line 30.And the part being positioned at non-display area can parallelly distribute, also can fan-shapedly distribute.When array base palte is rectangle, described signal wire 11 extends to the side, place, long limit of array base palte from viewing area, to reduce the length of signal wire 11, shown in Figure 1.
The gate electrode of described signal wire 11 and described thin film transistor (TFT) is set in the embodiment of the present invention for arrange with material with layer, and the part that described signal wire 11 is positioned at viewing area be arranged in parallel with described grid line 20, grid line 20 and signal wire 11 stagger and are spaced a distance, and realize insulation.Or, described signal wire 11 is very arranged with material with layer with leaking electricity with the source electrode 3 of described thin film transistor (TFT), and the part that described signal wire 11 is positioned at viewing area be arranged in parallel with described data line 30, data line 30 and signal wire 11 stagger and are spaced a distance, and realize insulation.
Public electrode is multiplexed with the touch control electrode of self-tolerant touch screen by technical scheme of the present invention, realizes embedded touch, is thinned the thickness of display device.Meanwhile, the problem that self-tolerant touch screen in prior art there will be ghost point phenomenon can also be overcome, shorten the touch control detection time, improve touch-control sensitivity.
Because public electrode 1 is multiplexed with touch control electrode 10, the public electrode 1 of the corresponding multiple electric connection of touch control electrode 10, therefore, the electric connection of described signal wire 11 and touch control electrode 10, at least one public electrode 1 being converted to described signal wire 11 corresponding with touch control electrode 10 is electrically connected.Concrete, the public electrode 1 that described signal wire 11 is corresponding with touch control electrode 10, to simplify circuit.And multiple public electrodes 1 of each touch control electrode 10 correspondence can be electrically connected by connecting line (not shown), specifically can form described connecting line while formation public electrode 1, described connecting line and public electrode 1 are structure as a whole.
The concrete scheme that described signal wire 11 is electrically connected with touch control electrode 10 is introduced below with the public electrode 1 that described signal wire 11 is corresponding with touch control electrode 10.
Figure 2 shows that the structural representation one of a pixel cell of IPS array base palte in the embodiment of the present invention; Figure 5 shows that the structural representation two of a pixel cell of IPS array base palte in the embodiment of the present invention; Figure 3 shows that the cut-open view of Fig. 2 and Fig. 5 along A-A; Figure 4 shows that the cut-open view of Fig. 2 along B-B; Figure 6 shows that the cut-open view of Fig. 5 along B-B.
In a concrete embodiment, shown in composition graphs 1-Fig. 4, make first rete (namely making the first rete of public electrode 1) of described touch control electrode 10 and the non-conterminous setting of the second rete making described signal wire 11, between described first rete and the second rete, be provided with insulation course.Namely be provided with insulation course between described signal wire 11 and touch control electrode 10, described signal wire 11 is electrically connected with corresponding touch control electrode 10 by the via hole in described insulation course.Shown in Fig. 2, Fig. 4, Fig. 7-Fig. 9, corresponding manufacture craft can be:
Form the second rete making signal wire 11, patterning processes is carried out to described second rete, form the pattern comprising multiple signal wire 11, concrete, the material of described second rete is grid metal, carry out patterning processes to described second rete, form the pattern comprising the gate electrode of many signal line 11, many grid lines 20 and thin film transistor (TFT), gate electrode and grid line 20 are structure as a whole simultaneously.
Described second rete forms insulation course, carries out patterning processes to described insulation course, in described insulation course, form via hole, concrete, described insulation course comprises gate insulation layer 101 and passivation layer 102;
Described insulation course is formed the first rete making touch control electrode 10, patterning processes is carried out to described first rete, form the pattern comprising multiple touch control electrode 10.Wherein, touch control electrode 10 is electrically connected with corresponding signal wire 11 by the via hole 6 in described insulation course, is specially, this touch control electrode 10 correspondence a public electrode 1 be electrically connected by described via hole 6 and described signal wire 11.Concrete, the material of described first rete is transparent conductive material, carries out patterning processes to described first rete, forms the pattern comprising multiple public electrode 1, described multiple public electrode 1 is multiplexed with multiple touch control electrode 10, the public electrode 1 of the corresponding multiple electric connection of each touch control electrode.
Shown in composition graphs 1, Fig. 5 and Fig. 6, described signal wire 11 extends to non-display area from viewing area, on the bearing of trend of described signal wire 11, insulation course is provided with between described signal wire 11 and not corresponding touch control electrode 10, concrete, be provided with insulation course between the public electrode 1 that described signal wire 11 is corresponding with this touch control electrode 10, be not electrically connected.Because signal wire 11 with the not corresponding overlapping setting of touch control electrode 10, can decrease the impact of signal wire 11 on pixel aperture ratio.
In above-mentioned steps, also can first form touch control electrode 10, and then form signal wire 11.
Figure 2 shows that the structural representation one of a pixel cell of IPS array base palte in the embodiment of the present invention; Figure 5 shows that the structural representation two of a pixel cell of IPS array base palte in the embodiment of the present invention; Figure 10 shows that the cut-open view two of Fig. 2 and Fig. 5 along A-A; Figure 11 represents the cut-open view two of Fig. 2 along B-B; Figure 12 represents the cut-open view two of Fig. 5 along B-B.
In another particular embodiment of the invention, shown in composition graphs 2, Figure 10 and Figure 11, the first rete (namely making the first rete of public electrode 1) making described touch control electrode 10 is disposed adjacent with the second rete making described signal wire 11, does not have other retes between described first rete and the second rete.Described touch control electrode 10 is overlapped on corresponding signal wire 11, and in electrical contact, be specially, a public electrode 1 of this touch control electrode 10 correspondence is overlapped on described signal wire 11, thus the one_to_one corresponding realizing described signal wire 11 and touch control electrode 10 is electrically connected.
Shown in composition graphs 1, Fig. 5, Figure 10 and Figure 12, described signal wire 11 extends to non-display area from viewing area, on the bearing of trend of described signal wire 11, described signal wire 11 staggers with not corresponding touch control electrode 10 and arranges, be not electrically connected, be specially, on the bearing of trend of described signal wire 11, the public electrode 1 that described signal wire 11 is corresponding with this touch control electrode 10 staggers and arranges, thus realizes described signal wire 11 and be not electrically connected with not corresponding touch control electrode 10.
It should be noted that, described touch control electrode 10 is overlapped on corresponding signal wire 11 and refers to: there is overlapping region between described signal wire 11 and touch control electrode 10, the part that both are positioned at overlapping region contacts setting completely.Shown in Figure 11 and Figure 12, corresponding manufacture craft can be:
Form the second rete making signal wire 11, patterning processes is carried out to described second rete, form the pattern comprising many signal line 11, concrete, the material of described second rete is grid metal, carry out patterning processes to described second rete, form the pattern comprising the gate electrode of many signal line 11, many grid lines 20 and thin film transistor (TFT), gate electrode and grid line 20 are structure as a whole simultaneously.
Described second rete is formed the first rete making touch control electrode 10, patterning processes is carried out to described first rete, form the pattern comprising multiple touch control electrode 10.Wherein, described touch control electrode 10 is overlapped on corresponding signal wire 11, and be specially, a public electrode 1 of this touch control electrode 10 is overlapped on described signal wire 11.Concrete, the material of described first rete is transparent conductive material, carries out patterning processes to described first rete, forms the pattern comprising multiple public electrode 1, described multiple public electrode 1 is multiplexed with multiple touch control electrode 10, the public electrode 1 of the corresponding multiple electric connection of each touch control electrode 10;
In above-mentioned steps, also can first form touch control electrode 10, and then form signal wire 11.
In above-mentioned two embodiments, when IPS array base palte is thin-film transistor array base-plate, the second rete making signal wire 11 also can be source and drain metal level, specifically can when forming source electrode 3 and the drain electrode of data line 30 and thin film transistor (TFT), form the signal wire 11 parallel with described data line 30 by same source and drain metal level simultaneously, signal wire 11 and data line 30, source electrode 3 and drain electrode are arranged with material with layer, and signal wire 11 and data line 30 stagger to keep at a certain distance away and arrange, realize insulating.
For bottom gate thin film transistor, shown in composition graphs 1-Fig. 6, in the embodiment of the present invention, IPS type thin-film transistor array base-plate specifically comprises:
Underlay substrate 100, as: the transparency carriers such as glass substrate, quartz base plate, organic resin substrate, comprise multiple pixel region;
Be arranged on the gate electrode of many grid lines 20 on described underlay substrate 100, many signal line 11 and thin film transistor (TFT), described grid line 20, signal wire 11 and gate electrode 2 are arranged with material with layer;
Be arranged on the gate insulation layer 101 on described underlay substrate 100;
Be arranged on the active layer pattern 5 of the thin film transistor (TFT) on described gate insulation layer 101, the material of described active layer 5 is silicon semiconductor or metal-oxide semiconductor (MOS);
Be arranged on a plurality of data lines 30 on described underlay substrate 100, thin film transistor (TFT) source electrode 3 and drain electrode, described grid line 20 and data line 30 transverse and longitudinal cross-distribution, limit described multiple pixel region.Described source electrode 3 and drain electrode are overlapped on the relative both sides of described active layer 5;
Be arranged on the pixel electrode 2 on described underlay substrate 100, described pixel electrode 2 is by being overlapped on the drain electrode with thin film transistor (TFT);
Be arranged on the passivation layer 102 on described thin film transistor (TFT);
Be arranged on the multiple public electrodes 1 on described underlay substrate 100, each public electrode 1 is positioned at corresponding pixel region, and described multiple public electrode 1 is multiplexed with multiple touch control electrode 10, the public electrode 1 of the corresponding multiple electric connection of each touch control electrode 10.Described signal wire 11 and touch control electrode 10 one_to_one corresponding, a public electrode 1 of described touch control electrode 10 correspondence is electrically connected with signal wire 11 by the via hole 6 run through in described gate insulation layer 101 and passivation layer 102.
Shown in composition graphs 1-Fig. 9, above-mentioned IP S type thin-film transistor array base-plate method for making specifically comprises:
Step S1, provide a underlay substrate 100, described underlay substrate 100 comprises multiple pixel region;
Step S2, on the underlay substrate 100 of step S1, form grid metal level, patterning processes is carried out to described grid metal level, form the gate electrode of many grid lines 20, signal wire 11 and thin film transistor (TFT), described signal wire 11 is parallel with grid line 20, described gate electrode and grid line 20 are structure as a whole, as shown in Figure 7;
Described grid metal level can be the alloy of the metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and these metals, and grid metal level can be single layer structure or sandwich construction, and sandwich construction is Cu Mo such as, Ti Cu Ti, Mo Al Mo etc.
Step S3, on the underlay substrate 100 of completing steps S2, form gate insulation layer 101, shown in Figure 4;
The material of gate insulation layer 101 can select oxide, nitride or oxides of nitrogen, can be individual layer, bilayer or sandwich construction.Particularly, the material of gate insulation layer 101 can be SiNx, SiOx or Si (ON) x.
Step S4, on the underlay substrate 100 of completing steps S3, form the active active layer pattern 5 of thin film transistor (TFT), as shown in Figure 7;
The material of described active layer 5 can select silicon semiconductor or metal-oxide semiconductor (MOS) (as: indium-zinc oxide, indium tin oxide).
Step S5, on the underlay substrate 100 of completing steps S4, form source and drain metal level, described source and drain metal level applies photoresist, described photoresist is exposed, development, forms photoresist reserve area and photoresist not reserve area, etches away the source and drain metal level of photoresist not reserve area, peel off remaining photoresist, form source electrode 3 and drain electrode 4, described source electrode 3 and drain electrode 4 are overlapped on the relative both sides of described active layer 5, as shown in Figure 8;
Described source and drain metal level can be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, the alloy of the metals such as W and these metals, source and drain metal level can be single layer structure or sandwich construction, and sandwich construction is Cu Mo such as, Ti Cu Ti, Mo Al Mo etc.
Step S6, on the underlay substrate 100 of completing steps S5, form pixel electrode 2, described pixel electrode 2 is overlapped on the drain electrode 4 of thin film transistor (TFT), shown in composition graphs 8 and Fig. 9;
Described pixel electrode 2 is made by transparent conductive material, as: indium-zinc oxide or indium tin oxide.
Step S7, on the underlay substrate 100 of completing steps S6, form passivation layer 102, patterning processes is carried out to described gate insulation layer 101 and passivation layer 102, form the via hole 6 running through described gate insulation layer 101 and passivation layer 102, shown in Figure 4;
The material of passivation layer 102 can select oxide, nitride or oxides of nitrogen, can be individual layer, bilayer or sandwich construction.Particularly, the material of passivation layer 102 can be SiNx, SiOx or Si (ON) x.
Step S8, on the underlay substrate 100 of completing steps S7, form multiple public electrode 1, each public electrode 1 is positioned at corresponding pixel region, described multiple public electrode 1 is multiplexed with multiple touch control electrode 10, the corresponding multiple public electrode 1 of each touch control electrode 10 is electrically connected by connecting line, and described connecting line and described public electrode 1 are structure as a whole; Described signal wire 11 extends to non-display area from viewing area, its one end is electrically connected by the public electrode 1 that the via hole 6 that runs through described gate insulation layer 101 and passivation layer 102 is corresponding with touch control electrode 10, realize the electric connection with corresponding touch control electrode 10, shown in composition graphs 2 and Fig. 4.And between described signal wire 11 and not corresponding touch control electrode 10, be formed with gate insulation layer 101 and passivation layer 102, realize insulation, namely, on the bearing of trend of described signal wire 11, gate insulation layer 101 and passivation layer 102 is formed with, shown in composition graphs 5 and Fig. 6 between the public electrode 1 that described signal wire 11 is corresponding with this touch control electrode 10;
Described public electrode 1 is made by transparent conductive material, as: indium-zinc oxide or indium tin oxide.
Concrete:
First, transparency conducting layer is formed by physical deposition, chemical sputtering or other film build methods at underlay substrate 100;
Afterwards, described transparent conductive film layer applies photoresist, described photoresist is exposed, development, form photoresist reserve area and photoresist not reserve area, the region at the corresponding public electrode of described photoresist reserve area and connecting line place, described photoresist is reserve area other regions corresponding not;
Then, with the photoresist retained for stopping the transparency conducting layer removing photoresist not reserve area;
Finally, remove remaining photoresist, form the pattern comprising public electrode 1 and connecting line, the two ends of described connecting line connect two adjacent public electrodes 1 respectively, thus are electrically connected multiple public electrodes 1 of touch control electrode 10 correspondence.
So far the making of array base palte is completed.
Also provide a kind of display device in the embodiment of the present invention, adopt IPS array base palte as above, in order to realize embedded touch, the thickness of thinning touch display device.And overcome the problem that self-tolerant touch control detection in prior art there will be ghost point phenomenon, shorten the touch control detection time, improve touch control detection sensitivity.
Described display device can be: any product or parts with Presentation Function such as liquid crystal panel, mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.
The public electrode of IPS array base palte is multiplexed with touch control electrode by technical scheme of the present invention, realizes embedded touch, can the thickness of thinning touch display part.And the signal wire be electrically connected with touch control electrode one_to_one corresponding is set, in the touch-control time period of a frame picture display time, whether the self-capacitance being detected touch control electrode by the signal wire of correspondence is changed, and determines touch location.In addition, due to signal wire and touch control electrode one_to_one corresponding, when multiple touch control electrode is touched simultaneously, also can accurately detect multiple touch location, overcome the ghost point phenomenon that self-tolerant touch control detection in prior art there will be.And the self-capacitance of all touch control electrode can detect together, relative to detecting horizontal and vertical touch control electrode array in prior art successively, shortening detection time, improve touch-control sensitivity.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from the technology of the present invention principle; can also make some improvement and replacement, these improve and replace and also should be considered as protection scope of the present invention.

Claims (13)

1. an IPS array base palte, comprise viewing area and the non-display area being positioned at viewing area periphery, the viewing area of described array base palte comprises multiple pixel cell, each pixel cell comprises slit public electrode and slit pixel electrode, it is characterized in that, one frame picture display time of described array base palte comprises displaying time section and touch-control time period, described multiple public electrode is multiplexed with multiple touch control electrode, the public electrode of the corresponding multiple electric connection of each touch control electrode, described array base palte also comprises:
Many signal line, described signal wire and touch control electrode one_to_one corresponding are electrically connected, in the displaying time section of a frame picture display time, public voltage signal is transmitted to touch control electrode by the signal wire of correspondence, in the touch-control time period of a frame picture display time, whether the self-capacitance being detected touch control electrode by the signal wire of correspondence is changed.
2. array base palte according to claim 1, it is characterized in that, described array base palte is thin-film transistor array base-plate, described array base palte comprises grid line and the data line of transverse and longitudinal cross-distribution, for limiting the region at described multiple pixel cell place, each pixel cell also comprises thin film transistor (TFT), and slit and the described data line of described public electrode and pixel electrode are almost parallel;
The gate electrode of described signal wire and described grid line and described thin film transistor (TFT) is for arrange with material with layer, or with the source electrode of described data line and described thin film transistor (TFT), leaking electricity very is arranged with material with layer.
3. array base palte according to claim 2, is characterized in that, is provided with insulation course between described signal wire and touch control electrode, and described touch control electrode is electrically connected with corresponding signal wire by the via hole in described insulation course.
4. array base palte according to claim 3, is characterized in that, described insulation course comprises gate insulation layer and passivation layer;
Described array base palte specifically comprises:
Underlay substrate;
Be arranged on the gate electrode of many grid lines on described underlay substrate, many signal line and thin film transistor (TFT), described grid line, signal wire and gate electrode are for arrange with material with layer;
Cover the gate insulation layer of described grid line, signal wire and gate electrode;
Be arranged on active layer pattern on described gate insulation layer, thin film transistor (TFT);
The source electrode of a plurality of data lines and thin film transistor (TFT), drain electrode, the source electrode of described data line and thin film transistor (TFT) is very arranged with material with layer with leaking electricity, and described source electrode and drain electrode are overlapped on the relative both sides of described active layer;
Be overlapped on the pixel electrode on described drain electrode;
Cover the passivation layer of described thin film transistor (TFT) and pixel electrode;
Be arranged on the multiple public electrodes on described passivation layer, the projection of described public electrode on described underlay substrate has overlapping region with the projection of corresponding signal wire on described underlay substrate, and described public electrode is electrically connected with corresponding signal wire by the via hole running through described gate insulation layer and passivation layer.
5. array base palte according to claim 2, is characterized in that, described touch control electrode is overlapped on corresponding signal wire, in electrical contact.
6. the array base palte according to any one of claim 2-5, is characterized in that, the part that described signal wire is positioned at viewing area be arranged in parallel with described grid line, or the part that described signal wire is positioned at viewing area be arranged in parallel with described data line.
7. the array base palte according to any one of claim 1-5, is characterized in that, described signal wire extends to non-display area from viewing area; Described array base palte is rectangular configuration, and described signal wire extends to the side, place, long limit of array base palte from viewing area.
8. the method for making of the IPS array base palte described in an any one of claim 1-7, described array base palte comprises viewing area and is positioned at the non-display area of viewing area periphery, the viewing area that described method for making is included in array base palte forms the step of multiple pixel cell, each pixel cell comprises public electrode and pixel electrode, it is characterized in that, one frame picture display time of described array base palte comprises displaying time section and touch-control time period, described multiple public electrode is multiplexed with multiple touch control electrode, the public electrode of the corresponding multiple electric connection of each touch control electrode, described method for making also comprises:
Form many signal line, described signal wire and touch control electrode one_to_one corresponding are electrically connected, in the displaying time section of a frame picture display time, public voltage signal is transmitted to touch control electrode by the signal wire of correspondence, in the touch-control time period of a frame picture display time, whether the self-capacitance being detected touch control electrode by the signal wire of correspondence is changed.
9. method for making according to claim 8, it is characterized in that, described array base palte is thin-film transistor array base-plate, described array base palte comprises grid line and the data line of transverse and longitudinal cross-distribution, for limiting the region at described multiple pixel cell place, each pixel cell also comprises thin film transistor (TFT), and slit and the described data line of described public electrode and pixel electrode are almost parallel;
The step forming many signal line is specially:
By forming the gate electrode of described signal wire, described grid line and described thin film transistor (TFT) to the patterning processes of same grid metal level, or, by forming source electrode, the drain electrode of described signal wire, described data line and described thin film transistor (TFT) to the patterning processes of same source and drain metal level.
10. method for making according to claim 9, is characterized in that, described method for making specifically comprises:
Form grid metal level, patterning processes is carried out to described grid metal level, form the pattern comprising described signal wire;
Form insulation course on the signal line, patterning processes is carried out to described insulation course, form via hole;
Described insulation course forms transparency conducting layer, carries out patterning processes to described transparency conducting layer, form multiple public electrode, described public electrode is electrically connected with corresponding signal wire by the via hole in described insulation course.
11. method for makings according to claim 10, is characterized in that, described insulation course comprises gate insulation layer and passivation layer;
Described method for making specifically comprises:
One underlay substrate is provided;
Described underlay substrate is formed grid metal level, patterning processes is carried out to described grid metal level, form the gate electrode of many grid lines, many signal line and thin film transistor (TFT);
Form the gate insulation layer covering described grid line, signal wire and gate electrode;
Described gate insulation layer is formed the active layer pattern of thin film transistor (TFT);
Described active layer is formed source and drain metal level, patterning processes is carried out to described source and drain metal level, form source electrode, the drain electrode of a plurality of data lines and thin film transistor (TFT);
Form pixel electrode, described pixel electrode is overlapped on the pixel electrode on described drain electrode;
Form the passivation layer covering described thin film transistor (TFT) and pixel electrode;
Patterning processes is carried out to described passivation layer and gate insulation layer, forms via hole, expose described signal wire;
Described passivation layer forms multiple public electrode, the projection of described public electrode on described underlay substrate has overlapping region with the projection of corresponding signal wire on described underlay substrate, and described public electrode is electrically connected with corresponding signal wire by the via hole running through described gate insulation layer and passivation layer.
12. method for makings according to claim 9, is characterized in that, described method for making specifically comprises:
Form grid metal level, patterning processes is carried out to described grid metal level, form the pattern comprising described signal wire;
Form transparency conducting layer, carry out patterning processes, form multiple public electrode to described transparency conducting layer, described touch control electrode is overlapped on corresponding signal wire, in electrical contact.
13. 1 kinds of display devices, is characterized in that, adopt the IPS array base palte described in any one of claim 1-7.
CN201510412192.1A 2015-07-14 2015-07-14 IPS array substrate, manufacture method thereof and display device Pending CN105093736A (en)

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