CN105071928A - FPGA-based quick generation method of big prime number and big prime number family - Google Patents
FPGA-based quick generation method of big prime number and big prime number family Download PDFInfo
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Abstract
The invention discloses an FPGA-based quick generation method of a big prime number and a big prime number family. According to the method, any calculation is not needed during a screening process, the characteristics of an FPGA are fully utilized, and a prime number with any value in any position can be quickly generated. Meanwhile, the method exhibits high flexibility and expandability, and a modularized design way is adopted. The calculating speed and hardware consumption resources can be adjusted on the basis of actual applications. The function of quickly generating a big prime number can be achieved on a small platform, thereby providing sufficient prime number resources for the information encryption technology of a miniature mobile device.
Description
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to a method for realizing rapid generation of a large prime number and a large prime number family based on an FPGA (field programmable gate array), which is applicable to various encryption technologies and scientific researches.
Background
Prime numbers have an irreplaceable position in the fields of mathematics and encryption due to uniqueness and inequality. But also, therefore, makes finding prime numbers not regular. Due to the complex computational process of the prime number generation algorithm, its use is generally limited to computer platforms. Meanwhile, due to the serial operation mode of the computer and the limitation of the calculation bit width, the speed of the computer will be rapidly reduced when a large prime number is searched.
The FPGA (Field-programmable Gate array) technology has the advantages of high performance, high reliability and high integration of an ASIC (application specific Integrated Circuit) integrated circuit technology, and overcomes the defects of poor design flexibility, long period and high investment cost of a common ASIC due to the programmable capacity of the FPGA (Field-programmable Gate array) technology. The FPGA chip has high performance and strong confidentiality, and simultaneously adopts a parallel operation mode. When FPGA development is carried out, a plurality of modules are often designed and calculated in parallel, and the processing speed is improved. The FPGA chip has no strong limitation on the calculation bit width, and the calculation bit widths of different modules can be set according to the requirements of different functions, so that the characteristic has great advantage in processing big data calculation. Due to the excellent performance of the FPGA, the FPGA is widely applied to the communication field, the medical field and the military field. However, the development difficulty of the FPGA is high, and different algorithms need to be modified to different degrees in practical application, so that the FPGA can be realized.
Invention patent 1 (inventor: Liu Shi seal, Chen Yu, a "fast generation method of prime number family suitable for information encryption technology application": patent application No. 201110253413.7) establishes a possible prime number family by selecting a reduced residual system with modulus M ═ 30. Meanwhile, according to the distribution rule and the characteristics of the combinations in the possible prime number families, all the combinations in the possible prime number families are deleted, so that all the primes at any positions can be generated quickly and accurately. The invention uses a parallel thought to generate prime numbers, does not have complex calculation in the generation process, and is very suitable for being realized by an FPGA with the parallel calculation characteristic. Meanwhile, the FPGA is more flexible in calculating bit width and has no limit of fixed calculating bit width.
At present, certain achievements are obtained in prime number generation at home and abroad, but the achievement is rare, and the prime number generation algorithm is realized on an FPGA chip in less quantity. The large element hardware generation method described in document 1 (celadon. RSA algorithm, research and design. science and technology and engineering, 2013.(1). P13) is a screening method. The method needs to repeatedly carry out addition for many times in the screening process, and does not utilize the distribution rule of the composite number to carry out screening. The method in document 1 is only software simulation performed on a computer, but the method of the present invention is already implemented on an FPGA chip, and can obtain a large prime number and a large prime number family in a short time. The invention patent 2 (inventor: B.Firex, C.Clavier, P.Palier, L.Tieli, "method for generating prime numbers verified to be suitable for chip cards": patent application No. 201280062261.5) proposes a prime number generation method suitable for chip cards, which has a complicated calculation process and has certain difficulty in implementation. The invention does not carry out any calculation in the screening process, and the screening process can be realized through comparison. Invention patent 3 (inventor: MarcJoye, Saint Zacharie, Paillier, Paris (FR), "method for generating a random number with a predetermined prime number": patent application No. US7149763B2) proposes a prime number generation method. The method generates a number which can be prime number through a certain operation, and then performs prime detection on the number. If the number is not prime number, a number which is possibly prime number is regenerated, and the primality test is carried out again. The method takes a lot of time to search prime numbers and repeats the prime detection. Each primality test takes a lot of time and carries out a lot of complex operations. In the prime number generation process, the invention is equivalent to only one-time prime detection, and a plurality of prime numbers or prime number groups can be generated. Meanwhile, the invention modifies the large prime number generation method in the invention patent 1 aiming at the characteristics of the FPGA chip and realizes the large prime number generation method on the FPGA chip, thereby greatly improving the prime number generation speed.
The invention is a big prime number generation method based on FPGA, which is developed by combining the technical characteristics of FPGA on the basis of the fast prime number generation method provided by patent 1. The method can rapidly generate prime number families with any positions and sizes through the FPGA chip. Therefore, the function of quickly generating a large prime number family on a small platform is realized, and the most complete prime number resource is provided for the information encryption technology of small mobile equipment.
The invention discloses a method for rapidly generating a large prime number and a large prime number family based on an FPGA (field programmable gate array), which has higher flexibility and expansibility and uses a modular design mode. The calculation speed and hardware consumption resources can be adjusted according to the actual application.
Disclosure of Invention
The invention aims to provide a method for quickly generating a large prime number and a large prime number family based on an FPGA (field programmable gate array), which can quickly generate a certain number of prime numbers at any positions and in any sizes. The method can meet the requirements of information real-time encryption in the aspects of randomness, calculation speed, the size of generated prime numbers and the like.
After determining an initial position x, the method establishes a family of 8 possible primes M (as shown in Table 2) from 30(x-1) to 30(x-1+ n), and screens all combinations from this range to obtain all primes in the range.
In order to achieve the above purpose, the method for generating large prime numbers in the present invention uses two modules to complete the main functions, namely, a calculation module and a storage module, as shown in fig. 1.
The calculation module consists of 8 remainder modules and 8 comparison modules, as shown in fig. 2.
The memory module consists of a FIFO module and an OR operation module, as shown in FIG. 3.
The technical scheme of the large prime number generation system comprises the following three designs:
design 1: the whole system uses fixed point integers, and different modules use different bit widths of the fixed point integers. The fixed point integer bit width of each module can be configured independently according to the module function and the characteristics of input and output data. Aiming at the prime number requirements of different sizes, the fixed point integer bit width can be adjusted to achieve ideal balance between the calculated amount and the hardware resource consumption.
Design 2: when the method of patent 1 is used for screening, a remainder operation of an element y in an initial position x and 8 possible prime number families is firstly carried out, namely, xmoy. Each screening process is divided into two steps, one step is a residue taking process, the other step is a comparison process, and the residue taking process and the comparison process are completed through a residue taking module and a comparison module. The two modules work simultaneously without mutual interference. And the comparison module screens possible prime number family regions as much as possible in the calculation process of the residue taking module.
Design 3: and screening all the composite numbers in M by adopting the prime number rapid generation method in the patent 1 to obtain all the prime numbers in M. And 4, screening all the combinations in the range is completed through 8 comparison modules on the premise of not carrying out addition, subtraction, multiplication and division operations.
In the above design 1, the bit width parameter configuration is characterized in that: and configuring the overall bit width reference n according to the requirement of prime number size. For example, if a prime number of a power of 32 of 2 needs to be generated at maximum, the overall bit width reference is determined to be a 32-bit fixed-point integer; on the other hand, if a prime number of a power of 64 of 2 is required to be generated at maximum, the overall bit width reference is defined as a fixed-point integer of 64 bits. The larger the number of primes that need to be generated, the more resources are consumed. Meanwhile, under the overall bit width reference of the 64-bit fixed point integers, a small number of variables in the remainder module are the 64-bit fixed point integers, and the rest are mostly 32-bit fixed point integers which are half of the overall bit width reference; some variables in the comparison module are 32-bit fixed point integers which are half of the overall bit width reference, and the rest are 8-bit fixed point integers. The 8-bit fixed-point integer bit width is always used in the memory module.
The characteristics in the above design 2 are: aiming at the requirement of prime number size, the comparison module is enabled to carry out screening operation as much as possible in the process of calculating by the residue taking module. When the overall bit width reference is n, the remainder taking module theoretically needs n clock cycles every time the remainder taking operation is performed, and the module needs n +3 clock cycles in the invention. And the comparison module receives the result of the remainder module once every n +3 clock cycles, and then performs comparison operation once every clock cycle to screen out the composite number within the range of M.
The characteristics in the above design 3 are: one comparison module corresponds to one possible prime number family a in 8 possible prime number familiesi(i is more than or equal to 1 and less than or equal to 8), screening out a from MiThe medium element is the composite number of the factors. The comparison module uses the possible prime number family aiAn element y in1As a standard, 8 pieces of position information B ═ B1B2B3B4B5B6B7B8 are generated]. The comparing module can use the possible prime number family a in any clock periodiAnother element y of2As a standard, 8 pieces of location information are updated. The screening process can be completed by comparing the result of the remainder operation on the initial position x with the 8 pieces of position information.
The invention has the advantages that:
the invention uses fixed point integer, and the bit width is flexible and adjustable. Therefore, the system can be adjusted according to different user requirements, and the consumption of hardware resources is reduced to the minimum. Different fixed point integer bit widths are used among different modules, and resource consumption is further saved. Meanwhile, the whole system adopts a modularized design structure, and the speed of the system can be improved only by adding a computing unit on the premise of not changing the whole structure.
The invention reasonably combines all modules together to work cooperatively, each group of modules operates independently without operating until the results of other modules are obtained, thus the working efficiency of the system is improved. Meanwhile, the number of the residue taking modules and the number of the comparison modules can be increased or decreased according to the requirements of users, and the number of the residue taking modules is increased, so that the calculation speed of the system can be increased; the addition of the comparison module can enlarge the number of prime numbers obtained by the system.
The invention combines the large prime number rapid generation method in patent 1 to rapidly screen out all the composite numbers in the designated range and obtain all the prime numbers in the range. After the user gives an arbitrary initial position x, the system will quickly complete the screening process. The screening process does not need any calculation, and only needs simple comparison, so that the calculation speed is greatly improved.
The invention passes the hardware test verification on the cycleeIV series chip of Altera company, can run on the FPGA chip and obtain the correct result, obtain the large prime number in short time.
Drawings
Fig. 1 is an overall configuration diagram of a prime number generation system.
FIG. 2 is a block diagram of a computing module.
Fig. 3 is a structural diagram of a memory module.
Table 1 is a table of 8 possible prime number families.
Table 2 is a table of 8 possible prime families corresponding to the position results of the present invention.
Table 3 is a prime number position table generated in the present invention.
Detailed Description
The overall working process of the system is as follows:
first, an initial position x is entered and the system will filter out all combinations in M. x is less than the nth power of 2 and n is the overall bit width reference.
The calculation module will screen out M to be less thanThe elements in the 8 possible prime families of (a) are all the combinations of factors. The screening of the composite of M, factored by a column of elements in the 8 possible prime families, is done every n +3 clock cycles.
Each residue module takes x as dividend and takes one a in 8 possible prime number familiesiAs a divisor. As shown in table 1, if a remainder module operates with the elements in the a2 possible prime number family as divisors, then the operation of xmod7 is completed within n +3 clock cycles; selecting the second number in a2 after completion37, continuing to operate xmod 37; after the operation is finished, the third number 67 in the a2 is selected, the operation of the xmod67 is continued, and the operation is continued until the divisor is larger than the divisorThe residue taking module finishes residue taking calculation through shift subtraction, and outputs a result c once every n +3 clock cyclesi(i is more than or equal to 1 and less than or equal to 8). Each comparison module is used for taking the result c of the rest moduleiAs input, one of 8 possible prime number families aiGenerating position information B as a standard, comparing ciAnd B, finishing the screening operation. As shown in table 1, if a comparison module generates position information B based on a2 probable prime number family, the position information is updated every n +3 periods. If the comparison module uses the position information of y ═ 7 in the previous n +3 clock cycles, all the numbers divisible by 7 in M can be screened out by using the calculation result of the residue module xmod 7; in the following n +3 clock cycles, the comparison module uses the position information of y ═ 37, and uses the calculation result of the residue module xmod37 to filter out all numbers in M that can be divided by 37, and so on.
The comparison module stores the result c of the remainder module in the comparison module after obtaining the result c each time, and updates c once in each subsequent clock cycle. Each update results in c being c +1, and if c > y, c is 1. And after the next calculation of the remainder module is finished, updating c in the comparison module into a new calculation result of the remainder module.
The compare module outputs n valid 8-bit position results every n +3 clock cycles, each result corresponding to one column in table 2. The first bit of each result corresponds to ax1Row, second bit corresponds to ax2And (6) rows. When an 8-bit position result is output using the position information of y, where 0 indicates that the number of corresponding positions in table 2 is not divisible by y and 1 indicates that the number of corresponding positions is divisible by y.
Within each clock cycle, 8 comparison modules output 8 results. And performing OR operation on the 8 results according to bits, or outputting the operation result to the storage module as the operation result of the calculation module. The y-values used by the 8 comparison modules each time position information is updated correspond to one column in table 1.
The calculation module outputs n valid 8-bit position results every n +3 clock cycles, each result corresponding to a column in table 2. 0 in each result indicates that the number of corresponding positions is not divisible by all elements in a column of Table 1, and 1 indicates that the number of corresponding positions is divisible by some element in a column of 8 numbers in Table 1.
The result of the calculation module is stored in the storage module. The storage module stores n 8-bit position results. And when the result is stored, performing OR operation on the result output by the current computing module and the result at the corresponding position in the FIFO module, and covering the OR operation result at the same position in the FIFO module after the OR operation is completed.
ThroughAfter one clock cycle, the result in the FIFO module is the location of all the primes in M.
Example (c): if a prime number close to e is required.
Step 1: an initial position x is calculated. If prime numbers close to e are required, 30(x-1) > e, and x is the minimum integer satisfying the condition. All values in the FIFO block are assigned a value of 0.
Step 2: the 8 remainder modules respectively calculate xmod31, xmod7, xmod11, xmod13, xmod17, xmod19, xmod23 and xmod29, wherein 8 numbers of 31, 7, 11, 13, 17, 19, 23 and 29 correspond to the column n-1 in table 1, namely P1.
And step 3: and waiting for 8 residue taking modules to finish the first residue taking operation.
And 4, step 4: the 8 remainder modules output the remainder results to the corresponding comparison modules, and then respectively calculate xmod61, xmod37, xmod41, xmod43, xmod47, xmod49, xmod53 and xmod59, which correspond to the column n-2 in table 1, i.e., P2. The 8 comparison modules respectively generate the position information by taking 8 numbers in the P1 as a standard. Each comparison module generates 8 pieces of position information, which are B1, B2, B3, B4, B5, B6, B7 and B8, and all comparison modules generate 8 groups of position information, which are B1, B2, B3, B4, B5, B6, B7 and B8.
And 5: when 8 balance modules take the elements of n-2 columns in table 1 as divisors and x as dividends to calculate, the comparison module performs screening. If the first comparing module receives the calculation result c1 of the first residue-taking module xmod31 at the kth clock cycle, the first comparing module generates 8 pieces of position information b1, b2, b3, b4, b5, b6, b7, b8 with 31 as a standard. If c1 is b1, the first bit of the output result is 1, otherwise, 0; if c1 is b2, the second bit of the output result is 1, otherwise, 0, and so on, and the 8-bit position result is output. Meanwhile, in the k-th clock cycle, the second comparing module receives the calculation result c2 of the second remainder module xmod7, and at this time, the second comparing module generates 8 pieces of position information b1, b2, b3, b4, b5, b6, b7, and b8 by using 7 as a standard. If c2 is b1, the first bit of the output result is 1, otherwise, 0; if c2 is b2, the second bit of the output result is 1, otherwise, 0, and so on, and the 8-bit position result is output. And the latter 6 comparison modules are analogized in the same way, the 8 comparison modules output 8 bit position results in the kth clock cycle, the 8 results are output as the final result of the calculation module after bitwise OR operation is carried out on the 8 results, and the 8 results and the data at the first position in the FIFO module are stored in the first position in the FIFO module after bitwise OR operation is carried out on the data at the first position in the FIFO module.
Step 6: in the k +1 clock cycle, c1 is re-assigned in the first comparison module, c1 ═ c1+ 1. If c1 > 31, c1 is 1. If c1 is b1, the first bit of the output result is 1, otherwise, 0; if c1 is b2, the second bit of the output result is 1, otherwise, 0, and so on, and the 8-bit position result is output. And the latter 7 comparison modules are analogized, the 8 comparison modules output 8 bit position results in total, the 8 results are subjected to bitwise OR operation and then serve as the final result of the calculation module to be output, and the final result is subjected to bitwise OR operation with the data at the second position in the FIFO module and then is stored in the second position in the FIFO module.
And 7: in the k +2 clock cycle, c1 is re-assigned in the first comparison module, c1 ═ c1+ 1. If c1 > 31, c1 is 1. If c1 is b1, the first bit of the output result is 1, otherwise, 0; if c1 is b2, the second bit of the output result is 1, otherwise, 0, and so on, and the 8-bit position result is output. And the last 7 comparison modules are analogized, the 8 comparison modules output 8 bit position results in total, the 8 results are subjected to bit-wise OR operation and then output as the final result of the calculation module, and the final result is subjected to bit-wise OR operation with the data at the third position in the FIFO module and then stored in the third position in the FIFO module.
And 8: and after the residue taking module completes the calculation of xmod61, xmod37, xmod41, xmod43, xmod47, xmod49, xmod53 and xmod59, the result is sent to a comparison module, and then 8 residue taking calculations in x and P3 are carried out. And after the comparison module obtains the residue calculation results of x and P2, generating position information by taking P2 as a standard, and screening out the total number of M with elements in P2 as factors. P for each completion of the post-residue moduleiAfter the remainder operation with the number in (1) as the divisor, the operation continues with Pi+1The number in (1) is the remainder operation of the divisor; and the comparison module screens the number in M once when obtaining the result of the residue module.
And step 9: and after waiting for M clock cycles, outputting the result in the FIFO module to obtain the positions of all prime numbers in M.
For example, prime numbers between 900 and 980 need to be screened, calculation is performed first Because of the fact thatSo a total of 3 8-bit binary data storage results are required in the FIFO modules, which results are now z 1-00000000, z 2-00000000, and z 3-00000000. Because of the fact thatSo the largest prime factor does not exceed 31 in all combinations between 930 and 980.
The remainder module 1 calculates x1mod31 first, and since the result c1 is 0, the result c1 is 31 and is sent to the comparison module 1, and the comparison module 1 generates 31 pieces of 8 pieces of position information b1, b2, b3, b4, b5, b6, b7, and b 8. If b1 is c1, the output result a1 is 00000001, otherwise the output result a1 is 00000000. If b2 equals c1, the second bit of the output result, a1(2), equals 1, otherwise a1(2) equals 0. After comparing all the 8 pieces of comparison information, the final comparison result a1 is obtained as 00000000. Subsequently, c1 ═ c1+1 ═ 32 is updated, c1 ═ c1-31 ═ 1 because c1 > 31, and 8 pieces of position information are compared again, resulting in a2 ═ 00000000. Subsequently, c1 ═ c1+1 ═ 2 is updated, and the 8 pieces of position information are compared again, resulting in A3 ═ 00000001.
The residue taking module 2 calculates x1mod7, sends the result c2 ═ 3 to the comparison module 2, and the comparison module 2 generates 7 pieces of 8 pieces of position information b1, b2, b3, b4, b5, b6, b7, and b 8. If B1 is c2, the output result B1 is 00000001, otherwise the output result B1 is 00000000. If B2 equals c2, the second bit of the output result, B1(2), equals 1, otherwise B1(2), equals 0. After comparing all the 8 pieces of comparison information, the final comparison result B1 is obtained as 00010000. Subsequently, c2 ═ c2+1 ═ 4 is updated, and the 8 pieces of position information are compared again, resulting in B2 ═ 10000001. Subsequently, c2 ═ c2+1 ═ 5 is updated, and the 8 pieces of position information are compared again, resulting in B3 ═ 00001000.
The residue module 3 calculates x1mod11 and sends the result c3 ═ 9 to the comparison module 3. The comparison module 3 outputs 3 results C1 ═ 00001000, C2 ═ 00000000, and C3 ═ 00100000.
The residue module 4 calculates x1mod13 and sends the result c4 ═ 5 to the comparison module 4. The comparison module 4 outputs 3 results D1 ═ 01000000, D2 ═ 00100000, and D3 ═ 00000000.
The residue module 5 calculates x1mod17 and sends the result c5 ═ 14 to the comparison module 5. The comparison module 5 outputs 3 results E1 ═ 00000001, E2 ═ 00000000, and E3 ═ 00000000.
The residue module 6 calculates x1mod19 and sends the result c6 ═ 12 to the comparison module 6. The comparison module 6 outputs 3 results F1 ═ 00000000, F2 ═ 00000001, and F3 ═ 00000000.
The residue module 7 calculates x1mod23 and sends the result c7 ═ 8 to the comparison module 7. The comparison module 7 outputs 3 results G1 ═ 00000000, G2 ═ 00001000, and G3 ═ 10000000.
The residue module 8 calculates x1mod29 and sends the result c8 ═ 2 to the comparison module 8. The comparison module 8 outputs 3 results H1 ═ 00000000, H2 ═ 00000000, and H3 ═ 00000000.
As shown in table 3, the result of each comparison module is bitwise ored, and finally 3 results, Y1-01011001, Y2-10101001, and Y3-10101001, are obtained. Y1 is bitwise ored with z1 to update the value z 1-z 1orY1, z 2-z 2orY2, and z 3-z 3orY3 of z 1.
Subsequently, the 8 remainder modules will compute x1mod61, x1mod37, x1mod41, x1mod43, x1mod49, x1mod53, x1mod59, respectively, obtaining 8 results. The 8 comparison modules respectively update 8 pieces of position information of 61, 37, 41, 43, 49, 53 and 59, and the total number of the 8 pieces of position information is 64 pieces of position information, and the 8 pieces of position information are compared with the result of the remainder module. New 3 final results were obtained. Due to the fact thatThe largest prime factor does not exceed 31, so the calculation result Y1, Y2, and Y3 are 00000000. And updating z1, z2 and z3 again to obtain the final results of z 1-01011001, z 2-10101001 and z 3-10101001.
z1 ═ 01011001 corresponds to 8 numbers between (x1-1) × 30 ═ 900 and (x2-1) × 30 ═ 930, and is 901, 907, 911, 913, 917, 919, 923, 929, respectively. Wherein, the prime numbers are 907, 911, 919 and 929.
z2 ═ 10101001 corresponds to 8 numbers between (x2-1) × 30 ═ 930 and (x3-1) × 30 ═ 960, and is 931, 937, 941, 943, 947, 949, 953, 959, respectively. Among them, prime numbers are 937, 941, 947, 953.
z3 ═ 10101001 corresponds to 8 numbers between (x3-1) × 30 ═ 960 to x3 × 30 ═ 990, and is 961, 967, 971, 973, 977, 979, 983, 989, respectively. Wherein prime numbers are 967, 971, 977, 983.
Table 18 generation of possible prime number families
TABLE 2 table of 8 possible prime families corresponding to the position results of the present invention
TABLE 3 prime number position table generated in the present invention
| 1 | 2 | 3 | |
| 31 | 00000000 | 00000000 | 00000001 |
| 7 | 00010000 | 10000001 | 00001000 |
| 11 | 00001000 | 00000000 | 00100000 |
| 13 | 01000000 | 00100000 | 00000000 |
| 17 | 00000001 | 00000000 | 00000000 |
| 19 | 00000000 | 00000001 | 00000000 |
| 23 | 00000000 | 00001000 | 10000000 |
| 29 | 00000000 | 00000000 | 00000000 |
| Results | 01011001 | 10101001 | 10101001 |
Claims (5)
1. A big prime number and big prime number group rapid generation method based on FPGA is characterized in that a calculation module and a storage module are used for forming a big prime number and big prime number group generation system, so that a big prime number and big prime number group generation function is realized; wherein,
the big prime number and big prime number group generating system uses fixed point integers, and different modules use different fixed point number bit widths;
the big prime number and big prime number family generating system firstly carries out residue taking calculation and then carries out screening calculation in each screening calculation process;
the system for generating large prime numbers and large prime number families screens out the composite numbers containing a factor in the range by using the method in invention patent 1 (a method for quickly generating prime number families suitable for the application of information encryption technology: patent application number: 201110253413.7) and 8 pieces of position information generated by taking the factor as a standard.
2. The method according to claim 1, wherein the fixed-point integer used by the big prime and big prime family generating system specifically comprises:
the fixed point bit width of each module can be configured independently according to the module function and the characteristics of input and output data. Aiming at prime number requirements of different sizes, the bit width of the fixed point can be adjusted to save hardware resources.
3. The FPGA-based big prime and big prime family generating method of claim 1, wherein the characteristic of the big prime generating system in the screening process specifically comprises:
before screening out all the combinations containing the same factor in the range, the large prime and large prime family generating system needs to perform the remainder calculation by taking the factor as the divisor and the initial position as the dividend.
Each screening process is divided into two steps, one step is a residue taking process, the other step is a comparison process, and the residue taking process and the comparison process are completed through a residue taking module and a comparison module. The two modules work simultaneously without mutual interference. The comparison module screens possible prime number family regions in the calculation process of the residue taking module.
4. The method for generating big prime and big prime families based on FPGA of claim 1, wherein the characteristic of the big prime generation system using the method of patent 1 for the screening process specifically includes:
the screening process is carried out by the comparison module, and any addition, subtraction, multiplication and division operation is not carried out in the screening process.
One ratioThe comparison module corresponds to one possible prime number family a in 8 possible prime number familiesi(i is more than or equal to 1 and less than or equal to 8), and screening out aiThe medium element is the composite number of the factors. The comparison module uses the possible prime number family aiAn element y in1As a standard, 8 pieces of position information B ═ B1B2B3B4B5B6B7B8 are generated]. The comparing module can use the possible prime number family a in any clock periodiAnother element y of2As a standard, 8 pieces of location information are updated. The screening process can be completed by comparing the result of the remainder operation on the initial position x with the 8 pieces of position information.
5. The FPGA-based big prime and big prime family generating method of claim 1, comprising the following steps;
step 1: an initial position x is calculated. If prime numbers close to e are required, 30(x-1) > e, and x is the minimum integer satisfying the condition. Establishing 8 possible prime number families M from 30(x-1) to 30(x-1+ n), and calculatingAll values in the FIFO module are assigned to be 0;
step 2: the 8 residue taking modules respectively calculate xmod31, xmod7, xmod11, xmod13, xmod17, xmod19, xmod23 and xmod29, wherein 8 numbers of 31, 7, 11, 13, 17, 19, 23 and 29 correspond to 8 numbers in a first column of 8 possible prime number families, namely n is 1 column and is P1;
and step 3: waiting for 8 residue taking modules to finish the first residue taking operation;
and 4, step 4: the 8 remainder modules output the remainder results to corresponding comparison modules, and then respectively calculate xmod61, xmod37, xmod41, xmod43, xmod47, xmod49, xmod53 and xmod59, which correspond to the second column n of the 8 possible prime number families, namely P2. The 8 comparison modules respectively generate the position information by taking 8 numbers in the P1 as a standard. Each comparison module generates 8 pieces of position information, namely B1, B2, B3, B4, B5, B6, B7 and B8, and all comparison modules generate 8 groups of position information, namely B1, B2, B3, B4, B5, B6, B7 and B8;
and 5: when the 8 remainder modules calculate by taking the element of the second column n-2 columns in the 8 possible prime number families as the divisor and x as the dividend, the comparison module performs the screening. If the first comparing module receives the calculation result c1 of the first residue-taking module xmod31 at the kth clock cycle, the first comparing module generates 8 pieces of position information b1, b2, b3, b4, b5, b6, b7, b8 with 31 as a standard. If c1 is b1, the first bit of the output result is 1, otherwise, 0; if c1 is b2, the second bit of the output result is 1, otherwise, 0, and so on, and the 8-bit position result is output. Meanwhile, in the k-th clock cycle, the second comparing module receives the calculation result c2 of the second remainder module xmod7, and at this time, the second comparing module generates 8 pieces of position information b1, b2, b3, b4, b5, b6, b7, and b8 by using 7 as a standard. If c2 is b1, the first bit of the output result is 1, otherwise, 0; if c2 is b2, the second bit of the output result is 1, otherwise, 0, and so on, and the 8-bit position result is output. The latter 6 comparison modules are analogized in the same way, the 8 comparison modules output 8 bit position results in the kth clock cycle, the 8 results are output as the final result of the calculation module after bitwise OR operation is carried out on the 8 results, and the 8 results are stored in the first position of the FIFO module after bitwise OR operation is carried out on the 8 results and the data in the first position of the FIFO module;
step 6: in the k +1 clock cycle, c1 is re-assigned in the first comparison module, c1 ═ c1+ 1. If c1 > 31, c1 is 1. If c1 is b1, the first bit of the output result is 1, otherwise, 0; if c1 is b2, the second bit of the output result is 1, otherwise, 0, and so on, and the 8-bit position result is output. The latter 7 comparison modules are analogized, the 8 comparison modules output 8 bit position results in total, the 8 results are subjected to bit-wise OR operation and then serve as the final result of the calculation module to be output, and the final result is subjected to bit-wise OR operation with the data at the second position in the FIFO module and then is stored in the second position in the FIFO module;
and 7: in the k +2 clock cycle, c1 is re-assigned in the first comparison module, c1 ═ c1+ 1. If c1 > 31, c1 is 1. If c1 is b1, the first bit of the output result is 1, otherwise, 0; if c1 is b2, the second bit of the output result is 1, otherwise, 0, and so on, and the 8-bit position result is output. The latter 7 comparison modules are analogized in this way, the 8 comparison modules output 8 bit position results in total, the 8 results are subjected to bitwise OR operation and then output as the final result of the calculation module, and the final result is subjected to bitwise OR operation with the data at the third position in the FIFO module and then stored at the third position in the FIFO module;
and 8: and after the residue taking module completes the calculation of xmod61, xmod37, xmod41, xmod43, xmod47, xmod49, xmod53 and xmod59, the result is sent to a comparison module, and then 8 residue taking calculations in x and P3 are carried out. And after the comparison module obtains the residue calculation results of x and P2, generating position information by taking P2 as a standard, and screening out the total number of M with elements in P2 as factors. The last module is completed by piAfter the remainder operation with the number in (1) as the divisor, the operation continues with pi+1The number in (1) is the remainder operation of the divisor; the comparison module screens the number in M once when obtaining the result of the residue module;
and step 9: and after waiting for M clock cycles, outputting the result in the FIFO module to obtain the positions of all prime numbers in M.
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