CN105068938A - Wear balancing method of non-volatile memory based on multi-level cell - Google Patents
Wear balancing method of non-volatile memory based on multi-level cell Download PDFInfo
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Abstract
The invention discloses a wear balancing method of a non-volatile memory system based on a multi-level cell. The wear balancing method comprises the following steps: dividing each wafer in a storage region of the non-volatile memory system into a plurality of sub-storage regions; randomly exchanging data in a physical line in the sub-storage regions by using an algebra-based wear balancing algorithm after P writing requests are performed in each sub-storage region every time; and performing data exchange by selecting a hot sub-storage region and a cold sub-storage region in various sub-storage regions after T writing requests are performed in the storage region of the non-volatile memory system every time, wherein T is a region exchange interval, which is a predetermined value or a random number; the hot sub-storage region is the sub-storage region having more cumulative writing numbers; and the cold sub-storage region is the sub-storage region having less cumulative writing numbers. In combination with a table-based wear balancing algorithm and the algebra-based wear balancing algorithm, the wear balancing method disclosed by the invention has the advantages of being long in service life, safe and reliable.
Description
Technical field
The invention belongs to field of solid state storage, more specifically, relate to a kind of abrasion equilibrium method of the nonvolatile memory system based on multilevel-cell.
Background technology
Along with the development of multi-core technology, the demand of computer system to internal memory is more and more higher, comprises the many aspects such as capacity, power consumption, performance, extensibility.Traditional dynamic RAM (DynamicRandomAccessMemory, DRAM) internal memory is owing to being subject to the constraint of extensibility and electricity leakage power dissipation, and in the face of new applied environment, its development is restricted.
The appearance of novel non-volatile memory (Non-VolatileMemory, NVM) technology, the development for memory system provides a kind of new resolving ideas.Current novel nonvolatile memory mainly contains phase transition storage (PhaseChangeMemory, and memristor (ResistiveRandomAccessMemory PCM), RRAM) etc., they have the advantage that capacity is large, low in energy consumption, performance is high, are the most competitive candidates of internal memory of future generation.Compare DRAM technology, these nonvolatile memorys have significant advantage in energy consumption, performance, extensibility etc., and cause academia and a large amount of concern of industrial community, the current research based on nonvolatile memory is also a focus direction.
In order to improve the cost performance of NVM chip, multilevel-cell technology (Multi-LevelCell, MLC) will be applied in NVM system, this makes a unit can store 2 or 4 data bit, therefore, the version (Single-LevelCell, SLC) of MLC-2/MLC-4 chip its individual layer relative has more Large Copacity and lower price advantage.But due to material restriction and excessive programming operation, cause the permanance of MLC-2/MLC-4 chip to reduce by 100 times than the version of its individual layer.Its lower permanance limits the life problems brought, and becomes the Main Bottleneck that they play the part of interior main memory role.In SLC technology, in PCM chip, the most capitalization number of times of each unit is 10
7~ 10
8, and RRAM is 10
8~ 10
12.In MLC technology, in PCM chip, the permanance of each unit is 10
5~ 10
6, and RRAM can reach 10
7.Uniform write access can make NVM chip reach the serviceable life of several years, but uneven write access can make some storage unit in seconds be worn through, thus causes internal memory to lose efficacy.Therefore, utilize abrasion equilibrium technology, unbalanced upper strata write access is converted into balanced bottom write access, to extend the serviceable life of these NVM system, seems especially important.
For the Wear leveling algorithm of nonvolatile memory, existing research work can be divided into two classes---the Wear leveling algorithm (TBWL) based on form and the Wear leveling algorithm (AWL) based on algebraically.(1) based on the Wear leveling algorithm of form: such algorithm have recorded the mapping relations of each logical block and physical block, that has also added up each logical block writes number of times simultaneously.Write the high and minimum block of number of times to write gap between counterbalance weight by periodically exchanging.Wear leveling algorithm typically based on form has row to exchange (LineSwapping), section exchange (SegmentSwapping), and page exchanges (PageSwapping) etc.Their difference is the granularity difference of minimum crosspoint, and there is a big difference for the time overhead of its storage space expense and exchange.In order to reach the high life-span, the granularity requirements of mapping and crosspoint is enough little, and such as row exchanges, but this can cause very high space expense.In addition, the most wearing and tearing algorithm based on form adopts the exchanging policy determined, this makes the program of malice can guess the reposition region to be exchanged, thus carries out heavy attack to a specific region, causes all provisional capitals in this region to be worn through.(2) based on the Wear leveling algorithm of algebraically: typical algorithm has Start-Gap and SecurityRefresh etc.Wear leveling algorithm based on algebraically is mapped by algebraically, periodic mobile physical line, being exchanged by a large amount of row makes the logical line of " heat " can move on each physical line from probability, and its physical address can be calculated by given logical address and algebraic function and obtain.Wear leveling algorithm based on algebraically has low expense, the advantage of high security, has been used at present in the Prototyping Platform based on NVM.
Along with MLC technology is applied in NVM system, memory size is multiplied and result in space expense based on the Wear leveling algorithm of form also along with rolling up, and such as, in the system of 64GB, space expense reaches 2.5GB, cannot be applied to real system.And permanance decline causes the number of times exchanged based on algebraically Wear leveling algorithm to reduce, insufficient exchange times causes unbalanced distribution problem of writing, thus directly causes low serviceable life.In order to promote the efficiency of the Wear leveling algorithm based on algebraically, typical method is improved exchange frequency and increases region quantity.Improve exchange frequency and can cause hydraulic performance decline, and increase the unbalanced traffic of writing between region quantity meeting deteriorated area, reduce serviceable life on the contrary.
Summary of the invention
For above defect or the Improvement requirement of prior art, the invention provides a kind of abrasion equilibrium method of the nonvolatile memory system based on multilevel-cell, organically combine the advantage of the Wear leveling algorithm based on form and the Wear leveling algorithm based on algebraically and overcome respective defect, there is high life and safe and reliable advantage.
For achieving the above object, the invention provides a kind of abrasion equilibrium method of the nonvolatile memory system based on multilevel-cell, it is characterized in that, comprise the steps: that each wafer of the storage area of nonvolatile memory system is divided into multiple sub-storage areas by (1), each sub-storage areas is made up of several physical lines; (2) to each sub-storage areas, after it often performs P write request, use the Wear leveling algorithm based on algebraically to exchange data in the physical line of this sub-storage areas at random, thus realize inside, sub-storage areas write number of times balance; Wherein, P is the exchange cycle of the predetermined Wear leveling algorithm based on algebraically; (3) after the storage area of nonvolatile memory system often performs T write request, from each sub-storage areas, choose " heat " sub-storage areas and " cold " sub-storage areas carry out exchanges data, thus the number of times of writing realized between sub-storage areas balances; Wherein, T is mapping of field interval, is predetermined value or random number, and " heat " sub-storage areas refers to that access is comparatively frequent, and the more sub-storage areas of number of times is write in accumulation, and " cold " sub-storage areas refers to that access infrequently, and the less sub-storage areas of number of times is write in accumulation.
Preferably, T is predetermined value, and described step (3) comprises the steps: that the average accumulated that (3-1) calculates sub-storage areas writes number of times further
accumulation is write the sub-storage areas of number of times higher than mean value as " heat " sub-storage areas, accumulation is write the sub-average sub-storage areas of number of times as " cold " sub-storage areas; Wherein, n is the number of sub-storage areas, w
ibe that number of times is write in the accumulation of i-th sub-storage areas; (3-2) weights of each " heat " sub-storage areas are calculated
with the weights of each " cold " sub-storage areas
and then calculate the weights summation of " heat " sub-storage areas
the weights summation of " cold " sub-storage areas
(3-3) random number X is generated
1and X
2, make
(3-4) by X
1order deducts the weights of " heat " sub-storage areas one by one, works as X
1when≤0, choose corresponding " heat " sub-storage areas, by X
2order deducts the weights of " cold " sub-storage areas one by one, works as X
2when≤0, choose corresponding " cold " sub-storage areas; (3-5) exchange the data of all physical lines of " heat " sub-storage areas chosen and " cold " sub-storage areas chosen, after performing T write request, return step (3-1).
Preferably, T is random number, and described step (3) comprises the steps: that (3-1) generates random number N further, calculates mapping of field interval T=N*K, and wherein, K is the physics line number that each sub-storage areas comprises; (3-2) after execution T write request, accumulation is write the maximum sub-storage areas of number of times as " heat " sub-storage areas, accumulation is write the sub-storage areas of least number of times as " cold " sub-storage areas; (3-3) exchange the data of all physical lines of " heat " sub-storage areas and " cold " sub-storage areas, return step (3-1).
Preferably, complete the exchanges data of " heat " sub-storage areas and " cold " sub-storage areas by the following method: (A1) calculates the capable exchange interval t=T/K of the single physical of " heat " sub-storage areas to be exchanged and " cold " sub-storage areas, wherein, K is the physics line number that each sub-storage areas comprises; (A2) often t write request is performed, just from " heat " sub-storage areas to be exchanged, choose a physical line, the physical line identical with offset address in " cold " sub-storage areas to be exchanged carries out exchanges data, until complete the exchanges data of all physical lines of " heat " sub-storage areas to be exchanged and " cold " sub-storage areas.
Preferably, in described step (2), the memory read-write caused by exchanges data operates and directly performs in wafer inside, not committed memory controller and bus resource.
Preferably, described step (3) is performed by Memory Controller Hub, and the memory read-write caused by exchanges data operates and takies bus resource.
In general, the above technical scheme conceived by the present invention compared with prior art, has following beneficial effect:
1, the Wear leveling algorithm based on form and the Wear leveling algorithm based on algebraically has been organically combined.Its core concept is a lot of sub-storage areas whole spatial division, adopts the Wear leveling algorithm based on algebraically, adopt the Wear leveling algorithm based on form between zones, thus realize low space expense and high serviceable life at intra-zone.
2, in NVM wafer (bank), perform the Wear leveling algorithm based on algebraically of individual layer, namely completely independent between each sub-storage areas, this had both avoided the additional request sent out by the Wear leveling algorithm based on algebraically and has taken bus and cause performance degradation problem, and number of times is write in the accumulation simultaneously making the Memory Controller Hub on upper strata accurately can record each storage subregion.
3, in Memory Controller Hub, perform the sub-storage areas Wear leveling algorithm based on form, can effectively utilize more hardware resource, what adopt more complicated exchanging policy to balance sub-storage areas between the inner and wafer of all wafers writes number of times, obtains high serviceable life and security simultaneously.
Accompanying drawing explanation
Fig. 1 is the principle schematic of the abrasion equilibrium method of the nonvolatile memory system based on multilevel-cell of the embodiment of the present invention;
Fig. 2 is the principle schematic of fine-grained switching method.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.In addition, if below in described each embodiment of the present invention involved technical characteristic do not form conflict each other and just can mutually combine.
For the ease of understanding the present invention, first the following noun occurred in the present invention is made an explanation:
Physical line: the addressed location that memory system is the most basic.In different systems, row size can be different, and a usual row size can be 64 bytes, 128 bytes, 256 bytes.
Sub-storage areas: be made up of several physical lines, a usual sub-storage areas can be made up of 2048,4096 or 8192 row.
Physical address: the address corresponding to physical equipment, it is a true address.
Logical address: the address of upper level applications request is a virtual address.
" heat " sub-storage areas: refer in particular to access comparatively frequently, the more sub-storage areas of number of times is write in accumulation.
" cold " sub-storage areas: refer in particular to access infrequently, the less sub-storage areas of number of times is write in accumulation.
Fig. 1 is the principle schematic of the abrasion equilibrium method of the nonvolatile memory system based on multilevel-cell of the embodiment of the present invention.Inclusion region exchange, address maps and request queue module in nonvolatile memory controller.Address mapping table has added up each logic region number corresponding physical region number, the time writing number of times and the last exchange of accumulation.It is exchange in order to accurately carry out cold and hot region that number of times and swap time are write in accumulation.In addition, mapping of field also needs use Parasites Fauna, comprise 4 registers, wherein two registers record the current region exchanged respectively, a register record exchanges line number, last register record internal memory accumulation write number of times, this register be used for toggle area exchange.The abrasion equilibrium module integration based on algebraically of individual layer is in NVMbank, and each abrasion equilibrium module based on algebraically manages a region independently.Abrasion equilibrium module based on algebraically uses pure hardware implementing, has the advantage of low expense and low delay.
In addition, for the problem that the Wear leveling algorithm security based on form is poor, present invention uses a kind of random exchanging policy, make the program of malice cannot guess swap time and new physical location.The present invention simultaneously devises a kind of fine-grained exchanged form, can avoid performance degradation during mapping of field.
Unbalancedly between each row of intra-zone distribution is write in order to balance, the present invention uses the Wear leveling algorithm based on algebraically of individual layer to manage regional independently, " heat " row write often can be exchanged with other row in this region fast, avoid a row by too early worn out.Wear leveling algorithm typically based on algebraically has Start-Gap and SecurityRefresh.Start-Gap is at the reserved blank line of each intra-zone, periodically exchanges blank line and its neighbours' row.Start-Gap needs 3 registers, stores the physical address that minimum logical address is corresponding respectively, blank line pointer and write counter.SecurityRefresh periodically moves a random skew all row, often takes turns after exchange completes, the more secret key (key) that stochastic generation one is new, as the distance of next round movement.SecurityRefresh needs 4 registers, deposits last round of secret key respectively, and when the secret key of front-wheel, current internal exchanges pointer and writes counter.Based on the Wear leveling algorithm of algebraically to write number of times between the inner each row of low-down calculating and storage overhead equilibrium region.In algebraically maps, logical row address and physical line address existence function mapping relations, by simple algebraic manipulation, just can obtain the physical line address corresponding to logical row address.In the present invention, the abrasion equilibrium strategy based on algebraically is independently carried out in each region, can carry out how effective movement to make the region of " heat ".Wearing and tearing module based on algebraically uses pure hardware implementing, has the advantage of low delay.
As mentioned above, the Wear leveling algorithm based on algebraically makes each intra-zone in nonvolatile memory, well can reach the target of load balancing.
The abrasion equilibrium method of the nonvolatile memory system based on multilevel-cell of the embodiment of the present invention comprises the steps:
(1) each wafer of the storage area of NVM system is divided into multiple sub-storage areas, each sub-storage areas is made up of several physical lines.
(2) to each sub-storage areas, after it often performs P write request, use the Wear leveling algorithm based on algebraically to exchange data in the physical line of this sub-storage areas at random, thus realize inside, sub-storage areas write number of times balance.
Wherein, the memory read-write caused by exchanges data operates and directly performs in wafer inside, not committed memory controller and bus resource; P is the exchange cycle of the Wear leveling algorithm based on algebraically, is predetermined value, considers the value that life-span of abrasion equilibrium method of the present invention and performance choose P.Preferably, P ∈ (8,128), now, the life-span of abrasion equilibrium method of the present invention is moderate, and its performance degradation maintains between 0.78% and 12.5% simultaneously.
(3) after the storage area of NVM system often performs T write request, from each sub-storage areas, choose " heat " sub-storage areas and " cold " sub-storage areas carry out exchanges data, thus the number of times of writing realized between sub-storage areas balances.
Wherein, T is predetermined value or random number, and " heat " sub-storage areas refers to that access is comparatively frequent, and the more sub-storage areas of number of times is write in accumulation, and " cold " sub-storage areas refers to that access infrequently, and the less sub-storage areas of number of times is write in accumulation.This step is performed by Memory Controller Hub, and the memory read-write caused by exchanges data operates and takies bus resource.
By performing above-mentioned steps (2) and (3), the number of times of writing completed between inside, sub-storage areas and sub-storage areas in different levels respectively balances, thus realizes abrasion equilibrium.
In order to writing the traffic and avoiding powerful region to attack between equilibrium region, adopt traditional deterministic exchange algorithm, such as periodically exchange the region that most cold-peace is the hottest, the program of malice can be caused to follow the tracks of and the specific physical region of heavy attack, cause equipment to lose efficacy very early.Such as one comprises the region of 2048 row, adopt deterministic algorithm, by malice worn out needs 39 minutes, in order to avoid this phenomenon, the present invention devises a kind of stochastic selection algorithm based on weighting or dynamic random and adjusts exchange cycle and complete exchange between region.Therefore the program of malice cannot detect reposition and the swap time in exchanged region, thus effectively avoids attacking.
In one embodiment of the invention, by selecting " cold " sub-storage areas to be exchanged and " heat " sub-storage areas based on the stochastic selection algorithm of weighting, above-mentioned steps (3) comprises the steps: further
(3-1) average accumulated calculating sub-storage areas writes number of times
accumulation is write the sub-storage areas of number of times higher than mean value as " heat " sub-storage areas, accumulation is write the sub-average sub-storage areas of number of times as " cold " sub-storage areas; Wherein, n is the number of sub-storage areas, w
ibe that number of times is write in the accumulation of i-th sub-storage areas.
(3-2) weights of each " heat " sub-storage areas are calculated
with the weights of each " cold " sub-storage areas
and then calculate the weights summation of " heat " sub-storage areas
the weights summation of " cold " sub-storage areas
(3-3) random number X is generated
1and X
2, make
(3-4) by X
1order deducts the weights of " heat " sub-storage areas one by one, works as X
1when≤0, choose corresponding " heat " sub-storage areas, by X
2order deducts the weights of " cold " sub-storage areas one by one, works as X
2when≤0, choose corresponding " cold " sub-storage areas.
(3-5) exchange the data of all physical lines of " heat " sub-storage areas chosen and " cold " sub-storage areas chosen, after performing T write request, return step (3-1).
Wherein, T is mapping of field interval, is predetermined value, considers the value that life-span of abrasion equilibrium method and performance choose T.Preferably, T=128*K, now, the life-span of abrasion equilibrium method is moderate, and its performance degradation maintains about 1.56% simultaneously, and wherein, K is be the physics line number that each sub-storage areas comprises.
In one embodiment of the invention, the method choice being exchanged interval by dynamic random adjustment goes out " cold " sub-storage areas to be exchanged and " heat " sub-storage areas, and above-mentioned steps (3) comprises the steps: further
(3-1) generate random number N, calculate mapping of field interval T=N*K, wherein, K is the physics line number that each sub-storage areas comprises.
N is less, and the life-span of this abrasion equilibrium method is longer, but can cause its hydraulic performance decline simultaneously, and vice versa.Preferably, N ∈ (64,256), now the life-span of abrasion equilibrium method is moderate, and its performance degradation maintains between 3.13% and 0.78% simultaneously.
(3-2) after execution T write request, accumulation is write the maximum sub-storage areas of number of times as " heat " sub-storage areas, accumulation is write the sub-storage areas of least number of times as " cold " sub-storage areas.
(3-3) exchange the data of all physical lines of " heat " sub-storage areas and " cold " sub-storage areas, return step (3-1).
When carrying out exchanges data to two sub-storage areas, can move all physical lines of two sub-storage areas, the request of exchange takes request queue, and this can block the normal request performed.Now, NVM internal memory cannot provide the service on upper strata.Such as, a sub-storage areas comprises 2048 row, and completing exchanges data needs 6.1ms.In order to avoid performance degradation, the embodiment of the present invention adopts fine-grained switching method, successively moves the data of all physical lines.
Fine-grained switching method comprises the steps:
(A1) the exchange interval t=T/K that the single physical of " heat " sub-storage areas to be exchanged and " cold " sub-storage areas is capable is calculated.
(A2) often t write request is performed, just from " heat " sub-storage areas to be exchanged, choose a physical line, the physical line identical with offset address in " cold " sub-storage areas to be exchanged carries out exchanges data, until complete the exchanges data of all physical lines of " heat " sub-storage areas to be exchanged and " cold " sub-storage areas.
Particularly, as shown in Figure 2, be stored in register by regional number to be exchanged, often perform t write request, two row just choosing skew identical to be exchanged two regions exchange, namely from two regions, read the data of a row respectively, and the position of writing the other side is gone, exchange pointer simultaneously and add 1, when exchanging pointer value and reaching N, exchange completes, and removes the value of register.
Below from space expense, time overhead, additionally write the abrasion equilibrium method of the aspect such as expense and performance impact to the nonvolatile memory system based on multilevel-cell of the present invention and assess.
We store address mapping table in sram, are convenient to capacity extension, support the bank of greater number.Value required when exchanging with the territories, register storage area of four 32.Suppose the capacity C=64GB of whole nonvolatile memory, it includes M sub-storage areas (M=65536), each sub-storage areas needs the storage space of 12 bytes, and use the space of 4 bytes to store physical address respectively, number of times and nearest swap time are write in accumulation.All space expenses are: OSUM=(3*M*4+4*4) byte=(12*M+16) byte=256KB.Visible, the abrasion equilibrium method of the nonvolatile memory system based on multilevel-cell of the present invention is very low to the requirement of hardware resource.
There is two parts time overhead in method of the present invention: the time overhead of address conversion and the time overhead of execution area selection algorithm.Memory request needs to carry out the conversion of logic region address to physical region address in controller inside, and therefore need to search address mapping table in sram, the time of tabling look-up is 3 ~ 5 treatment cycles.Memory request needs to carry out logical offset address in non-volatile wafer inside and changes to grabbing of physical deflection address, needs 1 ~ 2 treatment cycle.Relative to the time that read-write operation consumes, this time delay can be ignored.And perform and need to access all data in SRAM based on the stochastic selection algorithm of weighting, the time of consumption reaches microsecond rank, and we perform on backstage, thus hides the execution time, alleviates its impact on normal request.
Additionally write expense and performance impact: because Wear leveling algorithm introduces extra request, these exchange requests can block the execution of normal request, and take system bus and other hardware resources, result in performance degradation.Additionally writing overhead computational formula is 1/P+2/t, and wherein P is the exchange cycle of the Wear leveling algorithm based on algebraically, and t is the exchange interval that the single physical of sub-storage areas is capable.Usual t=128, P=8 ~ 64, now additionally writing expense is 3.1% ~ 14.1% respectively.And we adopt the abrasion equilibrium structure of layering effectively can alleviate the expense of the high Wear leveling algorithm based on algebraically to the impact of system performance, therefore the major effect of system performance degradation is the exchange of the storage subregion performed in controller inside, and the impact of this expense on performance maintains about 1.56%.
Those skilled in the art will readily understand; the foregoing is only preferred embodiment of the present invention; not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1., based on an abrasion equilibrium method for the nonvolatile memory system of multilevel-cell, it is characterized in that, comprise the steps:
(1) each wafer of the storage area of nonvolatile memory system is divided into multiple sub-storage areas, each sub-storage areas is made up of several physical lines;
(2) to each sub-storage areas, after it often performs P write request, use the Wear leveling algorithm based on algebraically to exchange data in the physical line of this sub-storage areas at random, thus realize inside, sub-storage areas write number of times balance; Wherein, P is the exchange cycle of the predetermined Wear leveling algorithm based on algebraically;
(3) after the storage area of nonvolatile memory system often performs T write request, from each sub-storage areas, choose " heat " sub-storage areas and " cold " sub-storage areas carry out exchanges data, thus the number of times of writing realized between sub-storage areas balances; Wherein, T is mapping of field interval, is predetermined value or random number, and " heat " sub-storage areas refers to that access is comparatively frequent, and the more sub-storage areas of number of times is write in accumulation, and " cold " sub-storage areas refers to that access infrequently, and the less sub-storage areas of number of times is write in accumulation.
2., as claimed in claim 1 based on the abrasion equilibrium method of the nonvolatile memory system of multilevel-cell, it is characterized in that, T is predetermined value, and described step (3) comprises the steps: further
(3-1) average accumulated calculating sub-storage areas writes number of times
accumulation is write the sub-storage areas of number of times higher than mean value as " heat " sub-storage areas, accumulation is write the sub-average sub-storage areas of number of times as " cold " sub-storage areas; Wherein, n is the number of sub-storage areas, w
ibe that number of times is write in the accumulation of i-th sub-storage areas;
(3-2) weights of each " heat " sub-storage areas are calculated
with the weights of each " cold " sub-storage areas
and then calculate the weights summation of " heat " sub-storage areas
the weights summation of " cold " sub-storage areas
(3-3) random number X is generated
1and X
2, make
(3-4) by X
1order deducts the weights of " heat " sub-storage areas one by one, works as X
1when≤0, choose corresponding " heat " sub-storage areas, by X
2order deducts the weights of " cold " sub-storage areas one by one, works as X
2when≤0, choose corresponding " cold " sub-storage areas;
(3-5) exchange the data of all physical lines of " heat " sub-storage areas chosen and " cold " sub-storage areas chosen, after performing T write request, return step (3-1).
3., as claimed in claim 1 based on the abrasion equilibrium method of the nonvolatile memory system of multilevel-cell, it is characterized in that, T is random number, and described step (3) comprises the steps: further
(3-1) generate random number N, calculate mapping of field interval T=N*K, wherein, K is the physics line number that each sub-storage areas comprises;
(3-2) after execution T write request, accumulation is write the maximum sub-storage areas of number of times as " heat " sub-storage areas, accumulation is write the sub-storage areas of least number of times as " cold " sub-storage areas;
(3-3) exchange the data of all physical lines of " heat " sub-storage areas and " cold " sub-storage areas, return step (3-1).
4. as claimed any one in claims 1 to 3 based on the abrasion equilibrium method of the nonvolatile memory system of multilevel-cell, it is characterized in that, complete the exchanges data of " heat " sub-storage areas and " cold " sub-storage areas by the following method:
(A1) calculate the exchange interval t=T/K that the single physical of " heat " sub-storage areas to be exchanged and " cold " sub-storage areas is capable, wherein, K is the physics line number that each sub-storage areas comprises;
(A2) often t write request is performed, just from " heat " sub-storage areas to be exchanged, choose a physical line, the physical line identical with offset address in " cold " sub-storage areas to be exchanged carries out exchanges data, until complete the exchanges data of all physical lines of " heat " sub-storage areas to be exchanged and " cold " sub-storage areas.
5. as claimed any one in claims 1 to 3 based on the abrasion equilibrium method of the nonvolatile memory system of multilevel-cell, it is characterized in that, in described step (2), the memory read-write caused by exchanges data operates and directly performs in wafer inside, not committed memory controller and bus resource.
6. as claimed any one in claims 1 to 3 based on the abrasion equilibrium method of the nonvolatile memory system of multilevel-cell, it is characterized in that, described step (3) is performed by Memory Controller Hub, and the memory read-write caused by exchanges data operates and takies bus resource.
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| CN105955891A (en) * | 2016-04-25 | 2016-09-21 | 华中科技大学 | Double-layer wear-leveling method and system |
| CN106980799A (en) * | 2017-03-10 | 2017-07-25 | 华中科技大学 | The nonvolatile memory encryption system that a kind of abrasion equilibrium is perceived |
| CN108920386A (en) * | 2018-07-20 | 2018-11-30 | 中兴通讯股份有限公司 | Abrasion equilibrium and access method, equipment and storage medium towards Nonvolatile memory |
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| CN105955891A (en) * | 2016-04-25 | 2016-09-21 | 华中科技大学 | Double-layer wear-leveling method and system |
| CN105955891B (en) * | 2016-04-25 | 2018-12-14 | 华中科技大学 | A kind of bilayer abrasion equilibrium method and system |
| CN106980799A (en) * | 2017-03-10 | 2017-07-25 | 华中科技大学 | The nonvolatile memory encryption system that a kind of abrasion equilibrium is perceived |
| CN110362268A (en) * | 2018-04-10 | 2019-10-22 | 阿里巴巴集团控股有限公司 | Abrasion equilibrium treating method and apparatus |
| CN110362268B (en) * | 2018-04-10 | 2023-10-03 | 阿里巴巴集团控股有限公司 | Wear balance processing method and device |
| CN108920386A (en) * | 2018-07-20 | 2018-11-30 | 中兴通讯股份有限公司 | Abrasion equilibrium and access method, equipment and storage medium towards Nonvolatile memory |
| CN108920386B (en) * | 2018-07-20 | 2020-06-26 | 中兴通讯股份有限公司 | Wear leveling and access method, equipment and storage medium for nonvolatile memory |
| US11320989B2 (en) | 2018-07-20 | 2022-05-03 | Zte Corporation | Wear leveling and access method and device for non-volatile memory, and storage medium |
| TWI718492B (en) * | 2019-03-12 | 2021-02-11 | 群聯電子股份有限公司 | Data storing method, memory storage apparatus and memory control circuit unit |
| CN110175385A (en) * | 2019-05-20 | 2019-08-27 | 山东大学 | A kind of non-volatile FPGA layout optimization method and system based on performance abrasion equilibrium |
| CN113918478A (en) * | 2020-07-10 | 2022-01-11 | 美光科技公司 | Memory wear management |
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