CN105068938A - Wear balancing method of non-volatile memory based on multi-level cell - Google Patents

Abstract

The invention discloses a wear leveling method of a non-volatile memory system based on multi-level units. Including: dividing each wafer in the storage area of the non-volatile memory system into multiple sub-storage areas; for each sub-storage area, after each execution of P write requests, use an algebra-based wear leveling algorithm to randomly exchange the sub-storage area Data in the physical row of the storage area; after every T write requests are executed in the storage area of the non-volatile memory system, a "hot" sub-storage area and a "cold" sub-storage area are selected from each sub-storage area for data Exchange; wherein, T is the area exchange interval, which is a predetermined value or a random number. storage area. The invention combines the advantages of the table-based wear leveling algorithm and the algebra-based wear leveling algorithm, and has the advantages of long service life, safety and reliability.

Description

A wear-leveling method for non-volatile memory based on multi-level cells

technical field

The invention belongs to the field of solid-state storage, and more specifically relates to a wear leveling method of a multi-level unit-based nonvolatile memory system.

Background technique

With the development of multi-core technology, computer systems have higher and higher requirements for memory, including capacity, power consumption, performance, scalability and other aspects. The development of traditional dynamic random access memory (Dynamic Random Access Memory, DRAM) is limited in the face of new application environments due to the constraints of scalability and leakage power consumption.

The emergence of new non-volatile memory (Non-VolatileMemory, NVM) technology provides a new solution for the development of memory systems. The current new non-volatile memory mainly includes phase change memory (PhaseChangeMemory, PCM) and memristor (ResistiveRandomAccessMemory, RRAM), which have the advantages of large capacity, low power consumption and high performance, and are the most competitive for next-generation memory. candidates. Compared with DRAM technology, these non-volatile memories have significant advantages in terms of energy consumption, performance, and scalability, and have attracted a lot of attention from academia and industry. The current research based on non-volatile memories is also a hot topic.

In order to improve the cost performance of NVM chips, multi-level cell technology (Multi-LevelCell, MLC) will be applied to the NVM system, which allows a cell to store 2 or 4 data bits, therefore, MLC-2/MLC-4 Compared with its single-layer version (Single-LevelCell, SLC), the chip has larger capacity and lower price advantages. But due to material limitations and over-programming operations, the endurance of MLC-2/MLC-4 chips is 100 times lower than that of their single-layer versions. The longevity issues posed by their low endurance limit became the main bottleneck for them to play the main memory role. In the SLC technology, the maximum write times of each unit in the PCM chip is 10 ⁷ -10 ⁸ , while that of the RRAM is 10 ⁸ -10 ¹² . In MLC technology, the durability of each unit in the PCM chip is 10 ⁵ -10 ⁶ , while RRAM can reach 10 ⁷ . Uniform write access can make NVM chips last for several years, but uneven write access can cause some memory cells to wear out within seconds, leading to memory failure. Therefore, it is particularly important to use wear leveling technology to convert unbalanced upper-layer write accesses into balanced lower-layer write accesses to prolong the service life of these NVM systems.

For the wear leveling algorithm of non-volatile memory, the existing research work can be divided into two categories - table-based wear leveling algorithm (TBWL) and algebra-based wear leveling algorithm (AWL). (1) Table-based wear leveling algorithm: This type of algorithm records the mapping relationship between each logical block and physical block, and also counts the write times of each logical block. Write gaps between blocks are balanced by periodically exchanging blocks with the highest and lowest write counts. Typical table-based wear leveling algorithms include line swapping (LineSwapping), segment swapping (SegmentSwapping), page swapping (PageSwapping), etc. The difference between them is that the granularity of the smallest switching unit is different, and there is a big gap between the storage space overhead and the switching time overhead. To achieve a high lifetime, the granularity of mapping and swapping units is required to be small enough, such as row swapping, but this incurs a very high space overhead. In addition, most table-based wear and tear algorithms use a deterministic swap strategy, which allows malicious programs to guess the new location of the area to be swapped, so as to carry out a brute force attack on a specific area, causing all rows in this area to be destroyed. worn out. (2) Algebra-based wear leveling algorithm: Typical algorithms include Start-Gap and SecurityRefresh. The algebra-based wear leveling algorithm periodically moves physical rows through algebraic mapping, and through a large number of row exchanges, the "hot" logical row can be moved to each physical row in probability, and its physical address can pass a given logical address and algebraic functions to obtain. The algebra-based wear leveling algorithm has the advantages of low overhead and high security, and has been applied in the prototype platform based on NVM.

With the application of MLC technology to the NVM system, the memory capacity has doubled, resulting in a large increase in the space overhead of the wear leveling algorithm based on the table. For example, in a 64GB system, the space overhead reaches 2.5GB, which cannot be applied to real system. The decrease in durability leads to a reduction in the number of exchanges based on the algebraic wear leveling algorithm. Insufficient exchange times lead to unbalanced write distribution, which directly leads to a low service life. In order to improve the efficiency of the algebra-based wear leveling algorithm, typical methods include increasing the exchange frequency and increasing the number of regions. Increasing the swap frequency will lead to performance degradation, and increasing the number of regions will worsen the unbalanced write traffic between regions, which will reduce the service life.

Contents of the invention

Aiming at the above defects or improvement needs of the prior art, the present invention provides a wear leveling method based on a multi-layer unit non-volatile memory system, which organically combines the advantages of a table-based wear leveling algorithm and an algebra-based wear leveling algorithm And overcome their respective defects, with long life and the advantages of safety and reliability.

In order to achieve the above object, the present invention provides a wear leveling method of a non-volatile memory system based on multi-level units, which is characterized in that it includes the following steps: (1) each chip in the storage area of the non-volatile memory system The unit is divided into multiple sub-storage areas, and each sub-storage area is composed of several physical rows; (2) For each sub-storage area, after each execution of P write requests, the sub-storage area is randomly exchanged using an algebra-based wear leveling algorithm The data in the physical row of the area, so as to realize the balance of write times inside the sub-storage area; where, P is the exchange cycle of the predetermined algebra-based wear leveling algorithm; (3) every time T is executed in the storage area of the non-volatile memory system After a write request, a "hot" sub-storage area and a "cold" sub-storage area are selected from each sub-storage area for data exchange, so as to achieve a balance of write times between the sub-storage areas; where T is the area exchange interval , is a predetermined value or a random number, the "hot" sub-storage area refers to the sub-storage area with more frequent access and more cumulative write times, and the "cold" sub-storage area refers to the sub-storage area with less frequent access and less cumulative write times area.

Preferably, T is a predetermined value, and the step (3) further includes the following steps: (3-1) calculating the average cumulative write times of the sub-storage area A sub-storage area with a cumulative write count higher than the average value is regarded as a "hot" sub-storage area, and a sub-storage area with a cumulative write count lower than the average value is regarded as a "cold" sub-storage area; wherein, n is the number of sub-storage areas , w _i is the cumulative write times of the i-th sub-storage area; (3-2) Calculate the weight of each "hot" sub-storage area and the weights of each "cold" sub-storage region Then calculate the sum of the weights of the "hot" sub-storage area and the sum of the weights of the "cold" sub-storage regions (3-3) Generate random numbers X ₁ and X ₂ such that (3-4) Sequentially subtract the weight of the "hot" sub-storage area from X ₁ one by one. When X ₁ ≤ 0, select the corresponding "hot" sub-storage area, and subtract the weight of the "cold" sub-storage area from X ₂ one by one. The weight of the storage area, when X ₂ ≤ 0, select the corresponding "cold" sub-storage area; (3-5) exchange all physical rows of the selected "hot" sub-storage area and the selected "cold" sub-storage area data, after executing T write requests, return to step (3-1).

Preferably, T is a random number, and the step (3) further includes the following steps: (3-1) generating a random number N, and calculating the area exchange interval T=N*K, wherein K is the Number of physical rows; (3-2) After executing T write requests, use the sub-storage area with the largest cumulative write times as the "hot" sub-storage area, and use the sub-storage area with the least cumulative write times as the "cold" sub-storage area ; (3-3) Exchanging the data of all physical rows of the "hot" sub-storage area and the "cold" sub-storage area, and returning to step (3-1).

Preferably, the data exchange of the "hot" sub-storage area and the "cold" sub-storage area is accomplished by (A1) calculating the exchange of a single physical row of the "hot" sub-storage area and the "cold" sub-storage area to be exchanged Interval t=T/K, wherein, K is the number of physical lines that each sub-storage area contains; (A2) every time t write requests are executed, a physical line is selected from the "hot" sub-storage area to be exchanged, and The physical rows with the same offset address in the exchanged "cold" sub-storage area perform data exchange until the data exchange of all physical rows in the "hot" sub-storage area and the "cold" sub-storage area to be exchanged is completed.

Preferably, in the step (2), the memory read and write operations caused by data exchange are directly executed inside the wafer, without occupying memory controller and bus resources.

Preferably, the step (3) is executed by a memory controller, and memory read and write operations caused by data exchange occupy bus resources.

Generally speaking, compared with the prior art, the above technical solution conceived by the present invention has the following beneficial effects:

1. It organically combines the table-based wear leveling algorithm and the algebra-based wear leveling algorithm. Its core idea is to divide the entire space into many sub-storage areas, adopt algebra-based wear leveling algorithm inside the area, and use table-based wear leveling algorithm between areas, so as to achieve low space overhead and high service life.

2. Execute a single-layer algebra-based wear leveling algorithm in the NVM wafer (bank), that is, each sub-storage area is completely independent, which avoids the additional requests sent by the algebra-based wear leveling algorithm to occupy the bus. Performance degradation problem, while enabling the upper memory controller to accurately record the cumulative write times of each storage sub-area.

3. Execute the table-based sub-storage area wear leveling algorithm in the memory controller, which can effectively use more hardware resources and adopt more complex exchange strategies to balance the write times of all sub-storage areas within and between wafers , while obtaining high service life and safety.

Description of drawings

1 is a schematic diagram of the principle of a wear leveling method for a non-volatile memory system based on multi-level cells according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of the principle of the fine-grained exchange method.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not constitute a conflict with each other.

In order to facilitate understanding of the present invention, at first the following nouns appearing in the present invention are explained:

Physical row: The most basic access unit of the memory system. In different systems, the row size can be different, usually a row size can be 64 bytes, 128 bytes, 256 bytes.

Sub-storage area: composed of several physical rows, usually a sub-storage area can be composed of 2048, 4096 or 8192 rows.

Physical address: The address corresponding to the physical device, which is a real address.

Logical address: The address requested by the upper application program, which is a virtual address.

"Hot" sub-storage area: specifically refers to a sub-storage area with frequent access and a large number of accumulated write times.

"Cold" sub-storage area: specifically refers to a sub-storage area that is accessed infrequently and has a small cumulative number of writes.

FIG. 1 is a schematic diagram of a wear leveling method for a non-volatile memory system based on multi-level cells according to an embodiment of the present invention. The non-volatile memory controller contains the area swap, address map, and request queue modules. The address mapping table counts the physical area number corresponding to each logical area number, the accumulated write times and the time of the latest exchange. The cumulative write count and swap time are for accurate swapping of hot and cold regions. In addition, area exchange also needs to use a register set, including 4 registers, two of which record the area currently being exchanged, one register records the number of rows that have been exchanged, and the last register records the cumulative write times of the memory. Registers are used to trigger zone swaps. The single-layer algebra-based wear leveling module is integrated in NVMbank, and each algebra-based wear leveling module independently manages an area. The algebra-based wear leveling module is implemented using pure hardware, which has the advantages of low overhead and low latency.

In addition, aiming at the poor security of the table-based wear leveling algorithm, the present invention uses a random exchange strategy, so that malicious programs cannot guess the exchange time and new physical location. At the same time, the present invention designs a fine-grained exchange mode, which can avoid performance degradation during area exchange.

In order to balance the unbalanced write distribution among rows in a region, the present invention uses a single-layer algebra-based wear leveling algorithm to manage each region independently, so that the "hot" row with a large number of writes can be quickly compared with the rows in the region. Other rows are swapped to avoid premature wear-through of one row. Typical algebra-based wear leveling algorithms include Start-Gap and SecurityRefresh. Start-Gap is to reserve a blank line inside each area, and periodically exchange the blank line with its neighbors. Start-Gap needs 3 registers, which respectively store the physical address corresponding to the minimum logical address, the blank line pointer and the write counter. SecurityRefresh periodically moves all rows by a random offset. After each round of exchange, a new secret key (key) is randomly generated as the moving distance for the next round. SecurityRefresh requires 4 registers to store the secret key of the previous round, the secret key of the current round, the current internal exchange pointer and the write counter. An algebra-based wear leveling algorithm balances the number of writes between rows within a region with very low computational and storage overhead. In algebraic mapping, there is a functional mapping relationship between the logical row address and the physical row address, and the physical row address corresponding to the logical row address can be obtained through simple algebraic calculation. In the present invention, each region independently implements an algebra-based wear leveling strategy, so that "hot" regions can move more efficiently. The algebra-based wear module is implemented using pure hardware, which has the advantage of low latency.

As mentioned above, the wear leveling algorithm based on algebra makes it possible to well achieve the goal of load balancing within each area in the non-volatile memory.

The wear leveling method of the non-volatile memory system based on the multi-layer unit in the embodiment of the present invention comprises the following steps:

(1) Each wafer in the storage area of the NVM system is divided into multiple sub-storage areas, and each sub-storage area is composed of several physical rows.

(2) For each sub-storage area, after each execution of P write requests, use an algebra-based wear leveling algorithm to randomly exchange the data in the physical row of the sub-storage area, so as to achieve the balance of write times inside the sub-storage area.

Among them, the memory read and write operations caused by data exchange are directly executed inside the chip, and do not occupy memory controller and bus resources; P is the exchange period of the algebra-based wear leveling algorithm, which is a predetermined value, and the wear leveling of the present invention is considered comprehensively. The value of P is chosen for the lifetime and performance of the method. Preferably, P∈(8,128), at which point the wear leveling method of the present invention has a moderate lifespan while its performance degradation is maintained between 0.78% and 12.5%.

(3) After each execution of T write requests in the storage area of the NVM system, a "hot" sub-storage area and a "cold" sub-storage area are selected from each sub-storage area for data exchange, thereby realizing The number of writes is balanced.

Among them, T is a predetermined value or a random number, the "hot" sub-storage area refers to the sub-storage area with more frequent access and more cumulative write times, and the "cold" sub-storage area refers to the sub-storage area with infrequent access and less cumulative write times sub storage area. This step is performed by the memory controller, and memory read and write operations caused by data exchange occupy bus resources.

By performing the above steps (2) and (3), the balance of write times within the sub-storage areas and between the sub-storage areas is completed at different levels, thereby achieving wear leveling.

In order to balance the write traffic between areas and avoid brute-force area attacks, traditional deterministic exchange algorithms, such as periodically exchanging the coldest and hottest areas, will cause malicious programs to track and brute-force attack specific physical area, resulting in early failure of the device. For example, for an area containing 2048 rows, using a deterministic algorithm, it only takes 39 minutes to be worn out maliciously. In order to avoid this phenomenon, the present invention designs a weighted random selection algorithm or dynamically adjusts the exchange cycle to complete exchange between regions. Therefore, malicious programs cannot detect the new location and exchange time of the exchanged area, thereby effectively avoiding attacks.

In one embodiment of the present invention, the "cold" sub-storage area and the "hot" sub-storage area to be exchanged are selected by a weight-based random selection algorithm, and above-mentioned step (3) further includes the following steps:

(3-1) Calculate the average cumulative write times of the sub-storage area A sub-storage area with a cumulative write count higher than the average value is regarded as a "hot" sub-storage area, and a sub-storage area with a cumulative write count lower than the average value is regarded as a "cold" sub-storage area; wherein, n is the number of sub-storage areas , w _i is the cumulative write times of the i-th sub-storage area.

(3-2) Calculate the weight of each "hot" sub-storage area and the weights of each "cold" sub-storage region Then calculate the sum of the weights of the "hot" sub-storage area and the sum of the weights of the "cold" sub-storage regions

(3-3) Generate random numbers X ₁ and X ₂ such that $x_1\&Element;\&lsqb;0,\underset{w_i>\stackrel{\&OverBar;}{w}}{\&Sigma;}{W}_i\&rsqb;,x_2\&Element;\&lsqb;0,\underset{w_i<\stackrel{\&OverBar;}{w}}{\&Sigma;}{W}_i\&rsqb;.$

(3-4) Sequentially subtract the weight of the "hot" sub-storage area from X ₁ one by one. When X ₁ ≤ 0, select the corresponding "hot" sub-storage area, and subtract the weight of the "cold" sub-storage area from X ₂ one by one. The weight of the storage area. When X ₂ ≤ 0, the corresponding "cold" sub-storage area is selected.

(3-5) Exchanging the data of all the physical rows of the selected "hot" sub-storage area and the selected "cold" sub-storage area, and returning to step (3-1) after executing T write requests.

Wherein, T is the area exchange interval, which is a predetermined value, and the value of T is selected comprehensively considering the lifetime and performance of the wear leveling method. Preferably, T=128*K, at this time, the lifetime of the wear leveling method is moderate, and its performance degradation is maintained at about 1.56%, where K is the number of physical rows contained in each sub-storage area.

In one embodiment of the present invention, the "cold" sub-storage area and the "hot" sub-storage area to be exchanged are selected by dynamically randomly adjusting the exchange interval method, and the above-mentioned step (3) further includes the following steps:

(3-1) Generate a random number N, and calculate an area exchange interval T=N*K, where K is the number of physical rows contained in each sub-storage area.

The smaller N is, the longer the lifetime of the wear leveling method will be, but at the same time it will cause its performance to degrade, and vice versa. Preferably, N∈(64,256), at which point the lifetime of the wear leveling method is moderate while its performance degradation is maintained between 3.13% and 0.78%.

(3-2) After executing T write requests, use the sub-storage area with the largest accumulated write times as the "hot" sub-storage area, and use the sub-storage area with the least accumulated write times as the "cold" sub-storage area.

(3-3) Exchange the data of all physical rows of the "hot" sub-storage area and the "cold" sub-storage area, and return to step (3-1).

When exchanging data between two sub-storage areas, all physical rows of the two sub-storage areas will be migrated, and the exchanged requests will fill up the request queue, which will block normal execution requests. At this time, NVM memory cannot provide upper-layer services. For example, a sub-storage area contains 2048 rows, and it takes 6.1ms to complete the data exchange. In order to avoid performance degradation, the embodiment of the present invention adopts a fine-grained exchange method to migrate data of all physical rows one by one.

The fine-grained exchange method includes the following steps:

(A1) Calculate the exchange interval t=T/K of a single physical row of the "hot" sub-storage area and the "cold" sub-storage area to be exchanged.

(A2) Every time t write requests are executed, a physical row is selected from the "hot" sub-storage area to be exchanged, and the data is exchanged with the physical row with the same offset address in the "cold" sub-storage area to be exchanged until Complete the data exchange of all physical rows of the "hot" sub-storage area and the "cold" sub-storage area to be exchanged.

Specifically, as shown in Figure 2, store the number of the area to be exchanged in the register, and each time t write requests are executed, two rows with the same offset are selected from the two areas to be exchanged for exchange, that is, from the two The data of one row is read in the area, and written to the position of the other party. At the same time, the exchange pointer is incremented by 1. When the exchange pointer value reaches N, the exchange is completed and the value of the register is cleared.

The following evaluates the wear leveling method of the non-volatile memory system based on multi-level units in the present invention from the aspects of space overhead, time overhead, additional write overhead, and performance impact.

We store the address mapping table in SRAM to facilitate capacity expansion and support more banks. Use four 32-bit registers to store the values needed for area swapping. Assuming that the capacity of the entire non-volatile memory C=64GB, it contains M sub-storage areas (M=65536), each sub-storage area requires 12 bytes of storage space, and uses a 4-byte space to store the physical address, Cumulative write count and last swap time. All space overhead is: OSUM=(3*M*4+4*4) bytes=(12*M+16) bytes=256KB. It can be seen that the wear leveling method of the non-volatile memory system based on multi-layer units of the present invention has very low requirements on hardware resources.

The method of the present invention has two parts of time overhead: the time overhead of address conversion and the time overhead of executing the area selection algorithm. The memory request needs to be converted from the logical area address to the physical area address inside the controller, so the address mapping table needs to be looked up in the SRAM, and the time for looking up the table is 3 to 5 processing cycles. The memory request needs to be switched from the logical offset address to the physical offset address inside the non-volatile wafer, which requires 1 to 2 processing cycles. Compared with the time consumed by read and write operations, this delay can be ignored. However, the execution of the weight-based random selection algorithm needs to access all the data in the SRAM, and the consumption time reaches the microsecond level. We execute it in the background, thereby hiding the execution time and mitigating its impact on normal requests.

Additional write overhead and performance impact: Since the wear leveling algorithm introduces additional requests, these exchange requests will block the execution of normal requests and occupy the system bus and other hardware resources, resulting in performance degradation. The formula for calculating the additional write overhead is 1/P+2/t, where P is the exchange period of the algebra-based wear leveling algorithm, and t is the exchange interval of a single physical row in the sub-storage area. Usually t=128, P=8-64, and the additional write overhead is 3.1%-14.1% at this time. However, we adopt a layered wear leveling structure that can effectively alleviate the impact of the high overhead of the algebra-based wear leveling algorithm on system performance. Therefore, the main impact of system performance degradation is the exchange of storage sub-areas performed inside the controller. This overhead The impact on performance remains around 1.56%.

Those skilled in the art can easily understand that the above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention, All should be included within the protection scope of the present invention.

Claims (6)

1., based on an abrasion equilibrium method for the nonvolatile memory system of multilevel-cell, it is characterized in that, comprise the steps:

(1) each wafer of the storage area of nonvolatile memory system is divided into multiple sub-storage areas, each sub-storage areas is made up of several physical lines;

(2) to each sub-storage areas, after it often performs P write request, use the Wear leveling algorithm based on algebraically to exchange data in the physical line of this sub-storage areas at random, thus realize inside, sub-storage areas write number of times balance; Wherein, P is the exchange cycle of the predetermined Wear leveling algorithm based on algebraically;

(3) after the storage area of nonvolatile memory system often performs T write request, from each sub-storage areas, choose " heat " sub-storage areas and " cold " sub-storage areas carry out exchanges data, thus the number of times of writing realized between sub-storage areas balances; Wherein, T is mapping of field interval, is predetermined value or random number, and " heat " sub-storage areas refers to that access is comparatively frequent, and the more sub-storage areas of number of times is write in accumulation, and " cold " sub-storage areas refers to that access infrequently, and the less sub-storage areas of number of times is write in accumulation.

2., as claimed in claim 1 based on the abrasion equilibrium method of the nonvolatile memory system of multilevel-cell, it is characterized in that, T is predetermined value, and described step (3) comprises the steps: further

(3-1) average accumulated calculating sub-storage areas writes number of times accumulation is write the sub-storage areas of number of times higher than mean value as " heat " sub-storage areas, accumulation is write the sub-average sub-storage areas of number of times as " cold " sub-storage areas; Wherein, n is the number of sub-storage areas, w _ibe that number of times is write in the accumulation of i-th sub-storage areas;

(3-2) weights of each " heat " sub-storage areas are calculated with the weights of each " cold " sub-storage areas and then calculate the weights summation of " heat " sub-storage areas the weights summation of " cold " sub-storage areas

(3-3) random number X is generated ₁and X ₂, make

(3-4) by X ₁order deducts the weights of " heat " sub-storage areas one by one, works as X ₁when≤0, choose corresponding " heat " sub-storage areas, by X ₂order deducts the weights of " cold " sub-storage areas one by one, works as X ₂when≤0, choose corresponding " cold " sub-storage areas;

(3-5) exchange the data of all physical lines of " heat " sub-storage areas chosen and " cold " sub-storage areas chosen, after performing T write request, return step (3-1).

3., as claimed in claim 1 based on the abrasion equilibrium method of the nonvolatile memory system of multilevel-cell, it is characterized in that, T is random number, and described step (3) comprises the steps: further

(3-1) generate random number N, calculate mapping of field interval T=N*K, wherein, K is the physics line number that each sub-storage areas comprises;

(3-2) after execution T write request, accumulation is write the maximum sub-storage areas of number of times as " heat " sub-storage areas, accumulation is write the sub-storage areas of least number of times as " cold " sub-storage areas;

(3-3) exchange the data of all physical lines of " heat " sub-storage areas and " cold " sub-storage areas, return step (3-1).

4. as claimed any one in claims 1 to 3 based on the abrasion equilibrium method of the nonvolatile memory system of multilevel-cell, it is characterized in that, complete the exchanges data of " heat " sub-storage areas and " cold " sub-storage areas by the following method:

(A1) calculate the exchange interval t=T/K that the single physical of " heat " sub-storage areas to be exchanged and " cold " sub-storage areas is capable, wherein, K is the physics line number that each sub-storage areas comprises;

(A2) often t write request is performed, just from " heat " sub-storage areas to be exchanged, choose a physical line, the physical line identical with offset address in " cold " sub-storage areas to be exchanged carries out exchanges data, until complete the exchanges data of all physical lines of " heat " sub-storage areas to be exchanged and " cold " sub-storage areas.

5. as claimed any one in claims 1 to 3 based on the abrasion equilibrium method of the nonvolatile memory system of multilevel-cell, it is characterized in that, in described step (2), the memory read-write caused by exchanges data operates and directly performs in wafer inside, not committed memory controller and bus resource.

6. as claimed any one in claims 1 to 3 based on the abrasion equilibrium method of the nonvolatile memory system of multilevel-cell, it is characterized in that, described step (3) is performed by Memory Controller Hub, and the memory read-write caused by exchanges data operates and takies bus resource.