CN105068639B - A kind of method and system of dynamic control processor frequencies - Google Patents
A kind of method and system of dynamic control processor frequencies Download PDFInfo
- Publication number
- CN105068639B CN105068639B CN201510453061.8A CN201510453061A CN105068639B CN 105068639 B CN105068639 B CN 105068639B CN 201510453061 A CN201510453061 A CN 201510453061A CN 105068639 B CN105068639 B CN 105068639B
- Authority
- CN
- China
- Prior art keywords
- processor
- instruction
- caching
- instruction processing
- working frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses a kind of method and system of dynamic control processor frequencies, by presetting multistage instruction processing caching and multi-stage processor working frequency in processor, multistage instruction processing caching current storage status is detected, the multistage instruction processing buffer memory state is proportionate with processor working frequency；The storage state that caching is handled according to multistage instruction adjusts processor working frequency；The resource of processor can be rationally utilized, so as to reduce whole energy consumption.When the opposite processing working frequency of multistage instruction processing buffer memory of processor is excessively high, processor working frequency is adjusted to instruction processing and caches corresponding processor working frequency, ensure that various application programs smooth can be run, and when multistage instruction processing buffer memory versus operating frequency is relatively low, processor working frequency is adjusted to instruction processing and caches corresponding processor working frequency.
Description
Technical field
The present invention relates to terminal processing techniques field more particularly to a kind of dynamic control processor frequencies method and be
System.
Background technology
Fast development and universal, more and more use with intelligent terminal (for example, smart mobile phone, tablet computer etc.)
Family carries out web page browsing by using intelligent terminal, document process, reading electronic book, appreciates the various operations such as video/audio, pole
The big person of being convenient to use.
In practical applications, the required processor of different application programs, such as central processing unit
The speed of service (or working frequency) of (CentralProcessin Unit, CPU) or microprocessor etc. is different.It is for example, general
The required processor speed of service of file editor is relatively low, still, big when carrying out image real time transfer or web browsing etc.
During data volume transfer, processor must be run at higher velocities could meet program requirements.Since processor is not
Under the same speed of service, the noise difference of power consumption, fever and accessory is larger.If processor frequencies are higher, although processing
The speed of device process instruction but the power consumption of processor can be made higher, if processor frequencies are relatively low, although the work(of processor
It is slower to consume speed relatively low but that processor process instruction can be made.For energy saving, reduction calorific value and the work for improving processor
Performance, therefore, it is necessary to according to practical application demand, the corresponding working frequency for adjusting processor.
Therefore, the prior art has yet to be improved and developed.
Invention content
The technical problem to be solved in the present invention is, in view of the deficiencies of the prior art, provides a kind of dynamic control processor
The method and system of frequency, by this method, can solve it is existing when processor is in the application program for running high load,
It can not be transformed into high working frequency with the increase of load from low working frequency, the implementation procedure of application program caused to block
Problem.Simultaneously solve it is existing when processor run low-load application program when, can not be with the reduction of load, from height
Working frequency is transformed into ground working frequency, the problem of power consumption of processing unit is caused to waste.
In order to solve the above-mentioned technical problem, the technical solution adopted in the present invention is as follows：
A kind of method of dynamic control processor frequencies, wherein, it the described method comprises the following steps：
The multistage instruction processing that S1, processor are preset for storing instruction caches and for adjusting at the multistage of working frequency
Manage device working frequency；
S2, detection multistage instruction processing caching current storage status；
S3, according to detection multistage instruction processing caching current storage status, to search pre-set with this be multistage instruction
The corresponding processor working frequency of storage state of caching is handled, is adjusted to current processor working frequency.
The method of the dynamic control processor frequencies, wherein, the step S1 is specifically included：
S11, processor preset the equal instruction processing caching of N grades of memory capacity and N+1 level processor working frequencies；
S12, default N grades of instructions processing caching deposit sequence are the various operation conversions of in chronological sequence sequence storage terminal
Instruction；
S13, default processor process instruction sequence be at the time order and function sequence by deposit multistage instruction processing caching
Reason, first be stored in multistage instruction processing caching instruction first handled, after be put into multistage instruction processing caching instruction after handled.
The method of the dynamic control processor frequencies, wherein, the step S1 is further included：Default N grades of instructions processing is slow
The correspondence with N+1 level processor working frequencies is deposited, correspondence is：
When instruction processing caching HC [1] is not piled when pending instruction in processor, the working frequency of processor is
PL [0],
When instruction processing caching HC [1] is piled when pending instruction in processor, the working frequency of processor is set
For PL [1],
When instruction processing caching HC [2] is piled when pending instruction in processor, the working frequency of processor is set
For PL [2],
When instruction processing caching HC [3] is piled when pending instruction in processor, the working frequency of processor is set
For PL [3],
...,
When instruction processing caching HC [N-1] is piled when pending instruction in processor, the work frequency of processor is set
Rate is PL [N-1],
When instruction processing caching HC [N] is piled when pending instruction in processor, the working frequency of processor is set
For PL [N].
The method of the dynamic control processor frequencies, wherein, it is further included before the step S2：Setting processing device starts
The frequency of work is PL [0], for minimum frequency in default N+1 level processor working frequencies.
The method of the dynamic control processor frequencies, wherein, the step S2 is specifically included：
It is instructed in S21, processor processing first order instruction processing caching；
The detection signal of S22, detection instruction processing caching, according to the storage shape of detection signal decision instruction processing caching
Whether state is filled with according to detection information decision instruction processing caching, processing is instructed to be filled with if detection signal is flat for height；
Processing caching is instructed if detection signal is low put down not to be filled with.
The method of the dynamic control processor frequencies, wherein, in the step S3, caching is handled according to multistage instruction
Storage state adjusts processor working frequency：
When x grades of instruction processing cachings are piled, and x+1 grades of instruction processing cachings are not piled, processor working frequency is updated to
PL [x], wherein, x 0,1,2,3 ..., N-1, N.
A kind of system of dynamic control processor frequencies, wherein, the system comprises：
Presetting module, the multistage instruction processing for pre-setting for storing instruction cache and for adjusting working frequency
Multi-stage processor working frequency；
Detection module, for detecting the storage state of multistage instruction processing caching；
Working frequency setup module, for being set in advance according to detection multistage instruction processing caching current storage status, lookup
Put with this be multistage instruction processing caching the corresponding processor working frequency of storage state, be adjusted to current processor work
Frequency.
The system of the dynamic control processor frequencies, wherein, the presetting module includes：
One caching presetting module, for setting the size of N grades of instruction processing cachings, instruction deposit sequence and instruction processing are suitable
Sequence；
One working frequency presetting module, for presetting N+1 level processor working frequencies.
The system of the dynamic control processor frequencies, wherein, the detection module includes：
One signal detection module, for detecting the detection signal of multistage instruction processing caching；
One judgment module, for judging the storage shape of multistage instruction processing caching according to the signal that signal detection module detects
State.
The system of the dynamic control processor frequencies, further includes：
One initialization module, for setting the initial value of processor working frequency.
Advantageous effect：Compared with prior art, the method and system of dynamic control processor frequencies provided by the present invention,
It is slow according to detection multistage instruction processing by presetting multistage instruction processing caching and multi-stage processor working frequency in processor
The storage state deposited realizes dynamic adjustment processor working frequency；The resource of processor can be rationally utilized, so as to reduce entirety
Energy consumption, when the opposite processing working frequency of multistage instruction processing buffer memory of processor is excessively high, by processor working frequency tune
It is whole to cache corresponding processor working frequency for instruction processing, ensure that various application programs smooth can be run, and in multistage
When instruction processing buffer memory versus operating frequency is relatively low, processor working frequency is adjusted to instruction processing and caches corresponding place
Manage device working frequency.It is solved by this method when processor is in the application program for running high load, it can not be with load
Increase, be transformed into high working frequency from low working frequency, cause application program implementation procedure occur interim card problem.It solves simultaneously
It has determined when processor is in the application program for running low-load, can not be transformed into ground from high working frequency with the reduction of load
Working frequency, the problem of power consumption of processing unit is caused to waste.It realizes processor working frequency and handles buffer memory with multistage instruction
The dynamic regulation of state, and it is adjusted quickly, accurately；Meet the processing speed of instruction and have and control energy consumption well.
Description of the drawings
Fig. 1 is the flow chart of the method preferred embodiment of dynamic control processor frequencies of the present invention.
Fig. 2 is the flow chart of the method specific embodiment of dynamic control processor frequencies of the present invention.
Fig. 3 is the functional schematic block diagram of dynamic control processor frequencies system of the present invention.
Specific embodiment
The present invention provide dynamic control processor frequencies method and system, for make the purpose of the present invention, technical solution and
Effect is clearer, clear and definite, and the present invention is described in more detail below.It should be appreciated that specific embodiment described herein
Only to explain the present invention, it is not intended to limit the present invention.
Below in conjunction with the accompanying drawings, by the description of the embodiment, being described further to invention content.
Fig. 1 is referred to, Fig. 1 is the flow chart of the method preferred embodiment of dynamic control processor frequencies of the present invention.Such as figure
It is shown, it the described method comprises the following steps：
S100, processor preset multistage instruction processing caching for storing instruction and the multistage for adjusting working frequency
Processor working frequency；
S200, detection multistage instruction processing caching current storage status；
S300, according to detection multistage instruction processing caching current storage status, to search pre-set with this be that multistage refers to
The corresponding processor working frequency of storage state of processing caching is enabled, is adjusted to current processor working frequency.
In the step s 100, the multistage instruction processing that processor is preset for storing instruction caches and for adjusting work frequency
The multi-stage processor working frequency of rate.Wherein, the multistage instruction processing caching is N grades of instruction processing cachings, is denoted as respectively：HC
[1]、HC[2]、HC[3]、……、HC[N-1]、HC[N]；The capacity of this N grades of instruction processing caching can be equal, capacity
Size is HCRL bytes, and HCRL is preset fixed value, and value can be set according to the application field of processor, this
In be not limited, only provide example and be illustrated, such as 20,30,40 etc., be preferably 20.In the N grades of instruction processing caching
N is preset fixed value, can be set according to the application field of processor, not be limited here, only provide example and add
To illustrate, such as 10,15,20 etc., it is preferably 10.
The multi-stage processor working frequency is N+1 level processor working frequencies, is denoted as respectively：PL[0]、PL[1]、PL
[2], PL [3] ..., PL [N-1], PL [N], wherein, the setting of the N in N+1 level processor working frequencies and value and instruction
The N of processing caching is identical, here just not in burden.Further, the N+1 level processors working frequency is incremental,
Value can be it is preset, can also default settings initial operating frequency PL [0], calculate PL [1] automatically according to increasing law
To PL [N], such as N+1 level processors working frequency is to be incremented by arithmetic progression, and with PL [0] for initial value, d is tolerance；It increases
Long speed can be automatically adjusted according to the application field of processor；It only needs that by setting PL [0] and d processing can be adjusted
The growth rate of device working frequency；In addition the increasing law of N+1 level processors working frequency can also use other methods, such as pass
Increase Geometric Sequence etc., do not do introduce one by one here, as long as N+1 level processors working frequency uses incremental situation, belong to
In the protection domain of the application.Here N+1 level processor working frequencies are illustrated, it is assumed that 3,4 processor working frequencies of N can
PL [0]=1.5GHz, PL [1]=1.8GHz, PL [2]=2.0GHz, PL [3]=2.5GHz is followed successively by with ascending.
In step s 200, detection multistage instruction processing caching current storage status, the multistage instruction processing are deposited
Storage state is proportionate with processor working frequency；Wherein, detection multistage instruction processing caching current storage status, is to pass through
It is preset in detection multistage instruction processing caching to detect signal to realize.That is judge multistage instruction by detecting signal
Processing caching current storage status, multistage instruction handles preset detection signal in caching, and, when processing is filled with, detection is believed
Number output is high ordinary mail number, when processing caching is not filled with, detection signal output is LOW signal, and processor is according to detecting
Height is flat or LOW signal judges multistage instruction processing caching current storage status.Further, the detection multistage instruction processing is slow
It is to detect in real time when depositing current storage status, the storage state of multistage instruction processing caching can be detected in real time, to processing
The load of device detects in real time, adjusts processor working frequency in real time so that processing is in optimal working condition in real time.It also may be used
To be periodically detected multistage instruction processing buffer memory state, period modulation is carried out to processor working frequency, can be reduced
The call number of the detection signal of processor reduces the energy consumption of processor.
The multistage instruction processing buffer memory state is proportionate with processor working frequency, that is to say, that when multistage refers to
Processing is enabled to be filled with more, processor working frequency is higher.
In step S300, according to detecting, multistage instruction processing caching current storage status, lookup is pre-set and is somebody's turn to do
It is the corresponding processor working frequency of storage state of multistage instruction processing caching, is adjusted to current processor working frequency,
Adjustment process is specially：
When instruction processing caching HC [1] is not piled when pending instruction in processor, the working frequency of processor is
PL [0],
When instruction processing caching HC [1] is piled when pending instruction in processor, the working frequency of processor is set
For PL [1],
When instruction processing caching HC [2] is piled when pending instruction in processor, the working frequency of processor is set
For PL [2],
When instruction processing caching HC [3] is piled when pending instruction in processor, the working frequency of processor is set
For PL [3],
...,
When instruction processing caching HC [N-1] is piled when pending instruction in processor, the work frequency of processor is set
Rate is PL [N-1],
When instruction processing caching HC [N] is piled when pending instruction in processor, the working frequency of processor is set
For PL [N].
That is x grades of instruction processing cachings of detection signal detection are piled, when x+1 grades of instruction processing cachings are not piled, place
Reason device working frequency be updated to PL [x], wherein, x 0,1,2,3 ..., N-1, N.
Further, the step S100 is specifically included：S110, the equal instruction of N grades of memory capacity is preset on a processor
Processing caching and N+1 grades of incremental processor working frequencies；S120, default N grades of instructions processing caching deposit sequence is temporally
The instruction of the various operation conversions of sequencing storage terminal；S130, the sequence of processor process instruction is preset as by deposit multistage
Instruction processing caching time order and function sequential processes, first be stored in multistage instruction processing caching instruction first handled, after be put into it is more
It is handled after the instruction of grade instruction processing caching.
Specifically, the equal instruction processing caching of N grades of memory capacity and N+1 grades of incremental places can be preset on a processor
Manage device working frequency；And N grades of instruction processing caching deposit sequences are the various operation conversions of in chronological sequence sequence storage terminal
Instruction；The sequence of default processor process instruction is the time order and function sequential processes cached by deposit multistage instruction processing, first
Deposit multistage instruction processing caching instruction first handled, after be put into multistage instruction processing caching instruction after handled；Also
It is most first occurred instruction deposit first order instruction processing caching, as instruction time of origin sequencing is sequentially stored at instruction
Reason caching, the deposit second level instruction processing caching after first order instructs processing buffer memory full, and so on.At processor
Reason instruction is instructed according to the time order and function sequential processes of instruction deposit memory, that is to say, that processor first handles first order instruction
Instruction in processing caching.And ensure that the storage state of instruction processing caching, in this way can be accurate to be filled with successively from front to back
True adjusts processor working frequency according to instruction processing buffer memory state.
It just stores, can be, but not limited to for ensureing that forwardmost instruction processing is filled with subsequent instruction processing caching
Using following process：It can be when handling the instruction in first order instruction processing caching, in second level instruction processing caching
Instruction is handled using the speed deposit first order instruction identical with processor processing speed in caching, subsequent instruction processing caching
Same operation is taken in instruction.It can also be used when the first order instructs the instruction in processing caching to handle, and directly handled
Instruction in second level instruction processing caching, and instruct processing buffer update slow for the first order instruction processing second level simultaneously
It deposits, third level instruction processing buffer update is second level instruction processing caching, and so on, the first order is instructed into processing caching more
It is new to be cached for N grades of instruction processing；Form instruction processing caching ring.
Further, include before the step S200：The frequency that setting processing device is started to work is PL [0], for default N
Minimum frequency in+1 level processor working frequency.
Further, the step S2 is specifically included：It is instructed in processor processing first order instruction processing caching；Detection instruction
The detection signal of caching is handled, whether is filled with according to detection signal decision instruction processing caching；Refer to if detection signal is high puts down
Processing is enabled to be filled with；Processing caching is instructed if detection signal is low put down not to be filled with.
To sum up, Fig. 2 is please referred to, Fig. 2 is the flow chart of the method specific embodiment of dynamic control processor frequencies of the present invention
Include the following steps：
Step S10, after processor enables, setting acquiescence working frequency is PL [0]；Receive processor finger to be treated
It enables and instruction is put into instruction processing caching by the time order and function sequence instructed；
Step S20, the detection signal of N grades of instruction processing cachings is detected, when the signal for detecting instruction processing caching CH [x]
Line performs step S30 when generating rising edge, and step is performed when the signal wire for detecting instruction processing caching CH [x] generates failing edge
Rapid S40；
Step S30, setting processor working frequency is PL [x]；Wherein, x 0,1,2,3 ..., N-1, N.
Step S40, setting processor working frequency is PL [x-1]；Wherein, x 0,1,2,3 ..., N-1, N.
The present invention also provides dynamic control processor frequencies systems, please refer to Fig. 3, wherein, the system comprises：
Presetting module 100, for pre-setting multistage instruction processing caching and multi-stage processor working frequency；
Detection module 200, for detecting the storage state of multistage instruction processing caching；
Working frequency setup module 300, for advance according to detection multistage instruction processing caching current storage status, lookup
Setting with this be multistage instruction processing caching the corresponding processor working frequency of storage state, be adjusted to current processor work
Working frequency.
The system of the dynamic control processor frequencies, wherein, the presetting module includes：
One caching presetting module, for setting the size of N grades of instruction processing cachings, instruction deposit sequence and instruction processing are suitable
Sequence；N grades of memory capacity are equal, instruction of the deposit sequence for the various operation conversions of in chronological sequence sequence storage terminal；Instruction
The processing sequence instructed in processing caching is by the time order and function sequential processes of deposit multistage instruction processing caching, and first deposit is multistage
Instruction processing caching instruction first handled, after be put into multistage instruction processing caching instruction after handled.
One working frequency presetting module, for presetting N+1 level processor working frequencies, processing working frequency is with series N's
Increase and increase.
The system of the dynamic control processor frequencies, wherein, the detection module includes：
One signal detection module, for detecting the detection signal of all instructions processing caching, detection signal is high ordinary mail number
Or LOW signal；
One judgment module, for judging the storage state of multistage instruction processing caching according to the signal that detection module detects；
Processing is instructed to be filled with if detection signal is high puts down；Processing caching is instructed if detection signal is low put down not to be filled with.
The system of the dynamic control processor frequencies, further includes：
For setting the initial value of processor working frequency, processor working frequency initial value is set for one initialization module
There is PL [0], be minimum value in N+1 level work frequencies.
In conclusion a kind of method and system of dynamic control processor frequencies provided by the invention, by processor
Default multistage instruction processing caching and multi-stage processor working frequency, detection multistage instruction processing caching current storage status, institute
Multistage instruction processing buffer memory state is stated to be proportionate with processor working frequency；The storage of caching is handled according to multistage instruction
State adjusts processor working frequency；The resource of processor can be rationally utilized, it is more when processor so as to reduce whole energy consumption
When the opposite processing working frequency of grade instruction processing buffer memory is excessively high, processor working frequency is adjusted to instruction processing caching pair
The processor working frequency answered ensures that various application programs smooth can be run, and handles buffer memory phase in multistage instruction
When relatively low to working frequency, processor working frequency is adjusted to instruction processing and caches corresponding processor working frequency.Pass through
It, can not be with the increase of load, from low work frequency this solves when processor is in the application program for running high load
Rate is transformed into high working frequency, causes the implementation procedure of application program that interim card problem occurs.It solves simultaneously when processor is being transported
During the application program of row low-load, it can not be transformed into ground working frequency with the reduction of load from high working frequency, cause to handle
The problem of device power wastage.Dynamic regulation of the processor working frequency with multistage instruction processing buffer memory state is realized, and
And it is adjusted quickly, accurately；Meet the processing speed of instruction and have and control energy consumption well.
It should be understood that the application of the present invention is not limited to the above, it for those of ordinary skills, can
To be improved or converted according to the above description, all these modifications and variations should all belong to the guarantor of appended claims of the present invention
Protect range.
Claims (8)
1. a kind of method of dynamic control processor frequencies, wherein, it the described method comprises the following steps：
S1, processor preset multistage instruction processing caching for storing instruction and the multi-stage processor for adjusting working frequency
Working frequency；
S2, detection multistage instruction processing caching current storage status；
S3, caching current storage status is handled according to detection multistage instruction, the pre-set and multistage instruction is searched and handles and delay
The corresponding processor working frequency of storage state deposited, is adjusted to current processor working frequency, wherein, at the multistage instruction
Reason buffer memory state is proportionate with processor working frequency, when multistage instruction processing is filled with more, processor work
Working frequency is higher；
The step S1 is specifically included：
S11, processor preset the equal instruction processing caching of N grades of memory capacity and N+1 level processor working frequencies；
The finger of S12, default N grades of instructions processing caching deposit sequence for the various operation conversions of in chronological sequence sequence storage terminal
It enables；
S13, time order and function sequential processes of the sequence of processor process instruction to handle caching by deposit multistage instruction are preset, it is first
Deposit multistage instruction processing caching instruction first handled, after be put into multistage instruction processing caching instruction after handled；
When the first order instructs the instruction in processing caching to handle, the instruction in second level instruction processing caching is directly handled,
And the second level instructed into processing buffer update simultaneously third level instruction processing buffer update is for first order instruction processing caching
Two level instruction processing caching, and so on, the first order is instructed into processing buffer update as N grades of instruction processing cachings；Formation refers to
Processing caching ring is enabled, to ensure that forwardmost instruction processing is filled with, subsequent instruction processing caching is just stored.
2. the method for dynamic control processor frequencies according to claim 1, which is characterized in that the step S1 is also wrapped
It includes：Default N grades of instructions processing caching and the correspondence of N+1 level processor working frequencies, correspondence are：
When instruction processing caching HC [1] is not piled when pending instruction in processor, the working frequency of processor is PL
[0],
When instruction processing caching HC [1] is piled when pending instruction in processor, the working frequency for setting processor is PL
[1],
When instruction processing caching HC [2] is piled when pending instruction in processor, the working frequency for setting processor is PL
[2],
When instruction processing caching HC [3] is piled when pending instruction in processor, the working frequency for setting processor is PL
[3],
...,
When instruction processing caching HC [N-1] is piled when pending instruction in processor, the working frequency for setting processor is
PL [N-1],
When instruction processing caching HC [N] is piled when pending instruction in processor, the working frequency for setting processor is PL
[N]。
3. the method for dynamic control processor frequencies according to claim 1, which is characterized in that before the step S2 also
Including：The frequency that setting processing device is started to work is PL [0], for minimum frequency in default N+1 level processor working frequencies.
4. the method for dynamic control processor frequencies according to claim 1, which is characterized in that the step S2 is specifically wrapped
It includes：
It is instructed in S21, processor processing first order instruction processing caching；
S22, the detection signal for detecting instruction processing caching handle the storage state of caching according to detection signal decision instruction, i.e.,
Whether it is filled with according to detection information decision instruction processing caching, processing is instructed to be filled with if detection signal is flat for height；If inspection
It is that low flat then instruct handles caching not to be filled with to survey signal.
5. the method for dynamic control processor frequencies according to claim 1, which is characterized in that in the step S3, root
The storage state adjustment processor working frequency cached is handled according to multistage instruction is：It is piled when x grades of instruction processing cache, x+1 grades
For instruction processing caching when not piling, processor working frequency is updated to PL [x], wherein, x 0,1,2,3 ..., N-1, N.
6. a kind of system of dynamic control processor frequencies, which is characterized in that the system comprises：
Presetting module, the multistage instruction processing for pre-setting for storing instruction cache and for adjusting the more of working frequency
Level processor working frequency；
Detection module, for detecting the storage state of multistage instruction processing caching；
Working frequency setup module, for pre-set according to detection multistage instruction processing caching current storage status, lookup
Processor working frequency corresponding with the storage state of multistage instruction processing caching, is adjusted to current processor working frequency,
Wherein, the multistage instruction processing buffer memory state is proportionate with processor working frequency, when multistage instruction processing caches
What is be filled with is more, and processor working frequency is higher；
The presetting module includes：
One caching presetting module, for setting the size of N grades of instruction processing cachings, instruction deposit sequence and instruction processing sequence；
One working frequency presetting module, for presetting N+1 level processor working frequencies；
When the first order instructs the instruction in processing caching to handle, the instruction in second level instruction processing caching is directly handled,
And the second level instructed into processing buffer update simultaneously third level instruction processing buffer update is for first order instruction processing caching
Two level instruction processing caching, and so on, the first order is instructed into processing buffer update as N grades of instruction processing cachings；Formation refers to
Processing caching ring is enabled, to ensure that forwardmost instruction processing is filled with, subsequent instruction processing caching is just stored.
7. the system of dynamic control processor frequencies according to claim 6, which is characterized in that the detection module packet
It includes：
One signal detection module, for detecting the detection signal of all instructions processing caching；
One judgment module, for judging the storage state of multistage instruction processing caching according to the signal that signal detection module detects.
8. the system of dynamic control processor frequencies according to claim 7, it is characterised in that it is further included：
One initialization module, for setting the initial value of processor working frequency.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510453061.8A CN105068639B (en) | 2015-07-29 | 2015-07-29 | A kind of method and system of dynamic control processor frequencies |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510453061.8A CN105068639B (en) | 2015-07-29 | 2015-07-29 | A kind of method and system of dynamic control processor frequencies |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105068639A CN105068639A (en) | 2015-11-18 |
| CN105068639B true CN105068639B (en) | 2018-06-19 |
Family
ID=54498025
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510453061.8A Active CN105068639B (en) | 2015-07-29 | 2015-07-29 | A kind of method and system of dynamic control processor frequencies |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105068639B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101477398A (en) * | 2008-12-25 | 2009-07-08 | 深圳华为通信技术有限公司 | Terminal power consumption control method and apparatus |
| CN102667665A (en) * | 2009-11-06 | 2012-09-12 | 超威半导体公司 | Controlling performance state by tracking probe activity level |
| CN103246340A (en) * | 2012-02-06 | 2013-08-14 | 索尼公司 | Device and method for dynamically adjusting frequency of central processing unit |
| CN103544062A (en) * | 2012-07-12 | 2014-01-29 | 华为技术有限公司 | Processing method and device of processor |
| CN103955264A (en) * | 2014-05-15 | 2014-07-30 | 乐视致新电子科技（天津）有限公司 | Method and system for dynamically regulating working frequency of processor |
| CN103970256A (en) * | 2014-04-22 | 2014-08-06 | 中国科学院计算技术研究所 | Energy saving method and system based on memory compaction and CPU dynamic frequency modulation |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8407501B2 (en) * | 2011-03-28 | 2013-03-26 | International Business Machines Corporation | Allocation of storage resources in a networked computing environment based on energy utilization |
-
2015
- 2015-07-29 CN CN201510453061.8A patent/CN105068639B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101477398A (en) * | 2008-12-25 | 2009-07-08 | 深圳华为通信技术有限公司 | Terminal power consumption control method and apparatus |
| CN102667665A (en) * | 2009-11-06 | 2012-09-12 | 超威半导体公司 | Controlling performance state by tracking probe activity level |
| CN103246340A (en) * | 2012-02-06 | 2013-08-14 | 索尼公司 | Device and method for dynamically adjusting frequency of central processing unit |
| CN103544062A (en) * | 2012-07-12 | 2014-01-29 | 华为技术有限公司 | Processing method and device of processor |
| CN103970256A (en) * | 2014-04-22 | 2014-08-06 | 中国科学院计算技术研究所 | Energy saving method and system based on memory compaction and CPU dynamic frequency modulation |
| CN103955264A (en) * | 2014-05-15 | 2014-07-30 | 乐视致新电子科技（天津）有限公司 | Method and system for dynamically regulating working frequency of processor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105068639A (en) | 2015-11-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101908022B (en) | Method and device for managing internal memory of mobile communication equipment terminal | |
| CN102821164B (en) | Efficient parallel-distribution type data processing system | |
| US8812789B2 (en) | Systems and methods for cache line replacement | |
| US20160117046A1 (en) | Data Reporting Method and Apparatus, and Terminal Device | |
| CN106569733A (en) | Processing method and processing device for buffered data | |
| TW201209581A (en) | Electronic device having operation mode dynamic adjusting mechanism and method of the same | |
| CN107515663A (en) | The method and apparatus for adjusting central processor core running frequency | |
| CN104182361B (en) | Data buffer storage processing method and processing device | |
| TW200519621A (en) | Method and system for dynamically determining web resource to be loaded and saving space | |
| CN101576768A (en) | Method and device for switching device frequency | |
| CN109685712A (en) | Image buffer storage and application method and device, terminal | |
| CN103631616B (en) | Picture is quickly loaded and caching method and system | |
| CN107463445A (en) | Application process priority management method, apparatus, storage medium and electronic equipment | |
| CN105068639B (en) | A kind of method and system of dynamic control processor frequencies | |
| CN103617264B (en) | Method and device for capturing timeliness seed page | |
| CN107046309B (en) | Charging method and device capable of automatically adjusting charging current | |
| CN105354079A (en) | Method for improving utilization rate of system memory | |
| CN105786572B (en) | Using installation position selection method and apply installation position selection device | |
| US20160275900A1 (en) | Adaptive partial screen update with dynamic backlight control capability | |
| US10331562B2 (en) | Real-time cache repair tool | |
| CN101394405A (en) | Method and apparatus for data request processing | |
| CN104935802A (en) | Image processing method, electronic equipment, and system | |
| CN105338013A (en) | Network loading method and apparatus | |
| CN107045864A (en) | The adjusting method and device of a kind of screen intensity | |
| CN102110130B (en) | Method for implementing microphone detection on web page |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20211112 Address after: No. 338, block B, No. 59, Fuqian street, Dongying District, Dongying City, Shandong Province, 257100 Patentee after: Dongying dongkai Airport Industrial Park Co., Ltd Address before: 315100 floor 10, No. 5, Lane 999, Yangfan Road, high tech Zone, Ningbo, Zhejiang Patentee before: TCL mobile communication technology (Ningbo) Co., Ltd |
|
| TR01 | Transfer of patent right |