CN105049392A - Signal generating method and device - Google Patents
Signal generating method and device Download PDFInfo
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- CN105049392A CN105049392A CN201510520493.6A CN201510520493A CN105049392A CN 105049392 A CN105049392 A CN 105049392A CN 201510520493 A CN201510520493 A CN 201510520493A CN 105049392 A CN105049392 A CN 105049392A
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Abstract
The invention discloses a signal generating method and device. The method comprises the following steps: generating a baseband complex signal clock, and performing frequency division on the baseband complex signal clock to obtain a pseudo-code driving clock; generating a lower sideband data code CAD, a lower sideband pilot frequency code CAP, an upper sideband data code CBD and an upper sideband pilot frequency code CBP according to the pseudo-code driving clock; modulating the CAD according to lower sideband data dA to obtain a lower sideband data channel baseband signal component C'AD, and modulating the CBD according to upper sideband data dB to obtain an upper sideband data channel baseband signal component C'BD; selecting one of C'AD and CAP to serve as a lower sideband baseband signal component CA, and selecting one of C'BD and CBP to serve as an upper sideband baseband signal component CB; looking up a corresponding in-phase signal and a corresponding orthogonal signal from a modulation mapping table according to the CA and the CB; and modulating the in-phase signal and the orthogonal signal to generate a wideband signal. Through adoption of the signal generating method and device, power can be allocated to four paths of signals according to practical demands.
Description
Technical field
The present invention relates to field of satellite navigation, particularly relate to a kind of signal creating method and device.
Background technology
Along with the lasting construction of GLONASS (Global Navigation Satellite System) (GNSS), navigation Service demand is in continuous expansion.The number of signals that each satellite navigation system is broadcast in same frequency range gets more and more, and limited satellite navigation frequency spectrum is originally become and more and more blocks up.
Modulation system is the emphasis of Navigation Signal System research, which determines the power spectral envelope of navigation signal, plays conclusive effect to the positioning-speed-measuring time service precision of navigation system, compatibility and the key performance such as interoperability, antijamming capability and index.In GPS modernization and galileo signals design process, modulation system design is the focus that industry is paid close attention to.The permanent envelope AltBOC modulation technique that Galileo system adopts at the signal of E5 frequency range, by four different navigation signal E5a-data, E5a-pilot, E5b-data, E5b-pilot is modulated into a complex signal, and is up-converted into as the broadband signal of centered by 1191.795MHz; Wherein E5a-data and E5a-pilot is equivalent to the signal of the QPSK modulation on E5a frequency (1176.45MHz), E5b-data and E5b-pilot is equivalent to the signal of the QPSK modulation on E5b frequency (1207.14MHz); Adopting and in this way four different navigation signals are modulated to a time multiplexed signal, can only be that four road signals distribute same power, and modulator approach be complicated.
Foregoing, only for auxiliary understanding technical scheme of the present invention, does not represent and admits that foregoing is prior art.
Summary of the invention
Main purpose of the present invention is to provide a kind of signal creating method and device, be intended to solve in prior art and four different navigation signals are being modulated to a time multiplexed signal, can only be that four road signals distribute same power, and the technical problem of modulator approach complexity.
For achieving the above object, the invention provides a kind of signal creating method, the method comprises:
S10, produce baseband complex signal clock, and frequency division is carried out to described baseband complex signal clock obtain pseudo-code and drive clock;
S11, drive clock to drive according to described pseudo-code to produce lower sideband numeric data code C
aD, lower sideband pilot code C
aP, upper sideband numeric data code C
bDwith upper sideband pilot code C
bP;
S12, according to lower sideband data d
amodulation C
aDobtain lower sideband data channel baseband signal component C '
aD, and according to upper sideband data d
bmodulation upper sideband numeric data code C
bDobtain upper sideband data channel baseband signal component C '
bD;
S13, from described C '
aDand C
aPmiddle selection one is as lower sideband baseband signal component C
a, and from described C '
bDand C
bPmiddle selection one is as upper sideband baseband signal component C
b;
S14, according to described C
aand C
bcorresponding in-phase signal and orthogonal signalling are found in the modulation mapping table preset;
S15, described in-phase signal and orthogonal signalling to be modulated in the frequency centered by modulating frequency, to generate the broadband signal of frequency centered by modulating frequency.
Preferably, described step S13 comprises:
S131, by described C
aPwith a fixing binary sequence C
sAcarry out XOR, obtain lower sideband data channel baseband signal component C '
aP; And by described C
bPwith a fixing binary sequence C
sBcarry out XOR, obtain upper sideband data channel baseband signal component C '
bP;
S132, from described C '
aDand C '
aPmiddle selection one is as lower sideband baseband signal component C
a, and from described C '
bDand C '
bPmiddle selection one is as upper sideband baseband signal component C
b.
Preferably, described step S13 comprises:
S133, according to first preset Slot selection rule from described C '
aDand C
aPmiddle selection one is as C
a; And preset Slot selection rule from described C ' according to second
bDand C
bPmiddle selection one is as C
b.
Preferably, after described step S13, the method also comprises:
S16, to described C
acarry out binary modulated and generate the first modulation result, and to described C
bcarry out binary modulated and generate the second modulation result;
S17, according to lower sideband complex subcarrier, the first modulation result to be modulated, and according to upper sideband complex subcarrier, the second modulation result is modulated, generate corresponding in-phase signal and orthogonal signalling;
S18, described in-phase signal and orthogonal signalling to be modulated in the frequency centered by modulating frequency, to generate the broadband signal of frequency centered by modulating frequency.
Preferably, described method also comprises:
S19, by all described C
aand C
bvalue combine, step S16 ~ step S17 is performed to each combination, obtains in-phase signal corresponding to each combination and orthogonal signalling, generate modulation mapping table.
Preferably, described step S12 comprises:
S121, by described d
awith C
aDcarry out XOR, obtain C '
aD; And by described d
bwith C
bDcarry out XOR, obtain C '
bD.
In addition, for achieving the above object, the present invention also provides a kind of signal generating apparatus, and this device comprises:
Clock generator, for generating baseband complex signal clock;
Frequency divider, obtains pseudo-code driving clock for carrying out frequency division to described baseband complex signal clock;
Pseudo-code generator, produces lower sideband numeric data code C for driving clock to drive according to described pseudo-code
aD, lower sideband pilot code C
aP, upper sideband numeric data code C
bDwith upper sideband pilot code C
bP;
First modulation module, for according to lower sideband data d
amodulation C
aDobtain lower sideband data channel baseband signal component C '
aD;
Second modulation module, for according to upper sideband data d
bmodulation C
bDobtain upper sideband data channel baseband signal component C '
bD;
First multiplexing selector, for from described C '
aDand C
aPmiddle selection one is as lower sideband baseband signal component C
a;
Second multiplexing selector, for from described C '
bDand C
bPmiddle selection one is as upper sideband baseband signal component C
b;
Search module, for according to described C
aand C
bcorresponding in-phase signal and orthogonal signalling are found in the modulation mapping table preset;
Radio-frequency modulator, for being modulated to described in-phase signal and orthogonal signalling with modulating frequency f
scentered by frequency on, generate the broadband signal of frequency centered by modulating frequency.
Preferably, described device also comprises the 3rd modulation module and the 4th modulation module;
Described 3rd modulation module, for by described C
aPwith a fixing binary sequence C
sAcarry out XOR, obtain lower sideband data channel baseband signal component C '
aP;
Described 4th modulation module, for by described C
bPwith a fixing binary sequence C
sBcarry out XOR, obtain upper sideband data channel baseband signal component C '
bP;
Described first multiplexing selector is also for from described C '
aDand C '
aPmiddle selection one is as lower sideband baseband signal component C
a;
Described second multiplexing selector, also for from described C '
bDand C '
bPmiddle selection one is as upper sideband baseband signal component C
b.
Preferably, described first multiplexing selector comprises the first timeslot multiplex selector, for presetting Slot selection rule from described C ' according to first
aDand C
aPmiddle selection one is as C
a;
Second multiplexing selector comprises the second timeslot multiplex selector, for presetting Slot selection rule from described C ' according to second
bDand C
bPmiddle selection one is as C
b.
Preferably, described device also comprises:
Subcarrier-modulated module, for described C
acarry out binary modulated and generate the first modulation result, and to described C
bcarry out binary modulated and generate the second modulation result; And according to lower sideband complex subcarrier, the first modulation result is modulated, and according to upper sideband complex subcarrier, the second modulation result is modulated, generate corresponding in-phase signal and orthogonal signalling.
Preferably, described device also comprises: mapping table generation module, for by all described C
aand C
bvalue combine, obtain in-phase signal corresponding to each combination and orthogonal signalling by subcarrier-modulated module, generate modulation mapping table.
Preferably, described first modulation module comprises the first XOR device, for by described d
awith C
aDcarry out XOR, obtain C '
aD;
Described second modulation module comprises the second XOR device, for by described d
bwith C
bDcarry out XOR, obtain C '
bD.
Signal creating method of the present invention and device, generate baseband complex signal clock, and carry out frequency division to described baseband complex signal clock and obtain pseudo-code and drive clock; Drive clock to drive according to described pseudo-code and produce lower sideband numeric data code C
aD, lower sideband pilot code C
aP, upper sideband numeric data code C
bDwith upper sideband pilot code C
bP; According to lower sideband data d
amodulation C
aDobtain lower sideband data channel baseband signal component C '
aD, and according to upper sideband data d
bmodulation upper sideband numeric data code C
bDobtain upper sideband data channel baseband signal component C '
bD; From described C '
aDand C
aPmiddle selection one is as lower sideband baseband signal component C
a, and from described C '
bDand C
bPmiddle selection one is as upper sideband baseband signal component C
b; According to described C
aand C
bcorresponding in-phase signal and orthogonal signalling are found in the modulation mapping table preset; Described in-phase signal and orthogonal signalling are modulated in the frequency centered by modulating frequency, generate the broadband signal of frequency centered by modulating frequency; Namely to input four road signal madulation to a time multiplexed signal, can flexibly from this C '
aDand C
aPmiddle selection one is as lower sideband baseband signal component C
aand from this C '
bDand C
bPmiddle selection one is as C
bcarry out multiplexing, be that four road signals distribute power according to actual needs, and the power of this four roads signal need not be made necessary identical, and the method is simple, is easy to realize.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the first embodiment of signal creating method of the present invention;
Fig. 2 is the schematic flow sheet of the second embodiment of signal creating method of the present invention;
Fig. 3 is the schematic diagram of cosine binary system subcarrier of the present invention;
Fig. 4 is the schematic diagram of sinusoidal binary system subcarrier of the present invention;
Fig. 5 is the structural representation of the first embodiment of signal generating apparatus of the present invention;
Fig. 6 is the structural representation of the second embodiment of signal generating apparatus of the present invention.
The realization of the object of the invention, functional characteristics and advantage will in conjunction with the embodiments, are described further with reference to accompanying drawing.
Embodiment
Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
With reference to the schematic flow sheet that Fig. 1, Fig. 1 are the first embodiment of signal creating method of the present invention, the method comprises:
S10, generate baseband complex signal clock, and frequency division is carried out to this baseband complex signal clock obtain pseudo-code and drive clock.
The selection of this baseband complex signal clock CLK0 is the integral multiple of the least common multiple of pseudo-code clock frequency and four times of sub-carrier frequencies.In one embodiment, pseudo-code clock frequency is 10.23MHz, and sub-carrier frequencies is 15.345MHz, and four times of sub-carrier frequencies are 61.38MHz.The least common multiple of pseudo-code clock frequency and sub-carrier frequencies is 61.38MHz, and therefore baseband complex signal clock CLK0 can select 61.38MHz.
In this step, carry out six frequency divisions to baseband complex signal clock CLK0 and obtain pseudo-code driving clock CLK1, if the frequency as baseband signal clock CLK0 is 61.38MHz, then pseudo-code drives the frequency of clock CLK1 to be 10.23MHz, i.e. code frequency f
cfor 10.23MHz.
S11, drive clock CLK1 to drive according to this pseudo-code to produce lower sideband numeric data code C
aD, lower sideband pilot code C
aP, upper sideband numeric data code C
bDwith upper sideband pilot code C
bP.
Drive clock CLK1 to drive pseudo-code generator to produce four different length according to this pseudo-code to be the pseudo noise code of 10230, to be respectively lower sideband numeric data code C
aD, lower sideband pilot code C
aP, upper sideband numeric data code C
bDwith upper sideband pilot code C
bP, the value of pseudo noise code is+1 or-1.The cycle of pseudo noise code is 1ms.
S12, according to lower sideband data d
amodulation C
aDobtain lower sideband data channel baseband signal component C '
aD, and according to upper sideband data d
bmodulation C
bDobtain upper sideband data channel baseband signal component C '
bD.
Lower sideband data d
arepresent the data bit of lower sideband data channel modulation, upper sideband data d
brepresent the data bit of upper sideband data channel modulation.
In one embodiment, according to d
amodulation C
aDobtain C '
aD, and according to d
bmodulation C
bDobtain C '
bDstep comprise: by this d
awith C
aDcarry out XOR, obtain C '
aD; And by this d
bwith C
bDcarry out XOR, obtain C '
bD.
S13, from this C '
aDand C
aPmiddle selection one is as lower sideband baseband signal component C
a, and from this C '
bDand C
bPmiddle selection one is as upper sideband baseband signal component C
b.
In one embodiment, this step S13 comprises: S131, by C
aPwith a fixing binary sequence C
sAcarry out XOR, obtain lower sideband pilot channel baseband signal component C '
aP; And by C
bPwith a fixing binary sequence C
sBcarry out XOR, obtain upper sideband pilot channel baseband signal component C '
bP; S132, from this C '
aDand C '
aPmiddle selection one is as C
a, and from this C '
bDand C '
bPmiddle selection one is as C
b.Binary sequence C
sAwith binary sequence C
sBthe length of each binary digit be the integral multiple of 1ms, and binary sequence C
sAwith binary sequence C
sBthe length of each binary digit and binary sequence C
sAwith binary sequence C
sBrepetition period can be different.Further, this step S132 comprises: preset time slot rule from this C ' according to the 3rd
aDand C '
aPmiddle selection one is as C
a; And preset time slot rule from this C ' according to the 4th
bDand C '
bPmiddle selection one is as C
b.
3rd default Slot selection rule and the 4th is preset Slot selection rule and can be pre-set, and the 3rd default Slot selection rule and the 4th is preset Slot selection rule and be may be the same or different.
3rd presets time slot rule is: when odd numbered slots, selects one to input as exporting, when even timeslots, select another input as exporting, then, in the corresponding edge band signal in the end generated, data-signal and pilot signal will respectively account for the power of half, as when odd numbered slots, from C '
aD, C '
aPmiddle selection C '
aDas output, when even timeslots, from C '
aD, C '
aPmiddle selection C '
aPas output; 3rd presets time slot rule can also be: in every m time slot, a spaced pick n time slot (n<m), using an input as output, another inputs as output by other m-n time slot in m time slot, in the corresponding edge band signal then in the end generated, the power ratio exported is respectively n/m, 1-n/m, as in n time slot of every m time slot, from C '
aD, C '
aPmiddle selection C '
aDas output, time in m-n time slot of every m time slot, from C '
aD, C '
aPmiddle selection C '
aPas output, then in the corresponding edge band signal in the end generated, the power ratio of data-signal is n/m, and the power ratio of pilot signal is 1-n/m.
3rd presets Slot selection rule is: when odd numbered slots, one is selected to input as exporting, when even timeslots, select another input as exporting, in the corresponding edge band signal then in the end generated, data-signal and pilot signal will respectively account for the power of half, as when odd numbered slots, from C '
bD, C '
bPmiddle selection C '
bDas output, when even timeslots, from C '
bD, C '
bPmiddle selection C '
bPas output; This second default time slot rule can also be: in every m time slot, a spaced pick n time slot (n<m), using an input as output, another inputs as output by other m-n time slot in m time slot, in the corresponding edge band signal then in the end generated, the power ratio exported is respectively n/m, 1-n/m, as in n time slot of every m time slot, from C '
bD, C '
bPmiddle selection C '
bDas output, time in m-n time slot of every m time slot, from C '
bD, C '
bPmiddle selection C '
bPmiddle component is as output, then in the corresponding edge band signal in the end generated, the power ratio of data-signal is n/m, and the power ratio of pilot signal is 1-n/m.
In another embodiment, this step S13 comprises: S133, according to first preset Slot selection rule from this C '
aDand C
aPmiddle selection one is as C
a; And preset Slot selection rule from this C ' according to second
bDand C
bPmiddle selection one is as C
b.
This first is preset Slot selection rule and second and presets Slot selection rule and can pre-set, and this first is preset Slot selection rule and may be the same or different with this second default Slot selection rule.
As the first default Slot selection rule is: when odd numbered slots, one is selected to input as exporting, when even timeslots, select another input as exporting, in the corresponding edge band signal then in the end generated, data-signal and pilot signal will respectively account for the power of half, as when odd numbered slots, from C '
aD, C
aPmiddle selection C '
aDas output, when even timeslots, from C '
aD, C
aPmiddle selection C
aPas output; This first default time slot rule can also be: in every m time slot, a spaced pick n time slot (n<m), using an input as output, another inputs as output by other m-n time slot in m time slot, in the corresponding edge band signal then in the end generated, the power ratio exported is respectively n/m, 1-n/m, as in n time slot of every m time slot, from C '
aD, C
aPmiddle selection C '
aDas output, time in m-n time slot of every m time slot, from C '
aD, C
aPmiddle selection C
aPas output, then in the corresponding edge band signal in the end generated, the power ratio of data-signal is n/m, and the power ratio of pilot signal is 1-n/m.
As this second default Slot selection rule is: when odd numbered slots, one is selected to input as exporting, when even timeslots, select another input as exporting, in the corresponding edge band signal then in the end generated, data-signal and pilot signal will respectively account for the power of half, as when odd numbered slots, from C '
bD, C
bPmiddle selection C '
bDas output, when even timeslots, from C '
bD, C
bPmiddle selection C
bPas output; This second default time slot rule can also be: in every m time slot, a spaced pick n time slot (n<m), using an input as output, another inputs as output by other m-n time slot in m time slot, in the corresponding edge band signal then in the end generated, the power ratio exported is respectively n/m, 1-n/m, as in n time slot of every m time slot, from C '
bD, C
bPmiddle selection C '
bDas output, time in m-n time slot of every m time slot, from C '
bD, C
bPmiddle selection C
bPmiddle component is as output, then in the corresponding edge band signal in the end generated, the power ratio of data-signal is n/m, and the power ratio of pilot signal is 1-n/m.
S14, according to this C
aand C
bcorresponding in-phase signal and orthogonal signalling are found in the modulation mapping table preset.
In one embodiment, when sub-carrier frequencies is 15.345MHz, the frequency f of baseband complex signal clock CLK0
0for the quadruple rate of subcarrier.This modulation mapping table preset as shown in Table 1.C
at () represents lower sideband baseband signal component, C
bt () represents upper sideband baseband signal component, S
it () represents in-phase signal, S
qt () represents orthogonal signalling.
Table one:
Lower sideband baseband signal component as current input be 0 and the upper sideband baseband signal component of current input be 0, find corresponding in-phase signal S
it () is respectively 1 ,-1 ,-1,1 in the value in four out of phase moment of a sub-carrier cycle, find orthogonal signalling S
qt () is respectively 0,0,0,0 in the value in four out of phase moment of a sub-carrier cycle.
S15, this in-phase signal and orthogonal signalling to be modulated in the frequency centered by modulating frequency, to generate the broadband signal of frequency centered by modulating frequency.
In this step, this in-phase signal and orthogonal signalling are modulated to modulating frequency f
scentered by frequency on, the formula of modulation is S
i(t) cos (2 π f
st)-S
q(t) sin (2 π f
st), generate with modulating frequency f
scentered by the broadband signal of frequency.
Adopt above-described embodiment, obtain pseudo-code driving clock by carrying out frequency division to baseband complex signal clock; Drive clock to drive according to described pseudo-code and produce lower sideband numeric data code C
aD, lower sideband pilot code C
aP, upper sideband numeric data code C
bDwith upper sideband pilot code C
bP; According to lower sideband data d
amodulation C
aDobtain lower sideband data channel baseband signal component C '
aD, and according to upper sideband data d
bmodulation upper sideband numeric data code C
bDobtain upper sideband data channel baseband signal component C '
bD; From described C '
aDand C
aPmiddle selection one is as lower sideband baseband signal component C
a, and from described C '
bDand C
bPmiddle selection one is as upper sideband baseband signal component C
b; According to described C
aand C
bcorresponding in-phase signal and orthogonal signalling are found in the modulation mapping table preset; Described in-phase signal and orthogonal signalling are modulated in the frequency centered by modulating frequency, generate the broadband signal of frequency centered by modulating frequency; Namely to input four road signal madulation to a time multiplexed signal, can flexibly from this C '
aDand C
aPmiddle selection one is as lower sideband baseband signal component C
aand from this C '
bDand C
bPmiddle selection one is as C
bcarry out multiplexing, be that four road signals distribute power according to actual needs, and the power of this four roads signal need not be made necessary identical, and the method is simple, is easy to realize.
With reference to the schematic flow sheet that Fig. 2, Fig. 2 are the second embodiment of signal creating method of the present invention.
Based on the first embodiment of above-mentioned signal creating method, after step s 13, the method also comprises:
S16, to this C
acarry out binary modulated and generate the first modulation result, and to this C
bcarry out binary modulated and generate the second modulation result.
In this step, to C
aand C
bcarry out binary modulated respectively, in one embodiment, modulation result as shown in Table 2, S
1t () represents the first modulation result, S
2t () represents the second modulation result.
Table two:
| C A(t) | C B(t) | S 1(t) | S 2(t) |
| 0 | 0 | 1/2 | 1/2 |
| 0 | 1 | 1/2 | －1/2 |
| 1 | 0 | －1/2 | 1/2 |
| 1 | 1 | －1/2 | －1/2 |
S17, according to lower sideband complex subcarrier, the first modulation result to be modulated, and according to upper sideband complex subcarrier, the second modulation result is modulated, generate corresponding in-phase signal and orthogonal signalling.
In this step, the first modulation result generate step S16 and the second modulation result are modulated to lower sideband and upper sideband respectively, and modulation formula is as follows: S (t)=S
1(t) e* (t)+S
1t () e (t), e* (t) represent the complex subcarrier of lower sideband, e (t) represents the complex subcarrier of upper sideband, e (t)=SC
cos(t)+jSC
sin(t), e* (t)=SC
cos(t)-jSC
sin(t), SC
cos(t)=sign (cos (2 π f
sCt)), SC
sin(t)=sign (sin (2 π f
sCt)), wherein, SC
cost () represents cosine binary system subcarrier, SC
sint () represents sinusoidal binary system subcarrier; f
sCfor sub-carrier frequencies, f
sC=15.345MHz.As shown in Figure 3, this sinusoidal binary system subcarrier as shown in Figure 4 for this cosine binary system subcarrier.
S (t) is expressed as the form of real part and imaginary part, S (t)=S
i(t)+jS
q(t)=(S
1(t)+S
2(t)) SC
cos(t)+j (S
2(t)-S
1(t)) SC
sin(t).The real part S of S (t)
it () represents in-phase signal, the imaginary part S of S (t)
qt () represents orthogonal signalling.Work as S
1(t)=1/2, S
2during (t)=1/2, this S (t)=SC
cost (), namely orthogonal signalling are 0, check that Fig. 3 can learn, S (t) is respectively 1 ,-1 ,-1,1 in the value in four out of phase moment in a cosine subcarrier cycle.
S18, this in-phase signal and orthogonal signalling to be modulated in the frequency centered by modulating frequency, to generate the broadband signal of frequency centered by modulating frequency.
In this step, this in-phase signal and orthogonal signalling are modulated to modulating frequency f
scentered by frequency on, the formula of modulation is S
i(t) cos (2 π f
st)-S
q(t) sin (2 π f
st), generate with modulating frequency f
scentered by the broadband signal of frequency.
Further, the method also comprises:
S19, by this C all
aand C
bvalue combine, step S16 ~ step S17 is performed to each combination, obtains in-phase signal corresponding to each combination and orthogonal signalling, generate modulation mapping table.
This C
acan value be 0,1, this C
bcan value 0,1, to this C
aand C
bvalue carry out combination in any, four combinations can be obtained, be respectively (0,0), (0,1), (1,0), (1,1), each combination is adopted to the subcarrier-modulated of same way, perform step S16 ~ step S17, obtain in-phase signal corresponding to each combination and orthogonal signalling, note down in-phase signal corresponding to each combination and orthogonal signalling, generate modulation mapping table.As being 15.345MHz in sub-carrier frequencies, the f of baseband complex signal clock CLK0
0for the quadruple rate of subcarrier, when pseudo-code drives the frequency of clock CLK1 to be 10.23MHz, the modulation mapping table of generation as shown in Table 1.
According to the combination of different code frequencies and sub-carrier frequencies, the frequency f of baseband complex signal
0code frequency f can be chosen as
cwith four times of sub-carrier frequencies f
sCleast common multiple, as in the present embodiment, code frequency is 10.23MHz, sub-carrier frequencies is 15.345MHz, then the frequency of baseband complex signal can be chosen as 61.38MHz.Engineering construction personnel can according to sub-carrier frequencies f
sCto baseband complex signal f
0different frequency dividing ratios, voluntarily according to formula construction look-up table, as structure table one.
With reference to the first example structure schematic diagram that Fig. 5, Fig. 5 are signal generating apparatus of the present invention, this device comprises:
Clock generator 19, for generating baseband complex signal clock;
Frequency divider 10, obtains pseudo-code driving clock for carrying out frequency division to this baseband complex signal clock;
Pseudo-code generator 11, produces lower sideband numeric data code C for driving clock to drive according to this pseudo-code
aD, lower sideband pilot code C
aP, upper sideband numeric data code C
bDwith upper sideband pilot code C
bP;
First modulation module 12, for according to lower sideband data d
amodulation C
aDobtain lower sideband data channel baseband signal component C '
aD;
Second modulation module 13, for according to upper sideband data d
bmodulation C
bDobtain upper sideband data channel baseband signal component C '
bD;
First multiplexing selector 14, for from this C '
aDand C
aPmiddle selection one is as lower sideband baseband signal component C
a;
Second multiplexing selector 15, for from this C '
bDand C
bPmiddle selection one is as upper sideband baseband signal component C
b;
Search module 16, for according to this C
aand C
bcorresponding in-phase signal and orthogonal signalling are found in the modulation mapping table preset;
Radio-frequency modulator 17, for being modulated to this in-phase signal and orthogonal signalling with modulating frequency f
scentered by frequency on, generate the broadband signal of frequency centered by modulating frequency.
This baseband complex signal clock CLK0 is four times of the generation clock of sub-carrier frequencies.In one embodiment, this baseband complex signal clock CLK0 can select the clock of 6 × 10.023MHz=61.38MHz.
The selection of this baseband complex signal clock CLK0 is the integral multiple of the least common multiple of pseudo-code clock frequency and four times of sub-carrier frequencies.In one embodiment, pseudo-code clock frequency is 10.23MHz, and sub-carrier frequencies is 15.345MHz, and four times of sub-carrier frequencies are 61.38MHz.The least common multiple of pseudo-code clock frequency and sub-carrier frequencies is 61.38MHz, and therefore baseband complex signal clock CLK0 can select 61.38MHz.
This frequency divider 10 couples of baseband complex signal clock CLK0 carry out six frequency divisions and obtain pseudo-code driving clock CLK1, and if the frequency as baseband signal clock CLK0 is 61.38MHz, then pseudo-code drives the frequency of clock CLK1 to be 10.23MHz, i.e. code frequency f
cfor 10.23MHz.
The length that this pseudo-code generator 11 drives clock CLK1 to drive generation four different according to this pseudo-code is the pseudo noise code of 10230, is respectively lower sideband numeric data code C
aD, lower sideband pilot code C
aP, upper sideband numeric data code C
bDwith upper sideband pilot code C
bP, the value of pseudo noise code is+1 or-1.The cycle of pseudo noise code is 1ms.
Lower sideband data d
arepresent the data bit of lower sideband data channel modulation, upper sideband data d
brepresent the data bit of upper sideband data channel modulation.
In one embodiment, this first modulation module 12 comprises the first XOR device, for by this lower d
awith C
aDcarry out XOR, obtain C '
aD; This second modulation module 13 comprises the second XOR device, for by this d
bwith C
bDcarry out XOR, obtain C '
bD.
In one embodiment, this first multiplexing selector 14 comprises the first timeslot multiplex selector, for presetting Slot selection rule from this C ' according to first
aDand C
aPmiddle selection one is as C
a;
Second multiplexing selector 15 comprises the second timeslot multiplex selector, for presetting Slot selection rule from this C ' according to second
bDand C
bPmiddle selection one is as C
b.
This first is preset Slot selection rule and second and presets Slot selection rule and can pre-set, and this first is preset Slot selection rule and may be the same or different with this second default Slot selection rule.
As the first default Slot selection rule is: when odd numbered slots, one is selected to input as exporting, when even timeslots, select another input as exporting, in the corresponding edge band signal then in the end generated, data-signal and pilot signal will respectively account for the power of half, and as when odd numbered slots, the first timeslot multiplex selector is from C '
aD, C
aPmiddle selection C '
aDas output, when even timeslots, the first timeslot multiplex selector is from C '
aD, C
aPmiddle selection C
aPas output; This first default time slot rule can also be: in every m time slot, a spaced pick n time slot (n<m), using an input as output, another inputs as output by other m-n time slot in m time slot, in the corresponding edge band signal then in the end generated, the power ratio exported is respectively n/m, 1-n/m, and as in n time slot of every m time slot, the first timeslot multiplex selector is from C '
aD, C
aPmiddle selection C '
aDas output, time in m-n time slot of every m time slot, the first timeslot multiplex selector is from C '
aD, C
aPmiddle selection C
aPas output, then in the corresponding edge band signal in the end generated, the power ratio of data-signal is n/m, and the power ratio of pilot signal is 1-n/m.
As this second default Slot selection rule is: when odd numbered slots, one is selected to input as exporting, when even timeslots, select another input as exporting, in the corresponding edge band signal then in the end generated, data-signal and pilot signal will respectively account for the power of half, and as when odd numbered slots, the second timeslot multiplex selector is from C '
bD, C
bPmiddle selection C '
bDas output, when even timeslots, the second timeslot multiplex selector is from C '
bD, C
bPmiddle selection C
bPas output; This second default time slot rule can also be: in every m time slot, a spaced pick n time slot (n<m), using an input as output, another inputs as output by other m-n time slot in m time slot, in the corresponding edge band signal then in the end generated, the power ratio exported is respectively n/m, 1-n/m, and as in n time slot of every m time slot, the second timeslot multiplex selector is from C '
bD, C
bPmiddle selection C '
bDas output, time in m-n time slot of every m time slot, the second timeslot multiplex selector is from C '
bD, C
bPmiddle selection C
bPmiddle component is as output, then in the corresponding edge band signal in the end generated, the power ratio of data-signal is n/m, and the power ratio of pilot signal is 1-n/m.
This searches module 16 from according to this C
aand C
bcorresponding in-phase signal and orthogonal signalling are found in the modulation mapping table preset.
In one embodiment, when sub-carrier frequencies is 15.345MHz, the frequency f of baseband complex signal clock CLK0
0for the quadruple rate of subcarrier.This modulation mapping table preset as shown in Table 1.C
at () represents C
a, C
bt () represents upper sideband baseband signal component, S
it () represents in-phase signal, S
qt () represents orthogonal signalling.
As the C of current input
abe the C of 0 and current input
bbe 0, this is searched module 16 and finds corresponding in-phase signal S
it () is respectively 1 ,-1 ,-1,1 in the value in four out of phase moment of a sub-carrier cycle, find orthogonal signalling S
qt () is respectively 0,0,0,0 in the value in four out of phase moment of a sub-carrier cycle.
This in-phase signal and orthogonal signalling are modulated to modulating frequency f by this radio-frequency modulator 17
scentered by frequency on, the formula of modulation is S
i(t) cos (2 π f
st)-S
q(t) sin (2 π f
st), generate with modulating frequency f
scentered by the broadband signal of frequency.
Further, this device also comprises: the 3rd modulation module and the 4th modulation module;
3rd modulation module, for by this C
aPwith a fixing binary sequence C
sAcarry out XOR, obtain lower sideband data channel baseband signal component C '
aP;
4th modulation module, for by this C
bPwith a fixing binary sequence C
sBcarry out XOR, obtain upper sideband data channel baseband signal component C '
bP;
This first multiplexing selector is also for from this C '
aDand C '
aPmiddle selection one is as lower sideband baseband signal component C
a;
This second multiplexing selector, also for from this C '
bDand C '
bPmiddle selection one is as upper sideband baseband signal component C
b.
Binary sequence C
sAwith binary sequence C
sBthe length of each binary digit be the integral multiple of 1ms, and binary sequence C
sAwith binary sequence C
sBthe length of each binary digit and binary sequence C
sAwith binary sequence C
sBrepetition period can be different.
In one embodiment, this first multiplexing selector is also for presetting Slot selection rule from this C ' according to the 3rd
aDand C '
aPmiddle selection one is as lower sideband baseband signal component C
a; This second multiplexing selector is also for presetting Slot selection rule from this C ' according to the 4th
bDand C '
bPmiddle selection one is as upper sideband baseband signal component C
b.
3rd default Slot selection rule and the 4th is preset Slot selection rule and can be pre-set, and the 3rd default Slot selection rule and the 4th is preset Slot selection rule and be may be the same or different.
3rd presets time slot rule is: when odd numbered slots, selects one to input as exporting, when even timeslots, select another input as exporting, then, in the corresponding edge band signal in the end generated, data-signal and pilot signal will respectively account for the power of half, as when odd numbered slots, from C '
aD, C '
aPmiddle selection C '
aDas output, when even timeslots, from C '
aD, C '
aPmiddle selection C '
aPas output; 3rd presets time slot rule can also be: in every m time slot, a spaced pick n time slot (n<m), using an input as output, another inputs as output by other m-n time slot in m time slot, in the corresponding edge band signal then in the end generated, the power ratio exported is respectively n/m, 1-n/m, as in n time slot of every m time slot, from C '
aD, C '
aPmiddle selection C '
aDas output, time in m-n time slot of every m time slot, from C '
aD, C '
aPmiddle selection C '
aPas output, then in the corresponding edge band signal in the end generated, the power ratio of data-signal is n/m, and the power ratio of pilot signal is 1-n/m.
3rd presets Slot selection rule is: when odd numbered slots, one is selected to input as exporting, when even timeslots, select another input as exporting, in the corresponding edge band signal then in the end generated, data-signal and pilot signal will respectively account for the power of half, as when odd numbered slots, from C '
bD, C '
bPmiddle selection C '
bDas output, when even timeslots, from C '
bD, C '
bPmiddle selection C '
bPas output; This second default time slot rule can also be: in every m time slot, a spaced pick n time slot (n<m), using an input as output, another inputs as output by other m-n time slot in m time slot, in the corresponding edge band signal then in the end generated, the power ratio exported is respectively n/m, 1-n/m, as in n time slot of every m time slot, from C '
bD, C '
bPmiddle selection C '
bDas output, time in m-n time slot of every m time slot, from C '
bD, C '
bPmiddle selection C '
bPmiddle component is as output, then in the corresponding edge band signal in the end generated, the power ratio of data-signal is n/m, and the power ratio of pilot signal is 1-n/m.
With reference to the second example structure schematic diagram that Fig. 6, Fig. 6 are signal generating apparatus of the present invention.
Based on the first embodiment of above-mentioned signal generating apparatus, this device also comprises: subcarrier-modulated module 18, for this C
acarry out binary modulated and generate the first modulation result, and to this C
bcarry out binary modulated and generate the second modulation result; And according to lower sideband complex subcarrier, the first modulation result is modulated, and according to upper sideband complex subcarrier, the second modulation result is modulated, generate corresponding in-phase signal and orthogonal signalling.
This subcarrier-modulated module 18 couples of C
aand C
bcarry out binary modulated respectively, in one embodiment, modulation result as shown in above-mentioned table two, S
1t () represents the first modulation result, S
2t () represents the second modulation result.
The first modulation result generated and the second modulation result are also modulated to lower sideband and upper sideband by this subcarrier-modulated module 18 respectively, and modulation formula is as follows: S (t)=S
1(t) e* (t)+S
1t () e (t), e* (t) represent the complex subcarrier of lower sideband, e (t) represents the complex subcarrier of upper sideband, e (t)=SC
cos(t)+jSC
sin(t), e* (t)=SC
cos(t)-jSC
sin(t), SC
cos(t)=sign (cos (2 π f
sCt)), SC
sin(t)=sign (sin (2 π f
sCt)), wherein, SC
cost () represents cosine binary system subcarrier, SC
sint () represents sinusoidal binary system subcarrier; f
sCfor sub-carrier frequencies, f
sC=15.345MHz.As shown in Figure 3, this sinusoidal binary system subcarrier as shown in Figure 4 for this cosine binary system subcarrier.
S (t) is expressed as the form of real part and imaginary part, S (t)=S
i(t)+jS
q(t)=(S
1(t)+S
2(t)) SC
cos(t)+j (S
2(t)-S
1(t)) SC
sin(t).The real part S of S (t)
it () represents in-phase signal, the imaginary part S of S (t)
qt () represents orthogonal signalling.Work as S
1(t)=1/2, S
2during (t)=1/2, this S (t)=SC
cost (), namely orthogonal signalling are 0, check that Fig. 3 can learn, S (t) is respectively 1 ,-1 ,-1,1 in the value in four out of phase moment in a cosine subcarrier cycle.
Further, this device also comprises: mapping table generation module, for by this C all
aand C
bvalue combine, obtain in-phase signal corresponding to each combination and orthogonal signalling by subcarrier-modulated module 18, generate modulation mapping table.
This C
acan value be 0,1, this C
bcan value 0,1, this mapping table generation module is to this C
aand C
bvalue carry out combination in any, four combinations can be obtained, be respectively (0,0), (0,1), (1,0), (1,1), each combination is adopted to the subcarrier-modulated of same way, in-phase signal corresponding to each combination and orthogonal signalling are obtained by subcarrier-modulated module 18, note down in-phase signal corresponding to each combination and orthogonal signalling, generate modulation mapping table.As being 15.345MHz in sub-carrier frequencies, the f of baseband complex signal clock CLK0
0for the quadruple rate of subcarrier, when pseudo-code drives the frequency of clock CLK1 to be 10.23MHz, the modulation mapping table of generation as shown in Table 1.
According to the combination of different code frequencies and sub-carrier frequencies, the frequency f of baseband complex signal
0code frequency f can be chosen as
cwith four times of sub-carrier frequencies f
sCleast common multiple, as in the present embodiment, code frequency is 10.23MHz, sub-carrier frequencies is 15.345MHz, then the frequency of baseband complex signal can be chosen as 61.38MHz.Engineering construction personnel can according to sub-carrier frequencies f
sCto baseband complex signal f
0different frequency dividing ratios, voluntarily according to formula construction look-up table, as structure table one.
These are only the preferred embodiments of the present invention; not thereby the scope of the claims of the present invention is limited; every utilize specification of the present invention and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (11)
1. a signal creating method, is characterized in that, the method comprises:
S10, generate baseband complex signal clock, and frequency division is carried out to described baseband complex signal clock obtain pseudo-code and drive clock;
S11, drive clock to drive according to described pseudo-code to produce lower sideband numeric data code C
aD, lower sideband pilot code C
aP, upper sideband numeric data code C
bDwith upper sideband pilot code C
bP;
S12, according to lower sideband data d
amodulation C
aDobtain lower sideband data channel baseband signal component C '
aD, and according to upper sideband data d
bmodulation upper sideband numeric data code C
bDobtain upper sideband data channel baseband signal component C '
bD;
S13, from described C '
aDand C
aPmiddle selection one is as lower sideband baseband signal component C
a, and from described C '
bDand C
bPmiddle selection one is as upper sideband baseband signal component C
b;
S14, according to described C
aand C
bcorresponding in-phase signal and orthogonal signalling are found in the modulation mapping table preset;
S15, described in-phase signal and orthogonal signalling to be modulated in the frequency centered by modulating frequency, to generate the broadband signal of frequency centered by modulating frequency.
2. signal creating method as claimed in claim 1, it is characterized in that, described S13 comprises:
S131, by described C
aPwith a fixing binary sequence C
sAcarry out XOR, obtain lower sideband data channel baseband signal component C '
aP; And by described C
bPwith a fixing binary sequence C
sBcarry out XOR, obtain upper sideband data channel baseband signal component C '
bP;
S132, from described C '
aDand C '
aPmiddle selection one is as lower sideband baseband signal component C
a, and from described C '
bDand C '
bPmiddle selection one is as upper sideband baseband signal component C
b.
3. signal creating method as claimed in claim 1, it is characterized in that, described step S13 comprises:
S133, according to first preset Slot selection rule from described C '
aDand C
aPmiddle selection one is as C
a; And preset Slot selection rule from described C ' according to second
bDand C
bPmiddle selection one is as C
b.
4. the signal creating method as described in any one of claims 1 to 3, is characterized in that, after described step S13, the method also comprises:
S16, to described C
acarry out binary modulated and generate the first modulation result, and to described C
bcarry out binary modulated and generate the second modulation result;
S17, according to lower sideband complex subcarrier, the first modulation result to be modulated, and according to upper sideband complex subcarrier, the second modulation result is modulated, generate corresponding in-phase signal and orthogonal signalling;
S18, described in-phase signal and orthogonal signalling to be modulated in the frequency centered by modulating frequency, to generate the broadband signal of frequency centered by modulating frequency.
5. signal creating method as claimed in claim 4, it is characterized in that, described method also comprises:
S19, by all described C
aand C
bvalue combine, according to the formula of subcarrier-modulated, step S16 ~ step S17 is performed to each combination, obtains in-phase signal corresponding to each combination and orthogonal signalling, generate modulation mapping table.
6. the signal creating method as described in claim 1,2,3 or 5, is characterized in that, described step S12 comprises:
S121, by described d
awith C
aDcarry out XOR, obtain C '
aD; And by described d
bwith C
bDcarry out XOR, obtain C '
bD.
7. a signal generating apparatus, is characterized in that, this device comprises:
Clock generator, for generating baseband complex signal clock;
Frequency divider, obtains pseudo-code driving clock for carrying out frequency division to described baseband complex signal clock;
Pseudo-code generator, produces lower sideband numeric data code C for driving clock to drive according to described pseudo-code
aD, lower sideband pilot code C
aP, upper sideband numeric data code C
bDwith upper sideband pilot code C
bP;
First modulation module, for according to lower sideband data d
amodulation C
aDobtain lower sideband data channel baseband signal component C '
aD;
Second modulation module, for according to upper sideband data d
bmodulation C
bDobtain upper sideband data channel baseband signal component C '
bD;
First multiplexing selector, for from described C '
aDand C
aPmiddle selection one is as lower sideband baseband signal component C
a;
Second multiplexing selector, for from described C '
bDand C
bPmiddle selection one is as upper sideband baseband signal component C
b;
Search module, for according to described C
aand C
bcorresponding in-phase signal and orthogonal signalling are found in the modulation mapping table preset;
Radio-frequency modulator, for being modulated to described in-phase signal and orthogonal signalling with modulating frequency f
scentered by frequency on, generate the broadband signal of frequency centered by modulating frequency.
8. signal generating apparatus as claimed in claim 7, it is characterized in that, described device also comprises the 3rd modulation module and the 4th modulation module;
Described 3rd modulation module, for by described C
aPwith a fixing binary sequence C
sAcarry out XOR, obtain lower sideband data channel baseband signal component C '
aP;
Described 4th modulation module, for by described C
bPwith a fixing binary sequence C
sBcarry out XOR, obtain upper sideband data channel baseband signal component C '
bP;
Described first multiplexing selector is also for from described C '
aDand C '
aPmiddle selection one is as lower sideband baseband signal component C
a;
Described second multiplexing selector, also for from described C '
bDand C '
bPmiddle selection one is as upper sideband baseband signal component C
b.
9. signal generating apparatus as claimed in claim 7, it is characterized in that, described first multiplexing selector comprises the first timeslot multiplex selector, for presetting Slot selection rule from described C ' according to first
aDand C
aPmiddle selection one is as C
a;
Second multiplexing selector comprises the second timeslot multiplex selector, for presetting Slot selection rule from described C ' according to second
bDand C
bPmiddle selection one is as C
b.
10. the signal generating apparatus as described in any one of claim 7 to 9, is characterized in that, described device also comprises:
Subcarrier-modulated module, for described C
acarry out binary modulated and generate the first modulation result, and to described C
bcarry out binary modulated and generate the second modulation result; And according to lower sideband complex subcarrier, the first modulation result is modulated, and according to upper sideband complex subcarrier, the second modulation result is modulated, generate corresponding in-phase signal and orthogonal signalling.
11. signal generating apparatus as described in any one of claim 7 to 9, it is characterized in that, described first modulation module comprises the first XOR device, for by described d
awith C
aDcarry out XOR, obtain C '
aD;
Described second modulation module comprises the second XOR device, for by described d
bwith C
bDcarry out XOR, obtain C '
bD.
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|---|---|---|---|---|
| CN107037448A (en) * | 2016-02-03 | 2017-08-11 | 清华大学 | The generation method and device, method of reseptance and device of double frequency perseverance envelope navigation signal |
| CN111585928A (en) * | 2020-04-28 | 2020-08-25 | 中国电子科技集团公司第三研究所 | Voice signal single-sideband modulation and demodulation method and device |
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| CN102209056A (en) * | 2011-04-15 | 2011-10-05 | 华中科技大学 | Navigation signal modulation method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107037448A (en) * | 2016-02-03 | 2017-08-11 | 清华大学 | The generation method and device, method of reseptance and device of double frequency perseverance envelope navigation signal |
| CN107037448B (en) * | 2016-02-03 | 2019-10-15 | 清华大学 | The generation method and device, method of reseptance and device of double frequency perseverance envelope navigation signal |
| CN111585928A (en) * | 2020-04-28 | 2020-08-25 | 中国电子科技集团公司第三研究所 | Voice signal single-sideband modulation and demodulation method and device |
| CN111585928B (en) * | 2020-04-28 | 2023-05-05 | 中国电子科技集团公司第三研究所 | Single sideband modulation and demodulation method and device for voice signal |
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