CN105049145B - frame head fast synchronization system and method - Google Patents
frame head fast synchronization system and method Download PDFInfo
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Abstract
Frame head Fast synchronization system and method, belongs to satellite data transmission data receiver processing technology field.The present invention is that the synchronous method of existing frame head can not meet the problem of data processing speed is required in order to solve with the raising for passing numeric data code rate level is defended.Present system and method can realize data high-speed communication processing with it is synchronous, the data received from base equipment are gone here and there and converted, and handled data using N bit bit wides as internal data bit wide, so as to realize under a clock while processing N bit data, meet and defend the data processing speed requirement for passing data.The present invention is used for the frame head Fast synchronization of satellite data transmission data.
Description
Technical field
The present invention relates to frame head Fast synchronization system and method, belong to satellite data transmission data receiver processing technology field.
Background technology
In the communications field, frame head is synchronously the mostly important ring of Data processing, and it is the basis of follow-up data processing.
The form of current satellite data transmission data follows the AOS data format standards of CCSDS formulations mostly, the standard require data down transmission with
Data frame is unit, and data frame is originated using the data frame head arranged as mark, and data descend into earth station in the form of streaming.Therefore
Frame head is synchronously the first element of satellite data transmission data receiver processing, at present, as data bit rate is from traditional Mbps ranks
Rise to Gbps ranks, the time for leaving frame head synchronization for is shorter and shorter, the existing method synchronous to frame head can not meet data
The rate request of processing.
The content of the invention
The invention aims to solve with defending the raising for passing numeric data code rate level, the synchronous method of existing frame head without
Method meets the problem of data processing speed is required, and there is provided a kind of frame head Fast synchronization system and method.
Frame head Fast synchronization system of the present invention, including：
For caching not synchronization N bit parallel frame datas, and the output N bit parallel frame datas under the control of control module
Input buffer module；N values are 8 integral multiple, and scope is from 32 to 512；
For will be received in the N bit parallel frame datas of input buffer module and be received in the N of presynchronization cache module
The data cached input selecting module that selection output is carried out under the control of control module of bit presynchronization；L values are 8 integer
Times, scope is from 8 to 64；L is less than N；
Level cache module for the N bit data for inputting selecting module selection output to be carried out to level cache；
For the L2 cache module for the N bit data for receiving the output of level cache module；
For receiving the N bit data of level cache module output and the N bit data of L2 cache module output, and press
Position is spliced into the data combination module of 2N bit data；
It is respectively used to receive the 2N bit data of data combination module output, and the 2N bit data of reception is subjected to L
N number of L interception concatenation modules of bit data cutouts；N number of L interception concatenation module is terminated by first to n-th, adjacent L
Original position difference 1bit of the data of position interception concatenation module interception in 2N bit data；
The L bit data of L interception concatenation module output are received for correspondence, by the L bit data according to control module
Frame head compare N number of comparison control module for being pre-processed of mask information；It is each compare control module by L bit data not
The bit being compared carries out step-by-step and 0 operation, obtains pretreated L bit data；
Carried out for correspondence by pretreated L bit data and by the standard frame head set in advance that control module is inputted
The N number of frame head comparing module compared；Pretreated L bit data and standard frame head are carried out XOR ratio by the frame head comparing module
To operation, if the result obtained is 0, the pretreated L bit data are target frame head, export comparison result 1；Otherwise it is defeated
Go out comparison result 0；
Comparison result step-by-step for N number of frame head comparing module to be exported is spliced, and the frame head for forming N bit data compares knot
Fruit module；
For judging the N bit data that frame head comparison result module is exported, according to 1 in the N bit data, really
Surely frame head mark is retrieved, and sends the control module of frame header note signal, synchronization caching control signal and lock flag signal；
2N bit data for receiving data combination module output, and according to the dynamic depth of dynamic depth control module
Control information carries out the dynamic depth cache module of data buffer storage；
Dynamic depth control module for producing dynamic depth control information；
It is respectively used to receive the 2N bit data of dynamic depth cache module output, and N is carried out to the 2N bit data
N number of N interception modules of bit data cutouts；N number of N interception module is terminated by first to n-th, adjacent N interception
Original position difference 1bit of the data of module intercepts in 2N bit data；
Believe for receiving the N bit data that N number of N interception module interception is obtained, and being marked according to the frame head of control module
The data selecting module that the N bit data of number selection corresponding N interception module interception acquisition are exported；
Delay for the presynchronization that the synchronization caching control signal according to control module is controlled to presynchronization cache module
Deposit control module；
The N bit data corresponding to frame head marking signal for receiving data selecting module output, and according to presynchronization
The synchronization caching control signal of buffer control module, the N bit data of reception are exported or pre- as N bit as synchrodata
The presynchronization cache module of synchronization caching data output.
Control module determines that the detailed process for retrieving frame head is：Judge the N bit numbers of frame head comparison result module output
Whether there is frame head in, if occurring one 1 in the N bit data of the frame head comparison result module output in once comparing,
It is defined as frame head mark；If occurring multiple 1 in the N bit data of the frame head comparison result module output in once comparing,
The 1 of lowest order is chosen, is defined as frame head mark.
Frame head fast synchronization method, including：
For caching not synchronization N bit parallel frame datas, and defeated under the control of control module by input buffer module
The step of going out N bit parallel frame datas；N values are 8 integral multiple, and scope is from 32 to 512；
For will be received in the N bit parallel frame datas of input buffer module by inputting selecting module and be received in pre- same
The N bit presynchronization of step cache module is data cached to carry out the step of selection is exported under the control of control module；L values are 8
Integral multiple, scope is from 8 to 64；L is less than N；
Step for the N bit data for inputting selecting module selection output to be carried out to level cache by level cache module
Suddenly；
The step of for receiving the N bit data that level cache module is exported by L2 cache module；
For receiving N bit data and the output of L2 cache module that level cache module is exported by data combination module
N bit data, and step-by-step is the step of be spliced into 2N bit data；
For receiving the 2N bit data that data combination module is exported respectively by N number of L interception concatenation module, and it will connect
The step of 2N bit data of receipts carry out L bit data cutouts；N number of L interception concatenation module is whole to n-th by first
Only, original position difference 1bit of the data of adjacent L interception concatenation module interception in 2N bit data；
For receiving the L bit data that L interception concatenation modules are exported by N number of comparison control module correspondence, by the L
Bit data compare the step of mask information is pre-processed according to the frame head of control module；Each control module that compares is by L bit
Step-by-step and 0 operation are carried out without the bit of comparison in data, pretreated L bit data are obtained；
For by N number of frame head comparing module correspondence by pretreated L bit data with by control module input it is pre-
The step of standard frame head first set is compared；The frame head comparing module is by pretreated L bit data and standard frame head
Carry out XOR and compare operation, if the result obtained is 0, the pretreated L bit data are target frame head, and output compares knot
Really 1；Otherwise comparison result 0 is exported；
Comparison result step-by-step for being exported N number of frame head comparing module by frame head comparison result module is spliced, and forms N
The step of bit data；
For being judged by control module the N bit data that frame head comparison result module is exported, according to the N bit
1 in data, it is determined that retrieving frame head mark, and send frame header note signal, synchronization caching control signal and lock flag letter
Number the step of；
For receiving the 2N bit data that data combination module is exported by dynamic depth cache module, and according to dynamic depth
The step of dynamic depth control information for spending control module carries out data buffer storage；
The step of for producing dynamic depth control information by dynamic depth control module；
For receiving the 2N bit data that dynamic depth cache module is exported respectively by N number of N interception module, and to this
The step of 2N bit data carry out N bit data cutouts；N number of N interception module is terminated by first to n-th, adjacent N
Original position difference 1bit of the data of position interception module interception in 2N bit data；
The N bit data obtained are intercepted for receiving N number of N interception module by data selecting module, and according to control
The step of N bit data that the corresponding N interception module interception of frame head mark signal behavior of module is obtained are exported；
For being cached by presynchronization buffer control module according to the synchronization caching control signal of control module to presynchronization
The step of module is controlled；
For receiving the N bit corresponding to frame head marking signal that data selecting module is exported by presynchronization cache module
Data, and according to the synchronization caching control signal of presynchronization buffer control module, it regard the N bit data of reception as synchrodata
The step of output or output data cached as N bit presynchronization.
Control module determines that the detailed process for retrieving frame head is：Judge the N bit numbers of frame head comparison result module output
Whether there is frame head in, if occurring one 1 in the N bit data of the frame head comparison result module output in once comparing,
It is defined as frame head mark；If occurring multiple 1 in the N bit data of the frame head comparison result module output in once comparing,
The 1 of lowest order is chosen, is defined as frame head mark.
Advantages of the present invention：The present invention can realize data high-speed communication processing with it is synchronous, to being received from base equipment
To data gone here and there and converted, and data are handled using N bit bit wides as internal data bit wide, so as to realize one
N bit data are handled under individual clock simultaneously, meets and defends the data processing speed requirement for passing data.
Brief description of the drawings
Fig. 1 is the FB(flow block) of frame head Fast synchronization system of the present invention；
Fig. 2 is the flow chart of control module of the present invention.
Embodiment
Embodiment one：Illustrate present embodiment with reference to Fig. 1 and Fig. 2, frame head described in present embodiment is quick
Synchronization system, including：
For caching not synchronization N bit parallel frame datas, and the output parallel frame numbers of N bit under the control of control module 10
According to input buffer module 1；N values are 8 integral multiple, and scope is from 32 to 512；
For will be received in the N bit parallel frame datas of input buffer module 1 and be received in the N of presynchronization cache module 16
The data cached input selecting module 2 that selection output is carried out under the control of control module 10 of bit presynchronization；L values for 8 it is whole
Several times, scope is from 8 to 64；L is less than N；
The N bit data of output are selected to carry out the level cache module 3 of level cache for selecting module 2 will to be inputted；
For the L2 cache module 4 for the N bit data for receiving the output of level cache module 3；
For receiving the N bit data that the N bit data and L2 cache module 4 of the output of level cache module 3 are exported, and
Step-by-step is spliced into the data combination module 5 of 2N bit data；
It is respectively used to receive the 2N bit data that data combination module 5 is exported, and the 2N bit data of reception is subjected to L
N number of L interception concatenation modules 6 of bit data cutouts；N number of L interception concatenation module 6 is terminated by first to n-th, phase
Original position difference 1bit of the data that adjacent L interception concatenation module 6 is intercepted in 2N bit data；
The L bit data that L interception concatenation modules 6 are exported are received for correspondence, by the L bit data according to control module
10 frame head compares N number of comparison control module 7 that mask information is pre-processed；Each control module 7 that compares is by L bit numbers
Step-by-step and 0 operation are carried out without the bit of comparison in, pretreated L bit data are obtained；
Standard frame head set in advance for corresponding to by pretreated L bit data with being inputted by control module 10 enters
N number of frame head comparing module 8 that row is compared；The frame head comparing module 8 carries out pretreated L bit data and standard frame head different
Or operation is compared, if the result obtained is 0, the pretreated L bit data are target frame head, export comparison result 1；It is no
Then export comparison result 0；
Comparison result step-by-step for N number of frame head comparing module 8 to be exported is spliced, and the frame head for forming N bit data is compared
Object module 9；
For judging the N bit data that frame head comparison result module 9 is exported, according to 1 in the N bit data,
It is determined that retrieving frame head mark, and send the control mould of frame header note signal, synchronization caching control signal and lock flag signal
Block 10；
2N bit data for receiving the output of data combination module 5, and according to the dynamic of dynamic depth control module 12
Deep-controlled information carries out the dynamic depth cache module 11 of data buffer storage；
Dynamic depth control module 12 for producing dynamic depth control information；
It is respectively used to receive the 2N bit data of the output of dynamic depth cache module 11, and N is carried out to the 2N bit data
N number of N interception modules 13 of bit data cutouts；N number of N interception module 13 is terminated by first to n-th, adjacent N
Original position difference 1bit of the data that interception module 13 is intercepted in 2N bit data；
For receiving the N bit data that N number of interception of N interception module 13 is obtained, and according to the frame header of control module 10
The data selecting module 14 that the N bit data that the corresponding interception of N interception module 13 of note signal behavior is obtained are exported；
For the synchronization caching control signal according to control module 10 presynchronization cache module 16 is controlled it is pre- same
Walk buffer control module 15；
The N bit data corresponding to frame head marking signal for receiving the output of data selecting module 14, and according to pre- same
The synchronization caching control signal of buffer control module 15 is walked, the N bit data of reception are exported or be used as N as synchrodata
The presynchronization cache module 16 of the data cached output of bit presynchronization.
Embodiment two：Present embodiment is described further to embodiment one, and control module 10 determines retrieval
Detailed process to frame head is：Judge whether there is frame head in the N bit data that frame head comparison result module 9 is exported, if once
Occurs one 1 in the N bit data that frame head comparison result module 9 in comparison is exported, it is determined that for frame head mark；If once
Occur multiple 1 in the N bit data that frame head comparison result module 9 in comparison is exported, then choose the 1 of lowest order, be defined as frame
Labeling head.
Embodiment three：Illustrate present embodiment with reference to Fig. 1 and Fig. 2, frame head described in present embodiment is quick
Synchronous method, including：
For caching not synchronization N bit parallel frame datas, and under the control of control module 10 by input buffer module 1
The step of exporting N bit parallel frame datas；N values are 8 integral multiple, and scope is from 32 to 512；
For by input selecting module 2 will be received in the N bit parallel frame datas of input buffer module 1 and be received in it is pre-
The N bit presynchronization of synchronization caching module 16 is data cached to carry out the step of selection is exported under the control of control module 10；L takes
It is worth the integral multiple for 8, scope is from 8 to 64；L is less than N；
The N bit data of output are selected to carry out level cache for by level cache module 3 selecting module 2 will to be inputted
Step；
The step of for receiving the N bit data that level cache module 3 is exported by L2 cache module 4；
N bit data and L2 cache module 4 for receiving the output of level cache module 3 by data combination module 5
The N bit data of output, and step-by-step is the step of be spliced into 2N bit data；
For receiving the 2N bit data that data combination module 5 is exported respectively by N number of L interception concatenation module 6, and will
The step of 2N bit data of reception carry out L bit data cutouts；N number of L interception concatenation module 6 is by first to n-th
Terminate, original position difference 1bit of the data that adjacent L interception concatenation module 6 is intercepted in 2N bit data；
For receiving the L bit data that L interception concatenation modules 6 are exported by N number of comparison control module 7 correspondence, by the L
Bit data compare the step of mask information is pre-processed according to the frame head of control module 10；Each control module 7 that compares is by L
Step-by-step and 0 operation are carried out without the bit of comparison in bit data, pretreated L bit data are obtained；
For being inputted by N number of frame head comparing module 8 correspondence by pretreated L bit data and by control module 10
The step of standard frame head set in advance is compared；The frame head comparing module 8 is by pretreated L bit data and standard frame
Head carries out XOR and compares operation, if the result obtained is 0, and the pretreated L bit data are target frame head, and output is compared
As a result 1；Otherwise comparison result 0 is exported；
Comparison result step-by-step for being exported N number of frame head comparing module 8 by frame head comparison result module 9 is spliced, shape
The step of into N bit data；
N bit data for being exported by control module 10 to frame head comparison result module 9 judge, according to the N
1 in bit data, it is determined that retrieving frame head mark, and send frame header note signal, synchronization caching control signal and lock flag
The step of signal；
For receiving the 2N bit data that data combination module 5 is exported by dynamic depth cache module 11, and according to dynamic
The step of dynamic depth control information of state depth control block 12 carries out data buffer storage；
The step of for producing dynamic depth control information by dynamic depth control module 12；
2N bit data for receiving the output of dynamic depth cache module 11 respectively by N number of N interception module 13, and
The step of N bit data cutouts are carried out to the 2N bit data；N number of N interception module 13 is whole to n-th by first
Only, original position difference 1bit of the data that adjacent N interception module 13 is intercepted in 2N bit data；
N bit data for receiving the N number of interception of N interception module 13 acquisition by data selecting module 14, and according to
What the N bit data that the corresponding interception of N interception module 13 of frame head mark signal behavior of control module 10 is obtained were exported
Step；
For by presynchronization buffer control module 15 according to the synchronization caching control signal of control module 10 to presynchronization
The step of cache module 16 is controlled；
For receiving the N corresponding to frame head marking signal that data selecting module 14 is exported by presynchronization cache module 16
Bit data, and according to the synchronization caching control signal of presynchronization buffer control module 15, using the N bit data of reception as same
The step of step data output or output data cached as N bit presynchronization.
Embodiment four：Present embodiment is described further to embodiment three, and control module 10 determines retrieval
Detailed process to frame head is：Judge whether there is frame head in the N bit data that frame head comparison result module 9 is exported, if once
Occurs one 1 in the N bit data that frame head comparison result module 9 in comparison is exported, it is determined that for frame head mark；If once
Occur multiple 1 in the N bit data that frame head comparison result module 9 in comparison is exported, then choose the 1 of lowest order, be defined as frame
Labeling head.
In the present invention, for high speed frame data, frame head is the starting of mark one frame signal, and the detection of frame head is follow-up data
The basis of Treatment Analysis.General, data are transmitted or received in the form of bit flows, and frame head is by a string of independent specific data
Composition, its length is generally 32bit or 24bit, or other length values arranged in advance.In actual application demand, frame head
Content typically arranged in advance by communicating pair, in the detection, it is desirable to which frame head sychronisation only can enter to certain bits in frame head
Row is compared as synchronous basis for estimation.It is specifically expressed as follows shown in table 1：
The frame head form of table 1 is illustrated
| bit0 | bit1 | 2 | bit3 | 4 | bit5 | --------------------- | bit30 | bit31 |
In upper table, 2,4 in the 3rd row and the 5th row represent mask bit, and other row are synchronous criterion position.
The input/output signal of synchronization system：The input of frame head synchronization system is not synchronous frame data stream, to improve number
According to processing speed, on the basis of admissible peak frequency inside FPGA, using N bit high-bit width data, make system each
Clock can handle N bit frame data streams.Maximum accessible frame head length is L bit in the system, and L can be set.Frame head is same
It is the data streaming file after frame head locking signal and synchronization to walk system output signal, and is exported with N bit parallel modes, and correctly
Frame head starting bit will be used as the starting bit of first output data.
Groundwork flow：When not synchronous N bit parallel frame data streams are input in system, input is initially entered slow
Storing module 1 is cached；Selecting module 2 is inputted when that data will be sent to after the data for having caching in input buffer module 1,
Input selecting module 2 to receive from the data of presynchronization cache module 16 simultaneously, and selected under the control of control module 10
Export the data received；Input selecting module 2 outputs data to level cache module 3 and once cached, in next clock,
The data that level cache module 3 is cached enter L2 cache module 4, while being stored in new data in level cache module 3；Every
Data in level cache module 3 and L2 cache module 4 are all combined by individual clock, data combination module 5, form 2N
Bit bit wide data.2N bit bit wides data in data combination module 5 will be respectively fed to N number of L interception concatenation module 6 and dynamic
State depth buffer module 11；N number of L interception concatenation module 6 will intercept L bit data from the 2N bit data of input respectively,
Original position difference 1bit of the data that adjacent L interception concatenation module 6 is intercepted in the 2N bit of input.Then L interceptions
The L bit data of interception are respectively fed in corresponding comparison control module 7 by concatenation module 6；Control module 7 is compared by basis
The frame head that control module 10 is inputted compares mask information and the L bit data of interception is pre-processed, and need not be compared
Bit carry out step-by-step with 0 operation.Then pretreated L bit data are sent in frame head comparing module 8 and compared
It is right.In frame head comparing module 8, the standard frame set in advance that the L bit input datas of input will be inputted with control module 10
Head is compared, and output signal 1 is into frame head comparison result module 9 if it there is frame head in the data of input, and otherwise output is believed
Number 0 into frame head comparison result module 9.Frame head comparison result module 9 will be combined all input comparison results, be formed
N bit data are simultaneously sent to control module 10.The data that control module 10 is inputted according to frame head comparison result module 9 are sentenced
It is disconnected, represent to have retrieved frame head if containing 1, while lock flag signal is exported, and output frame labeling head to data are selected
Module 14, carries out path selection.Data selecting module 14 will carry out the data after synchronization to be output to presynchronization cache module 16,
Presynchronization cache module 16 carries out output selection under the control of presynchronization buffer control module 15, determines output data as most
Output data or the input as input selecting module 2 carry out re-synchronization operation after whole synchronization.In 2N bit data from number
It is input to according to composite module 5 after dynamic depth cache module 11, dynamic depth cache module 11 will carry out data buffer storage, it is cached
Depth is controlled by dynamic depth control module 12.The 2N that dynamic depth cache module 11 is exported after the caching of certain depth is completed
Bit data will be fed into N number of N interception module 13, and N interception modules 13 will intercept N bit data, it is believed that latter N are cut
The N bit data that modulus block 13 is intercepted will offset 1bit than the data that previous N interception module 13 is intercepted.N number of N interception
Data after interception are sent to data selecting module 14 by module 13.Data selecting module 14 will be inputted according to from control module 10
Frame head marking signal carry out data that the corresponding N interception module 13 of selection input as output, be output to presynchronization and cache
Module 16.By the way that in the indoor design state machine of control module 10, work(is determined to complete multiframe Locked Confirmation function and multiframe losing lock
Energy.By in the indoor design state machine of dynamic depth control module 12, confirming to be provided with to dynamic depth according to locking losing lock
The control of cache module 11, input selecting module 2 and presynchronization buffer control module 15.
The realization of each functions of modules：
Input buffer module 1：Not synchronous frame data stream to input is cached, it is ensured that carrying out data handling procedure
In, will not occur input data caused by not handling in time and lose.The data bit width of input is N bit, in control module 10
Control under output data to input selecting module 2, a width of N bit of outputs data bits.
Input selecting module 2：The selection output to input data is completed under the control of control module 10, is inputted as N
Bit, output data is N bit.
Level cache module 3：Complete to 1 grade of input data caching, input as N bit, be output as N bit.
L2 cache module 4：Complete the level 2 cache memory to input.
Data combination module 5：2 N bit data to input carry out step-by-step splicing, are spliced into 1 2N bit data.
L interception concatenation modules 6：L splicing interceptions are carried out to the 2N bit of input, so as to realize the 2N bit from input
Extracting data goes out L bit data, and extracting rule is：1st L interception concatenation modules 6 are from the of the 2N bit data of input
0bit starts, and continuous L bit data are extracted, and is used as the 1st L outputs for intercepting concatenation module 6.2nd L are cut
Take concatenation module 6 since the 2bit of the 2N bit data of input, continuous L bit data are extracted, the 2nd is used as
The output of L interception concatenation modules 6.By that analogy, until the interception concatenation modules 6 of n-th L are from the 2N bit data of input
Nbit starts, and continuous L bit data are extracted, and is used as the output of L interception concatenation modules 6 of n-th.It is final to realize
L interception splicings, the output result of each L interception concatenation module 6 will be output in corresponding comparison control module 7.
Compare control module 7：Realize and masking operation is carried out to N number of L bit data of input, according to the control of control module 10
The L bit data of each input are carried out step-by-step and 0 operation, make the bit that need not be compared into 0 by information processed, its
His bit invariant position.Its result is sent to the comparison operation that frame head is carried out in frame head comparing module 8.
Frame head comparing module 8：The module realizes the comparison of frame head, and whether the L bit data for identifying input are to be compared
Target frame head.Its alignments is to use the frame originating point information data of the L bit data of input and standard carrying out xor operation,
Obtained result represents that the L bit data of this input are desired target frame head when being all 0, while output 1 is compared to frame head
In object module 9.
Frame head comparison result module 9：The module realizes that the object information for comparing all frame heads is counted, will be all
Frame head comparison result step-by-step be spliced into Nbit data outputs into control module 10.
Control module 10：The module mainly completes the control and scheduling to total system, realize to input buffer module 1,
Input selecting module 2, compare control module 7, frame head comparing module 8, data selecting module 14 and presynchronization buffer control module
15 control.The workflow of control module 15 is as shown in Figure 2：In program after electricity, initialized first, by configuration information
It is written in modules, such as frame head compares mask bit information and is written in comparison control module 7, input selecting module 2 is set
The data in selection input buffer module 1 are set to, the standard frame head letter that standard is set to input will be compared in frame head comparing module 8
Breath etc..
Subsequently into whether having frame head judgement, indicated whether in the output result for judging frame head comparison result module 9 containing
Frame head, continues in judgement if entering without if, and comparison result is handled if containing frame head：Frame head label information is input to
Data selecting module 14 carries out data selection, if occurring multiple frame head comparing modules 8 in once comparing indicates that frame head ratio is aligned
Really, then the comparison result of lowest order is only chosen, ignores other comparison results.And control presynchronization buffer control module 15 to enter line number
According to caching, it will carry out being buffered in presynchronization cache module 16 from the data at the frame head sync bit.Complete the laggard company of processing
Whether continuous locking frame head correctly judges.
Continuously locking frame head whether correctly judge in, will determine that data jump frame length byte after, relevant position whether be
Target frame head, if correct frame head number is then added 1 by target frame head；Whether have frame head judgement, while input is selected if otherwise entering
The output of module 2 sets the output data with presynchronization cache module 16, abandons the first data, and the first data of the discarding are to miss
The frame head sentenced.Control 1 grade of caching of presynchronization buffer control module 15 to count simultaneously and carry out reducing.Controlled until presynchronization is cached
1 grade of caching counting of molding block 15 is reduced to 0, and the input selection for inputting selecting module 2 is switched into input buffer module 1.
After whether the continuous locking frame head of completion correctly judges, correct frame head number interpretation is carried out, if lock of its value more than setting
Determine threshold value and then enter locking working condition, enter whether continuous locking frame head correctly judges if lock threshold is less than.
In lock-out state work, the locking signal of presynchronization buffer control module 15 will be given, and it is simultaneously that locking signal is defeated
Go out to outside frame synchronization system.Presynchronization buffer control module 15 will control presynchronization cache module 16 to export the number after synchronization simultaneously
According to outside synchronization system.
Judge whether that frame head occur compares incorrect phenomenon simultaneously in the locked state, if continuous frame head is compared correctly,
Then go successively to lock-out state；By losing lock, count is incremented if continuous frame head is incorrect；
If losing lock, which is counted, is less than losing lock threshold value, proceed to judge, if more than losing lock threshold value, into out-of-lock condition, entering
Whether have frame head judgement, and re-start frame head retrieval if entering.
Dynamic depth cache module 11：The module carries out the number of respective depth to data under the control of control module 10
According to caching, the data bit width of input is 2N bit.
Dynamic depth control module 12：Clock number shared by frame length according to setting is cached mould by the module to dynamic depth
The caching depth of block 11 is controlled, it is ensured that when retrieving correct frame head, be output to the data of data selecting module 14 with
Corresponding frame head data is synchronous.
N interception modules 13：The continuous N of 2N bit extracting datas that the module is exported from dynamic depth buffer module 11
Bit data, common N number of N interception module 13 works simultaneously, and the 1bit data of the 1st module are dynamic depth cache module 11
Lowest order in the 2N bit of output, the lowest order of adjacent N positions interception module 13 is incremented by successively, and difference is 1.The module it is defeated
Go out data transfer to data selecting module 14.
Data selecting module 14：The module will carry out data selection according to the frame head label information of input, and selected marker is 1
The data of corresponding N interception modules 13 be used as its output result.
Presynchronization cache module 16：The module carries out data buffer storage under the control of presynchronization buffer control module 15.Its
Output is same under the control of presynchronization buffer control module 15, outputs data to outside input selecting module 2 or synchronization system
Portion.
Presynchronization buffer control module 15：The synchronization caching control of the module complete paired data under the control of control module 10
System, it is ensured that data will reach fixed synchronous frame data before frame lock threshold value and not lose, and ensure be synchronized the frame of mistake
After head, remaining data can be subjected to again frame head again and compared, it is ensured that data are not lost.
Claims (4)
1. a kind of frame head Fast synchronization system, it is characterised in that including：
For caching not synchronization N bit parallel frame datas, and the output N bit parallel frame datas under the control of control module (10)
Input buffer module (1)；N values are 8 integral multiple, and scope is from 32 to 512；
For will be received in the N bit parallel frame datas of input buffer module (1) and be received in the N of presynchronization cache module (16)
The data cached input selecting module (2) that selection output is carried out under the control of control module (10) of bit presynchronization；L values are 8
Integral multiple, scope is from 8 to 64；L is less than N；
The level cache module (3) of level cache is carried out for the N bit data of selecting module (2) selection output will to be inputted；
For the L2 cache module (4) for the N bit data for receiving level cache module (3) output；
For receiving the N bit data of level cache module (3) output and the N bit data of L2 cache module (4) output, and
Step-by-step is spliced into the data combination module (5) of 2N bit data；
It is respectively used to receive the 2N bit data of data combination module (5) output, and the 2N bit data of reception is subjected to L bit
N number of L interception concatenation modules (6) of data cutout；N number of L interception concatenation module (6) terminates by first to n-th, phase
Original position difference 2bit of the data of adjacent L interception concatenation module (6) interception in 2N bit data；
The L bit data of L interception concatenation module (6) output are received for correspondence, by the L bit data according to control module
(10) frame head compares N number of comparison control module (7) that mask information is pre-processed；Each control module (7) that compares is by L
Step-by-step and 0 operation are carried out without the bit of comparison in bit data, pretreated L bit data are obtained；
For correspondence by pretreated L bit data with being carried out by the standard frame head set in advance of control module (10) input
The N number of frame head comparing module (8) compared；The frame head comparing module (8) carries out pretreated L bit data and standard frame head
XOR compares operation, if the result obtained is 0, and the pretreated L bit data are target frame head, export comparison result 1；
Otherwise comparison result 0 is exported；
Comparison result step-by-step for N number of frame head comparing module (8) to be exported is spliced, and the frame head for forming N bit data compares knot
Fruit module (9)；
For judging the N bit data that frame head comparison result module (9) is exported, according to 1 in the N bit data, really
Surely frame head mark is retrieved, and sends the control module of frame header note signal, synchronization caching control signal and lock flag signal
(10)；
2N bit data for receiving data combination module (5) output, and according to the dynamic of dynamic depth control module (12)
Deep-controlled information carries out the dynamic depth cache module (11) of data buffer storage；
Dynamic depth control module (12) for producing dynamic depth control information；
It is respectively used to receive the 2N bit data of dynamic depth cache module (11) output, and N is carried out to the 2N bit data
N number of N interception modules (13) of bit data cutouts；N number of N interception module (13) terminates by first to n-th, phase
Original position difference 1bit of the data of adjacent N interception module (13) interception in 2N bit data；
For receiving the N bit data that N number of N interception module (13) interception is obtained, and according to the frame header of control module (10)
The data selecting module (14) that the N bit data that corresponding N interception module (13) interception of note signal behavior is obtained are exported；
For the synchronization caching control signal according to control module (10) presynchronization cache module (16) is controlled it is pre- same
Walk buffer control module (15)；
The N bit data corresponding to frame head marking signal for receiving data selecting module (14) output, and according to presynchronization
The N bit data of reception are exported or are used as N as synchrodata by the synchronization caching control signal of buffer control module (15)
The presynchronization cache module (16) of the data cached output of bit presynchronization.
2. frame head Fast synchronization system according to claim 1, it is characterised in that
Control module (10) determines that the detailed process for retrieving frame head is：Judge the N bit of frame head comparison result module (9) output
Whether there is frame head in data, if occurring one in the N bit data of frame head comparison result module (9) output in once comparing
1, it is determined that for frame head mark；If occurring in the N bit data of frame head comparison result module (9) output in once comparing many
Individual 1, then the 1 of lowest order is chosen, is defined as frame head mark.
3. a kind of frame head fast synchronization method, it is characterised in that including：
For caching not synchronization N bit parallel frame datas, and under the control of control module (10) by input buffer module (1)
The step of exporting N bit parallel frame datas；N values are 8 integral multiple, and scope is from 32 to 512；
For by input selecting module (2) will be received in the N bit parallel frame datas of input buffer module (1) and be received in it is pre-
The data cached step that selection output is carried out under the control of control module (10) of N bit presynchronization of synchronization caching module (16)
Suddenly；L values are 8 integral multiple, and scope is from 8 to 64；L is less than N；
The N bit data of output are selected to carry out level cache for selecting module (2) will to be inputted by level cache module (3)
Step；
The step of for receiving the N bit data that level cache module (3) is exported by L2 cache module (4)；
For receiving N bit data and L2 cache module that level cache module (3) is exported by data combination module (5)
(4) the N bit data of output, and step-by-step is the step of be spliced into 2N bit data；
For receiving the 2N bit data that data combination module (5) is exported respectively by N number of L interception concatenation module (6), and will
The step of 2N bit data of reception carry out L bit data cutouts；N number of L interception concatenation module (6) is by first to N
It is individual to terminate, original position difference 2bit of the data that adjacent L interception concatenation module (6) intercepts in 2N bit data；
For receiving the L bit data that L interception concatenation modules (6) export by N number of comparison control module (7) correspondence, by the L
Bit data compare the step of mask information is pre-processed according to the frame head of control module (10)；It is each to compare control module (7)
Bit in L bit data without comparison is subjected to step-by-step and 0 operation, pretreated L bit data are obtained；
For what is inputted by N number of frame head comparing module (8) correspondence by pretreated L bit data and by control module (10)
The step of standard frame head set in advance is compared；The frame head comparing module (8) is by pretreated L bit data and standard
Frame head carries out XOR and compares operation, if the result obtained is 0, and the pretreated L bit data are target frame head, output ratio
To result 1；Otherwise comparison result 0 is exported；
Comparison result step-by-step for being exported N number of frame head comparing module (8) by frame head comparison result module (9) is spliced, shape
The step of into N bit data；
N bit data for being exported by control module (10) to frame head comparison result module (9) judge, according to the N
1 in bit data, it is determined that retrieving frame head mark, and send frame header note signal, synchronization caching control signal and lock flag
The step of signal；
For receiving the 2N bit data that data combination module (5) is exported by dynamic depth cache module (11), and according to dynamic
The step of dynamic depth control information of state depth control block (12) carries out data buffer storage；
The step of for producing dynamic depth control information by dynamic depth control module (12)；
2N bit data for receiving dynamic depth cache module (11) output respectively by N number of N interception module (13), and
The step of N bit data cutouts are carried out to the 2N bit data；N number of N interception module (13) is whole to n-th by first
Only, original position difference 1bit of the data of adjacent N interception module (13) interception in 2N bit data；
N bit data for receiving N number of N interception module (13) interception acquisition by data selecting module (14), and according to
The N bit data that corresponding N interception module (13) interception of frame head mark signal behavior of control module (10) is obtained carry out defeated
The step of going out；
For by presynchronization buffer control module (15) according to the synchronization caching control signal of control module (10) to presynchronization
The step of cache module (16) is controlled；
For receiving the N corresponding to frame head marking signal that data selecting module (14) is exported by presynchronization cache module (16)
Bit data, and according to the synchronization caching control signal of presynchronization buffer control module (15), using the N bit data of reception as
The step of synchrodata output or output data cached as N bit presynchronization.
4. frame head fast synchronization method according to claim 3, it is characterised in that
Control module (10) determines that the detailed process for retrieving frame head is：Judge the N bit of frame head comparison result module (9) output
Whether there is frame head in data, if occurring one in the N bit data of frame head comparison result module (9) output in once comparing
1, it is determined that for frame head mark；If occurring in the N bit data of frame head comparison result module (9) output in once comparing many
Individual 1, then the 1 of lowest order is chosen, is defined as frame head mark.
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