CN105045752B - A kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages - Google Patents
A kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract
The present invention proposes a kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages,SRAM address spaces addressing decoding is directly carried out by PXI bus address and a SRAM reads the multiple of data and reads gating judgement processing,Carried out in a manner of being realized using address decoding with address strobe Synchronization Control,It enormously simplify the Coordination Treatment process of multiple links in flow chart of data processing,The mode for directly decoding addressing SRAM address spaces with address at the same time ingenious solves the problems, such as that SRAM operation rates match with PXI Bus Speeds,Avoid the trouble and risk hidden danger of SRAM read-write clock separate designs,The data section mode for reading a SRAM is directly gated by PXI addresses,Reduce fpga logic realization,It also can cleverly address and be combined with SRAM at the same time,Realize that the direct SRAM wide openings data of PXI buses are continuously read.
Description
Technical field
The present invention relates to digital processing field, more particularly to a kind of high-speed AD data based on wide opening SRAM storages
PXI bus transfer analytic methods.
Background technology
Under low speed sampling situations, since sampling rate is not high, need to only the SRAM for being adapted to sampling width be used to be stored
Design, is typically not required wide opening SRAM to carry out storage realization, so the data transfer parsing of SRAM is also relatively easy
It is more.
And under high speed sampling condition, since sample rate is typically each sampled with GSps or more, the work of rear end SRAM
Matching requirement is extremely difficult to as speed, so in order to realize real-time storage, it is necessary to reduce speed, expansion interface width
Mode handled, the extension of memory interface width is so that its matching problem between transfer bus complicates.
In the prior art, in terms of rate-matched, have using the method for different SRAM read-write clocks to handle PXI buses
With the solution of SRAM read-write rate matching issues, take SRAM write clock to be sampled with high-speed AD and carry out matched design, SRAM
Read clock and carry out matched design with PXI Bus Speeds, so as to coordinate the process of storage transmission, but this method exists for SRAM
Two kinds of operating clocks, add the complexity of SRAM timing control and the risk of storage implementation process, are unfavorable for FPGA progress
The stability Design of logic control.
In terms of data width matching transmission, since SRAM interface width is wider than bus interface width, as multi-disc parallel connection makes
With then often reaching more than ten times or tens times of relation poor again, read since bus can not once take a SRAM away
The data gone out, generally require the internal logical circuit of counter that does in FPGA and judge that processing carries out gradation transmission, such a mode not only adds
Fpga logic flow, also so that bus transfer efficiency reduces, it is impossible to immediate data reading is carried out in a manner of continuation address, is added
PXI bus read operation numbers, extend and read total time, and when being read particularly with Large Volume Data, the time of consuming will be straight
Connect the speed for influencing main control computer processing and the speed of display renewal.
The content of the invention
To solve above-mentioned the deficiencies in the prior art, the present invention proposes a kind of high-speed AD data based on wide opening SRAM storages
PXI bus transfer analytic methods.
The technical proposal of the invention is realized in this way：
A kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages, comprise the following steps：
Step (1)：It is parsed that the PXI buses of n times high-speed AD sampled data for being stored in SRAM read transmission
Journey, needs according to the total interface width K of SRAM data first1, high-speed AD sample quantization bit wide K2, PXI bus data interface widths K3、
SRAM address-bus widths W2To determine that PXI address bus decoding composition and PXI buses read the sampling of n times high-speed AD from SRAM
Data the reading times NL that need to actually carry out；
Step (2)：After the times N L that PXI buses need to be actually read is determined, then host computer main control unit passes through
PXI buses carry out NL continuous traversal access, obtain NL K successively since the base address set3The data number of bit wide
Group XNL；
Step (3)：Judge array of data XNLWhether need the rejecting for carrying out hash to handle, be then to XNLCarry out useless
Data rejecting is handled, and obtains N5The SRAM new data arrays X that a PXI containing useful AD data is readL；Otherwise by data number
Group XNLIndirect assignment gives array of data XL；
Step (4)：To array of data XLThe separating treatment of AD data is carried out, obtains the N number of high-speed AD read from SRAM
Sampled data array X, X data are transmitted to next flow and carry out other signal analysis and processings, and return to step (1), wait next
The transmission dissection process of batch data.
Alternatively, in the step (1), the PXI address bus is decoded as by SRAM address space addressable address sections
With address strobe control address field composition；
Wherein, SRAM address spaces addressable address section width is W2, determined by the address-bus width of SRAM device, should
Address bus docks in FPGA with SRAM address bus in section；It is W that address strobe, which controls address field bit wide,1；PXI address bus
Low W1- 1 to 0 is defined as address strobe control address field, the W of PXI address bus2+W1- 1 is arrived W1Position is defined as
SRAM address space addressable address sections.
Alternatively, address strobe control address field bit wide W1Definite method be：It need to meet following relation：
Wherein, N1It is defined as the maximum number for the complete AD sampled datas that a SRAM read data packet contains, N2It is defined as
PXI bus reads the complete AD sampled datas number that data maximum includes；
Wherein,Value be set to N3, represent that a SRAM reads data and required time is transmitted by PXI buses
Number；N1%N2Value be set to N4If N4More than 0, represent that the AD data amount checks that last time is read are less than N2。
Alternatively, the maximum number N for the complete AD sampled datas that a SRAM read data packet contains1Definite side
Method is K1With K2The maximum positive integer value of ratio：AD data are with sampling order in the SRAM data read
Arrange from low to high.
Alternatively, the N1Definite method in, work as K1With K2When ratio is integer, SRAM storage resources realize AD numbers
According to the peak use rate of storage.
Alternatively, a PXI bus reads the complete AD sampled datas number N that data maximum includes2Determine
Method is K3With K2The maximum positive integer value of ratio：
Alternatively, the N2Definite method in, work as K3With K2When ratio is integer, PXI data bus interfaces realize AD
The peak use rate of data transfer.
Alternatively, the W1Definite method in, work as N3It is equal toWhen, address strobe controls address field to AD data
Gating coding realizes peak use rate.
Alternatively, the W1Definite method in, work as N3It is equal toWhen, and N4During equal to 0, PXI buses realize AD data
The efficiency of transmission maximizes.
Alternatively, in the step (1), it is real that the PXI buses read n times high-speed AD sampled data institute from SRAM
The definite method for the reading times NL that border need to carry out is：
Wherein,Value be set to N5, required PXI operations time are read for calculating n times AD sampled datas
Number,For calculating during n times AD sampled datas are continuously read since address strobe control address field coded number is big
In N3When need the number of operations of the PXI bus hashes that do more.
Alternatively, in the step (2), described NL times continuous traversal cache flush mode, comprises the following steps：
Step (21)：If the count number of continuous traversal access is I, initialization value 0；
Step (22)：It is added with count number I to obtain PXI bus address by PXI buses base address, PXI buses initiate reading
Request；
Step (23)：FPGA takes SRAM according to SRAM address space addressable address after reading request is received
Number, is then judged according to address strobe control address, and gives the AD data accordingly gated in current SRAM data to PXI
Data/address bus；
Step (24)：Main control unit receives data/address bus K3The data of bit wide, and it is assigned to array of data XNLWith I
The numerical value of index, count number I add 1；
Step (25)：Judge whether count number I is equal to NL, be, represent that NL access finishes, wait for AD data solutions
Flow is analysed, otherwise return to step (22).
Alternatively, in the step (23), foundation address strobe control address is judged and by current SRAM
Reading the processing method that the AD data that accordingly gate give PXI data/address bus in data is：
Count W1It is E that the gating of bit wide, which controls address bit values, as E ＜ N3When -1, SRAM is read into E × N that data include2
To (E+1) × N2- 1 AD data is assigned to PXI data/address bus jointly with certain order；As E==(N3- 1) when, such as N4It is equal to
0, then SRAM is read into E × N that data include2To (E+1) × N2- 1 AD data is assigned to PXI numbers jointly with certain order
According to bus, if N4Not equal to 0, then SRAM is read into E × N that data include2To E × N2+N4- 1 AD data is with certain suitable
Sequence is assigned to PXI data/address bus jointly；IfThen 0 processing is sent to PXI bus datas.
Alternatively, the AD data using certain order be assigned to jointly the assignment method of PXI data/address bus as：E ×
N2A AD data are assigned to the K of PXI data/address bus2- 1 to the 0th, E × N2+ 1 AD data is assigned to PXI data/address bus
2 × K2- 1 to K2Position, and so on, (E+1) × N2- 1 AD data is assigned to the N of PXI data/address bus2×
K2- 1 to (N2-1)×K2Position, if PXI data/address bus N2×K2Position and also have a surplus position above, then remaining position zero padding processing or not
Processing；If N4Not equal to 0, then when E is equal to (N3- 1) when, the complete E × N of assignment2+N4After -1 AD data, PXI data/address bus
Remaining high position zero padding processing or not.
Alternatively, the W1The gating of bit wide controls the definite method of address bit values E to be：Wherein subscript H represents the binary value under gating address corresponding positions.
Alternatively, in the step (3), the foundation for whether carrying out hash rejecting processing is： N3Whether etc.
InIt is to illustrate W1Just data are read with a SRAM and led in the address of the address strobe control address field coding gating of bit wide
Cross PXI buses and be transmitted required number and match, the transmission without carrying out zero padding hash operates；IfThen
Illustrate that, in order to realize the work that continuously transmits of PXI buses, centre needs to carry outThe hash transmission operation of number.
Alternatively, it is described to X in the step (3)NLCarry out the process that hash rejects processing, including following step
Suddenly：
Step (31)：If to array of data XNLThe count number of operation is J1, to new data array XLThe count number of operation is
J2, J1And J2Equal initialization value is 0；
Step (32)：Judge J1WithWhether the remainder of complementation is more than or equal to N3, it is to enter step (33)；Otherwise enter
Step (34)；
Step (33)：J1Add 1, enter step (35)；
Step (34)：By array XNLWith J1The data of index are assigned to array XLWith J2The data of index, J1Add 1, J2
Add 1, enter step (35)；
Step (35)：Judge J1Whether it is less than NL, is then return to step (32), otherwise represents that hash has been rejected
Finish, wait for the separating treatment of AD data.
Alternatively, it is described to array of data X in the step (4)LThe separating treatment process of AD data is carried out, including
Following steps：
Step (41)：If to array of data XLThe count number of operation is R1, to the count number of final AD array of data X operations
For R2, R3To separate count number, R1、R2And R3Equal initialization value is 0, and sets θ as K2Bit wide every is all 1 binary number；
Step (42)：By array XLWith R1It is K that the data of index, which are assigned to bit wide,3Operation data δ, and judge R1With N3
Whether the remainder of complementation is equal to N3- 1, it is to enter step (43)；Otherwise enter step (44)；
Step (43)：Judge N4Whether it is equal to 0, is to enter step (44)；Otherwise enter step (47)；
Step (44)：δ and θ are subjected to step-by-step and retain its low K for obtained with operation2The new data of position data is assigned to
Array X is with R2The data of index, R2Add 1, R3Add 1, enter step (45)；
Step (45)：Judge R3Whether N is equal to2, it is then R3Assignment 0, R1Add 1, be then transferred to step (410)；Otherwise into
Enter step (46)；
Step (46)：δ is moved right K2Position, then carries out step-by-step with θ and retains its low K for obtained with operation2Position data
New data be assigned to array X with R2The data of index, R2Add 1, R3Add 1, be then back to step (45)；
Step (47)：δ and θ are subjected to step-by-step and retain its low K for obtained with operation2The new data of position data is assigned to
Array X is with R2The data of index, R2Add 1, R3Add 1, enter step (48)；
Step (48)：Judge R3Whether N is equal to4, it is then R3Assignment 0, R1Add 1, be then transferred to step (410)；Otherwise into
Enter step (49)；
Step (49)：δ is moved right K2Position, then carries out step-by-step with θ and retains its low K for obtained with operation2Position data
New data be assigned to array X with R2The data of index, R2Add 1, R3Add 1, be then back to step (48)；
Step (410)：Judge R1Whether N is less than5, it is then return to step (42), at the separation for otherwise representing N number of AD data
Science and engineering has been completed.
Alternatively, the PXI address bus, the bus data variable quantity of its address increment are calculated as K3, for byte
Carry out incremental computations situation, need byBit wide is as lowest order address increment, other corresponding address fields are to moving to leftPosition.
Alternatively, the timing really of PXI bus address is carried out, need to be with count number in the case of using byte as increment
Calculated as address change.
The beneficial effects of the invention are as follows：
(1) SRAM address spaces addressing decoding is directly carried out by PXI bus address and a SRAM reads the more of data
It is secondary to read gating judgement processing, carried out, enormously simplify in a manner of being realized using address decoding with address strobe Synchronization Control
The Coordination Treatment process of multiple links in flow chart of data processing；
(2) in a manner of directly decoding addressing SRAM address spaces by address, ingenious to solve SRAM operation rates total with PXI
The problem of line rate matches, avoids the trouble and risk hidden danger of SRAM read-write clock separate designs；
(3) the data section mode for reading a SRAM is directly gated by PXI addresses, reduces FPGA logic realizations,
It also can cleverly address and be combined with SRAM at the same time, realize that the direct SRAM wide openings data of PXI buses are continuously read；
(4) data quickly continuous read operation is carried out in a manner of the transmission of PXI blocks or burst transfer, substantially increases wide opening
The speed and efficiency that SRAM data is read, shorten the time of host computer data processing, improve system performance.
Embodiment
Below in conjunction with the embodiment of the present invention, the technical solution in the embodiment of the present invention is clearly and completely retouched
State, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.Based on the present invention
In embodiment, the every other implementation that those of ordinary skill in the art are obtained without making creative work
Example, belongs to the scope of protection of the invention.
In high-speed sampling design is implemented, because high-speed AD sampling rate is high, rear end real-time storage difficulty can be very big, design
When need to consider sampling rate and memory rate, sample matching relationship good between bit wide and memory interface width, usually
Storage is carried out by the way of multi-disc wide opening SRAM parallel memorizings, and storage speed is reduced in a manner of extension storage interface width
Rate, improves logic operability, reduces storing process risk.And the extension of SRAM interface width, in PXI bus transfers and parsing
Aspect brings the problem of new again so that transmission matching complicates, and transmission parsing complicates.The method of the present invention is based on this back of the body
That is realized under scape is adapted to the method for being transmitted parsing after high-speed AD sampled data SRAM is stored by PXI buses.
The present invention proposes a kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages, its base
Present principles are the modes synchronously realized with address strobe using address decoding, and the high-speed AD that SRAM storages are carried out by FPGA samples
Data transfer is read and data transfer matched design, and ingenious solve SRAM operation rates and the synchronism of PXI Bus Speeds is asked
Topic, solves the problems, such as the matching transmission of SRAM interface width and PXI highway widths, realizes the high-speed AD data of SRAM storages
It is effective to improve transmission control flow by the orderly effectively transmission of PXI buses, improve bus transfer timeliness, while specification
AD data bus transmission forms, simplify AD data transfers parsing difficulty, can lifting system transmission performance.
The method of the present invention directly carries out SRAM address spaces addressing decoding by PXI bus address and a SRAM is read
The multiple of data reads gating judgement processing, is carried out in a manner of being realized using address decoding with address strobe Synchronization Control.PXI
Bus address is made of two parts, and low level section part controls address field for address strobe, and high-order section addresses for SRAM address spaces
Address field.SRAM addressable address sections are directly docked in FPGA with SRAM address bus, directly by PXI bus appropriate address sections Lai
The mode of SRAM addressing of address change is updated, can in the case where high-speed sampling SRAM operation rates are far above PXI Bus Speeds
Ignore the nonsynchronous problem of SRAM and PXI Bus Speeds, brought great convenience to design, can effectively simplify FPGA design flow.
The change of low level sector address gating, does not interfere with the process of high-order segment addressing decoding, by the organic assembling of PXI bus address,
When PXI buses carry out continuous reading transmission, always make low level section gating address and high-order section decoding addressable address co-ordination,
Realize maximization transmittability of the PXI buses under its configuration surroundings.
PXI bus address two parts specifically take how many addresses bit wide, take which address bit scope of address, need to be by
SRAM total datas interface width, high-speed AD sampling bit wide, PXI bus datas interface width, SRAM maximum address scopes etc. are really
It is fixed.
A kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages of the present invention, specifically include
Following steps：
Step (1)：It is parsed that the PXI buses of n times high-speed AD sampled data for being stored in SRAM read transmission
Journey, needs according to the total interface width K of SRAM data first1, high-speed AD sample quantization bit wide K2, PXI bus data interface widths K3、
SRAM address-bus widths W2To determine that PXI address bus decoding composition and PXI buses read the sampling of n times high-speed AD from SRAM
Data the reading times NL that need to actually carry out；
Step (2)：After the times N L that PXI buses need to be actually read is determined, then host computer main control unit passes through
PXI buses carry out NL continuous traversal access, obtain NL K successively since the base address set3The data number of bit wide
Group XNL；
Step (3)：Judge array of data XNLWhether need the rejecting for carrying out hash to handle, be then to XNLCarry out useless
Data rejecting is handled, and obtains N5The SRAM new data arrays X that a PXI containing useful AD data is readL；Otherwise by data number
Group XNLIndirect assignment gives array of data XL；
Step (4)：To array of data XLThe separating treatment of AD data is carried out, obtains the N number of high-speed AD read from SRAM
Sampled data array X, X data are transmitted to next flow and carry out other signal analysis and processings, and return to step (1), wait next
The transmission dissection process of batch data.
In above-mentioned steps (1), PXI address bus is decoded as by SRAM address space addressable address sections and address strobe control
Address field forms.
Wherein, SRAM address spaces addressable address section width is W2, determined by the address-bus width of SRAM device, should
Address bus docks in FPGA with SRAM address bus in section；It is W that address strobe, which controls address field bit wide,1；PXI address bus
Low W1- 1 to 0 is defined as address strobe control address field, the W of PXI address bus2+W1- 1 is arrived W1Position is defined as
SRAM address space addressable address sections.
Above-mentioned address strobe control address field bit wide W1Definite method be：It need to meet following relation：
N1It is defined as the maximum number for the complete AD sampled datas that a SRAM read data packet contains, N1Definite method be
K1With K2The maximum positive integer value of ratio：It is assumed herein that AD data are to adopt in the SRAM data read
Sample order arranges from low to high, i.e., minimum, the N of data row number first adopted1When a AD data are in the SRAM data that homogeneous is read
Between on most rearward.
Above-mentioned N1Definite method in, work as K1With K2When ratio is integer, SRAM storage resources realize the storage of AD data
Peak use rate.
N2It is defined as a PXI bus and reads the complete AD sampled datas number that data maximum includes, N2Definite method be
K3With K2The maximum positive integer value of ratio：
Above-mentioned N2Definite method in, work as K3With K2When ratio is integer, PXI data bus interfaces realize AD data transfers
Peak use rate.
Value be set to N3, represent that a SRAM reads data and required number is transmitted by PXI buses；N1%
N2Value be set to N4If N4More than 0, represent that the AD data amount checks that last time is read are less than N2。
Above-mentioned W1Definite method in, work as N3It is equal toWhen, it is real that address strobe controls address field to encode the gating of AD data
Existing peak use rate.
Above-mentioned W1Definite method in, work as N3It is equal toWhen, and N4During equal to 0, PXI buses realize the effect of AD data transfers
Rate maximizes.
Work as K1With K2When ratio is integer, work as K3With K2When ratio is integer, work as N3It is equal toWhen, and N4, can be real during equal to 0
Existing SRAM storage resources, PXI bus interface resource utilization maximize, and PXI bus transfers efficiency maximizes.
In above-mentioned steps (1), PXI buses read from SRAM n times high-speed AD sampled data the reading that need to actually carry out
The definite method of times N L is：
Wherein,Value be set to N5, required PXI operations time are read for calculating n times AD sampled datas
Number,For calculating during n times AD sampled datas are continuously read since address strobe control address field coded number is big
In N3When need the number of operations of the PXI bus hashes that do more.
In above-mentioned steps (2), described NL times continuous traversal cache flush mode, comprises the following steps：
Step (21)：If the count number of continuous traversal access is I, initialization value 0；
Step (22)：It is added with count number I to obtain PXI bus address by PXI buses base address, PXI buses initiate reading
Request；Above-mentioned PXI buses base address, can start for zero-address, can not also start for zero-address, can according to specific PXI
Location service condition and SRAM storage conditions are definite to do；
Step (23)：FPGA takes SRAM according to SRAM address space addressable address after reading request is received
Number, is then judged according to address strobe control address, and gives the AD data accordingly gated in current SRAM data to PXI
Data/address bus；
Step (24)：Main control unit receives data/address bus K3The data of bit wide, and it is assigned to array of data XNLWith I
The numerical value of index, count number I add 1；
Step (25)：Judge whether count number I is equal to NL, be, represent that NL access finishes, wait for AD data solutions
Flow is analysed, otherwise return to step (22).
In above-mentioned steps (23), judged according to address strobe control address and read current SRAM corresponding in data
The processing method that the AD data of gating give PXI data/address bus is：
Count W1It is E that the gating of bit wide, which controls address bit values, as E ＜ N3When -1, SRAM is read into E × N that data include2
To (E+1) × N2- 1 AD data is assigned to PXI data/address bus jointly with certain order；As E==(N3- 1) when, such as N4It is equal to
0, then SRAM is read into E × N that data include2To (E+1) × N2- 1 AD data is assigned to PXI numbers jointly with certain order
According to bus, if N4Not equal to 0, then SRAM is read into E × N that data include2To E × N2+N4- 1 AD data is with certain suitable
Sequence is assigned to PXI data/address bus jointly；IfThen 0 processing is sent to PXI bus datas.
Wherein, AD data using certain order be assigned to jointly the assignment method of PXI data/address bus as：E × N2A AD numbers
According to the K for being assigned to PXI data/address bus2- 1 to the 0th, E × N2+ 1 AD data be assigned to PXI data/address bus the 2nd ×
K2- 1 to K2Position, and so on, (E+1) × N2- 1 AD data is assigned to the N of PXI data/address bus2×K2- 1 is arrived
(N2-1)×K2Position, if PXI data/address bus N2×K2Position and position of also having a surplus above, then remaining position zero padding are handled or not handled；If
N4Not equal to 0, then when E is equal to (N3- 1) when, the complete E × N of assignment2+N4After -1 AD data, the residue of PXI data/address bus is high
Position zero padding processing or not.
Wherein, W1The gating of bit wide controls the definite method of address bit values E to be：
Wherein subscript H represents the binary value under gating address corresponding positions.
In above-mentioned steps (3), if carrying out the foundation that hash rejecting is handled is：N3Whether it is equal toIt is to illustrate W1
Just data are read with a SRAM and passed by PXI buses in the address of the address strobe control address field coding gating of bit wide
Defeated required number matches, and the transmission without carrying out zero padding hash operates；IfThen illustrate to realize PXI
Bus continuously transmits work, and centre needs to carry outThe hash transmission operation of number.
In above-mentioned steps (3), to XNLThe process that hash rejects processing is carried out, is comprised the following steps：
Step (31)：If to array of data XNLThe count number of operation is J1, to new data array XLThe count number of operation is
J2, J1And J2Equal initialization value is 0；
Step (32)：Judge J1WithWhether the remainder of complementation is more than or equal to N3, it is to enter step (33)；Otherwise enter
Step (34)；
Step (33)：J1Add 1, enter step (35)；
Step (34)：By array XNLWith J1The data of index are assigned to array XLWith J2The data of index, J1Add 1, J2
Add 1, enter step (35)；
Step (35)：Judge J1Whether it is less than NL, is then return to step (32), otherwise represents that hash has been rejected
Finish, wait for the separating treatment of AD data.
It is described to array of data X in above-mentioned steps (4)LCarry out the separating treatment process of AD data, including following step
Suddenly：
Step (41)：If to array of data XLThe count number of operation is R1, to the count number of final AD array of data X operations
For R2, R3To separate count number, R1、R2And R3Equal initialization value is 0, and sets θ as K2Bit wide every is all 1 binary number；
Step (42)：By array XLWith R1It is K that the data of index, which are assigned to bit wide,3Operation data δ, and judge R1With N3
Whether the remainder of complementation is equal to N3- 1, it is to enter step (43)；Otherwise enter step (44)；
Step (43)：Judge N4Whether it is equal to 0, is to enter step (44)；Otherwise enter step (47)；
Step (44)：δ and θ are subjected to step-by-step and retain its low K for obtained with operation2The new data of position data is assigned to
Array X is with R2The data of index, R2Add 1, R3Add 1, enter step (45)；
Step (45)：Judge R3Whether N is equal to2, it is then R3Assignment 0, R1Add 1, be then transferred to step (410)；Otherwise into
Enter step (46)；
Step (46)：δ is moved right K2Position, then carries out step-by-step with θ and retains its low K for obtained with operation2Position data
New data be assigned to array X with R2The data of index, R2Add 1, R3Add 1, be then back to step (45)；
Step (47)：δ and θ are subjected to step-by-step and retain its low K for obtained with operation2The new data of position data is assigned to
Array X is with R2The data of index, R2Add 1, R3Add 1, enter step (48)；
Step (48)：Judge R3Whether N is equal to4, it is then R3Assignment 0, R1Add 1, be then transferred to step (410)；Otherwise into
Enter step (49)；
Step (49)：δ is moved right K2Position, then carries out step-by-step with θ and retains its low K for obtained with operation2Position data
New data be assigned to array X with R2The data of index, R2Add 1, R3Add 1, be then back to step (48)；
Step (410)：Judge R1Whether N is less than5, it is then return to step (42), at the separation for otherwise representing N number of AD data
Science and engineering has been completed.
PXI address bus, the bus data variable quantity of its address increment are calculated as K3, for carrying out incremental computations with byte
Situation, the method for the present invention is equally applicable, only need byBit wide is as lowest order address increment, other are accordingly
Location section is to moving to leftPosition；Bus address timing really is carried out in the case of using byte as increment, in step (2), is needed
With count numberCalculated as address change.
The method of the present invention is described in detail with reference to a specific embodiment.
First, it is assumed that the total interface width K of SRAM data1For 144 bit wides, high-speed AD sample quantization bit wide K2For 12 bit wides,
PXI bus data interface widths K3The specific transmission parsing implementation process explanation of the method for the present invention is carried out for 32 bit wides.
According to information above, it is first determined the mode of PXI addresses segmentation composition.The data read for a SRAM, its
Comprising sampled data number N1, it may be determined that it is
In order to save expense, the utilization for realizing storage resource is maximized, SRAM interface width is chosen for AD in design
The integral multiple of bit wide, for non-integral multiple, the SRAM bit wides that remaining deficiency once stores will be idle.
The sampled data number N that maximum can be included for the data that a PXI bus is read2For K3With K2The maximum of ratio
Positive integer value, i.e.,Therefore, the bit wide W of address strobe control address field1Need to meetI.e.Thus it can determine that W1For 3, i.e., using the 2~0 of PXI address bus
Position controls address field into row address strobe, realizes the gating of the 12 AD sampled datas included to a SRAM address reading data
Read operation.And the wide W of SRAM address space addressable address sections2Determined by selected specific SRAM type number, for example, this
It is 1M addressing spaces that SRAM is drafted in embodiment, therefore W2=20, i.e., carry out SRAM using 22~3 of PXI address bus
Address decoding addresses, so PXI address bus is only using its low 23 progress data read-write operation in the present embodiment.
Because SRAM data overall width is 144, a SRAM, which is read, includes 12 AD sampled datas, and PXI data/address bus
Width is 32, once reads and is at best able to read 2 complete AD sampled datas, so the data that a SRAM is read need 6
Secondary PXI read operations, which can be read, to be finished, and uses 2~0 of PXI address bus to be controlled into row address strobe, 3 ground
Location can gate the reading of 8 data of control, and in order to realize the continuous read operation of PXI buses, every 8 gatings control 2 times high
To send zero to be filled in FPGA.According to the order of digital independent, the stringent order by 6 readings is needed to be given in FPGA
Corresponding data, the control that PXI addresses carry out SRAM data reading are described as follows shown in table 1.
Table 1：PXI addresses use description
Since AD sampling output data width is 12, so 2 AD data are included altogether for each 32 PXI data,
11~0 sample for (n-1)th sampling, 23~12 for n-th, and 31~24 are not concerned with, and low level time is preceding in time in high precedence, number
Incrementally read from low to high according to according to address.
Resolving, host computer master control list are transmitted in the reading of the N=1024 sampled data for being stored in SRAM
Before member access, actual address realm when being first depending on the required length for obtaining sampled data to determine that PXI buses are fetched.
Because of each SRAM addressing change once, 12 AD data are often taken, PXI buses just need to carry out 2 times and invalid take zero behaviour
Make, so the actual number fetched of PXI buses is more than the n times data of actual needs, the actual continuous-reading of PXI buses
Times N L, it may be determined that be：
Wherein,Required PXI number of operations is read for calculating n times sampled data,Based on
Calculate the PXI number of operations for needing to do more during n times sampled data is continuously read.
PXI is actual need read operation number to determine after, since the base address set, carry out 32 bit data bus
682 times continuation address is incrementally fetched, and obtains the array of data X of 682 32 bit widesNL.The base address of PXI can be zero ground herein
Location starts, and can not also start for zero-address, can be changed according to specific PXI address utilizations and SRAM storage conditions,
Can flexible Application.Then, based on this array of data, it is transmitted the parsing of data.
Because in the present embodiment, the data acquired in last 2 times of low 3 consecutive variations of PXI bus address are FPGA institutes
The null value hash sent, so needing to be weeded out first.
The method for rejecting hash is, from array of data XNL682 data start counting up, if with count value by 8
The value of complementation is 6 or 7, then judges that the data for hash, are rejected, if remainder is not 6 or 7, is determined as useful reading
It, is assigned to new data array X by access evidence successivelyL, 170 hashes are finally rejected, obtain 512 useful datas.
Useful data array XLEach data be 32 bit wide PXI data, each data contain 2 useful AD data, institute
With need to be by XLEach data carry out AD data separation, be reassembled into 1024 AD data of actual needs, it is separated
Method is：From array of data XLProceed by, by low 12 of 32 data with hexadecimal number 0xFFF carry out step-by-steps with behaviour
Make, obtained new number will only retain its low 12 effective information, be an effective AD data, be assigned to final data array
X, 32 data are moved right 12, will move to low level in 23~12 another effective AD data originally, then with ten
Senary number 0xFFF carries out step-by-step and operation, and obtained new number will only retain its low 12 effective information, and then be assigned to data
Next number of array X, all X are completed with thisLThe AD data separatings of array to X arrays operate, and can obtain X arrays 1024
The data that the slave SRAM being actually needed is read.
During whole transmission parsing, there are middle by-carriage null value and the process of null value hash is rejected, here
Simply be illustrated the method for the present invention actual application and application in situation that may be present, although it is every 8 times reading
Have in operation 2 readings for hash, seem and waste transmission time, but in real work, due to holding for PXI buses
Continuous reading capability is achieved, and method greatly improves actually total work efficiency compared with the prior art.
If front end SRAM data width K1When expanding to 192 bit wide, then it is not required to carry out the middle supplement of hash again,
Actual transmissions efficiency is by higher.
In the present embodiment, PXI data/address bus has only used its low 24, and most-significant byte is not utilized, this is also and designs
Related, the present embodiment is merely illustrative in practical application may be there are such case, if high-speed AD sampling quantifies bit wide
K2For 8 when, then the present embodiment can then reach maximization in terms of PXI data transmission efficiencys.
The method of the present invention directly carries out SRAM address spaces addressing decoding by PXI bus address and a SRAM is read
The multiple of evidence of fetching reads gating judgement processing, is carried out in a manner of being realized using address decoding with address strobe Synchronization Control,
The Coordination Treatment process of multiple links in flow chart of data processing is enormously simplify, while addressing SRAM addresses are directly decoded with address
The mode in space is ingenious to solve the problems, such as that SRAM operation rates match with PXI Bus Speeds, avoids SRAM read-write clocks
The trouble and risk hidden danger of separate design.The data section mode for reading a SRAM is directly gated by PXI addresses, is reduced
Fpga logic is realized, while also can cleverly be addressed and be combined with SRAM, realizes the direct SRAM wide openings data of PXI buses
It is continuous to read, data quickly continuous read operation can be carried out in a manner of the transmission of PXI blocks or burst transfer, substantially increase width
The speed and efficiency that mouth SRAM data is read, shorten the time of host computer data processing, improve system performance.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
With within principle, any modification, equivalent replacement, improvement and so on, should all be included in the protection scope of the present invention god.
Claims (19)
1. a kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages, it is characterised in that including following
Step：
Step (1)：The PXI buses of n times high-speed AD sampled data for being stored in SRAM read transmission resolving, first
First need according to the total interface width K of SRAM data1, high-speed AD sample quantization bit wide K2, PXI bus data interface widths K3, SRAM
Location highway width W2To determine that PXI address bus decoding composition and PXI buses read n times high-speed AD sampled data institute from SRAM
The reading times NL that need to actually carry out；
Step (2)：After the times N L that PXI buses need to be actually read is determined, then host computer main control unit is total by PXI
Line carries out NL continuous traversal access, obtains NL K successively since the base address set3The array of data X of bit wideNL；
Step (3)：Judge array of data XNLWhether need the rejecting for carrying out hash to handle, be then to XNLHash is carried out to pick
Except processing, and obtain N5The SRAM new data arrays X that a PXI containing useful AD data is readL；Otherwise by array of data XNLDirectly
Connect and be assigned to array of data XL；
Step (4)：To array of data XLThe separating treatment of AD data is carried out, obtains the N number of high-speed AD hits read from SRAM
According to array X, X data are transmitted to next flow and carry out other signal analysis and processings, and return to step (1), wait next batch data
Transmission dissection process.
2. a kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages as claimed in claim 1, its
It is characterized in that, in the step (1), the PXI address bus is decoded as by SRAM address space addressable address sections and address
Gating control address field composition；
Wherein, SRAM address spaces addressable address section width is W2, determined by the address-bus width of SRAM device, SRAM
Location space addressable address section is docked in FPGA with SRAM address bus；It is W that address strobe, which controls address field bit wide,1；PXI addresses
The low W of bus1- 1 to 0 is defined as address strobe control address field, the W of PXI address bus2+W1- 1 is arrived W1Position is defined as
SRAM address space addressable address sections.
3. a kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages as claimed in claim 2, its
It is characterized in that, address strobe control address field bit wide W1Definite method be：It need to meet following relation：
Wherein, N1It is defined as the maximum number for the complete AD sampled datas that a SRAM read data packet contains, N2It is defined as once
PXI buses read the complete AD sampled datas number that data maximum includes；
Wherein,Value be set to N3, represent that a SRAM reads data and required number is transmitted by PXI buses；
N1%N2Value be set to N4If N4More than 0, represent that the AD data amount checks that last time is read are less than N2。
4. a kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages as claimed in claim 3, its
It is characterized in that, the maximum number N for the complete AD sampled datas that described SRAM read data packet contains1Definite method be K1
With K2The maximum positive integer value of ratio：In the SRAM data read AD data with sampling order by it is low to
Height arrangement.
5. a kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages as claimed in claim 4, its
It is characterized in that, the N1Definite method in, work as K1With K2When ratio is integer, SRAM storage resources realize that AD data store
Peak use rate.
6. a kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages as claimed in claim 3, its
It is characterized in that, described PXI bus reads the complete AD sampled datas number N that data maximum includes2Definite method be K3
With K2The maximum positive integer value of ratio：
7. a kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages as claimed in claim 6, its
It is characterized in that, the N2Definite method in, work as K3With K2When ratio is integer, PXI data bus interfaces realize that AD data pass
Defeated peak use rate.
8. a kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages as claimed in claim 3, its
It is characterized in that, the W1Definite method in, work as N3It is equal toWhen, address strobe controls address field to compile the gating of AD data
Code realizes peak use rate.
9. a kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages as claimed in claim 3, its
It is characterized in that, the W1Definite method in, work as N3It is equal toWhen, and N4During equal to 0, PXI buses realize AD data transfers
Efficiency maximizes.
10. a kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages as claimed in claim 1,
It is characterized in that, in the step (1), the PXI buses read n times high-speed AD sampled data institute from SRAM actually need to be into
The definite method of capable reading times NL is：
Wherein,Value be set to N5, required PXI number of operations is read for calculating n times AD sampled datas,For calculating during n times AD sampled datas are continuously read since address strobe control address field coded number is more than N3
When need the number of operations of the PXI bus hashes that do more.
11. a kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages as claimed in claim 1,
It is characterized in that, in the step (2), described NL times continuous traversal cache flush mode, comprises the following steps：
Step (21)：If the count number of continuous traversal access is I, initialization value 0；
Step (22)：It is added with count number I to obtain PXI bus address by PXI buses base address, PXI buses initiate reading request；
Step (23)：FPGA fetches SRAM according to SRAM address space addressable address, then after reading request is received
Judged according to address strobe control address, and it is total to give the AD data accordingly gated in current SRAM data to PXI data
Line；
Step (24)：Main control unit receives data/address bus K3The data of bit wide, and it is assigned to array of data XNLWith I indexes
Numerical value, count number I add 1；
Step (25)：Judge whether count number I is equal to NL, be, represent that NL access finishes, wait for AD data resolution flows
Journey, otherwise return to step (22).
12. a kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages as claimed in claim 11,
It is characterized in that, in the step (23), foundation address strobe control address is judged and is read current SRAM
The processing method that the AD data accordingly gated in data give PXI data/address bus is：
Count W1It is E that the gating of bit wide, which controls address bit values, as E ＜ N3When -1, SRAM is read into E × N that data include2To (E+
1)×N2- 1 AD data is assigned to PXI data/address bus jointly with certain order；As E==(N3- 1) when, such as N4Equal to 0, then will
SRAM reads E × N that data include2To (E+1) × N2- 1 AD data is assigned to PXI data/address bus jointly with certain order,
If N4Not equal to 0, then SRAM is read into E × N that data include2To E × N2+N4- 1 AD data is assigned so that certain order is common
It is worth and gives PXI data/address bus；IfThen 0 processing is sent to PXI bus datas.
13. a kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages as claimed in claim 12,
It is characterized in that, the AD data using certain order be assigned to jointly the assignment method of PXI data/address bus as：E × N2It is a
AD data are assigned to the K of PXI data/address bus2- 1 to the 0th, E × N2+ 1 AD data is assigned to the 2nd of PXI data/address bus
×K2- 1 to K2Position, and so on, (E+1) × N2- 1 AD data is assigned to the N of PXI data/address bus2×K2- 1
To (N2-1)×K2Position, if PXI data/address bus N2×K2Position and position of also having a surplus above, then remaining position zero padding are handled or not handled；
If N4Not equal to 0, then when E is equal to (N3- 1) when, the complete E × N of assignment2+N4After -1 AD data, the residue of PXI data/address bus is high
Position zero padding processing or not.
14. a kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages as claimed in claim 12,
It is characterized in that,
The W1The gating of bit wide controls the definite method of address bit values E to be：Wherein
Subscript H represents the binary value under gating address corresponding positions.
15. a kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages as claimed in claim 1,
It is characterized in that, in the step (3), the foundation for whether carrying out hash rejecting processing is：N3Whether it is equal to
It is to illustrate W1Just data are read with a SRAM and pass through PXI in the address of the address strobe control address field coding gating of bit wide
Bus is transmitted required number and matches, and the transmission without carrying out zero padding hash operates；IfThen explanation is
Realize the work that continuously transmits of PXI buses, centre needs to carry outThe hash transmission operation of number.
16. a kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages as claimed in claim 1,
It is characterized in that, in the step (3), it is described to XNLThe process that hash rejects processing is carried out, is comprised the following steps：
Step (31)：If to array of data XNLThe count number of operation is J1, to new data array XLThe count number of operation is J2, J1
And J2Equal initialization value is 0；
Step (32)：Judge J1WithWhether the remainder of complementation is more than or equal to N3, it is to enter step (33)；Otherwise enter step
(34)；
Step (33)：J1Add 1, enter step (35)；
Step (34)：By array XNLWith J1The data of index are assigned to array XLWith J2The data of index, J1Add 1, J2Add 1, into
Enter step (35)；
Step (35)：Judge J1Whether it is less than NL, is then return to step (32), otherwise represents that hash has been rejected and finishes, wait
Carry out the separating treatment of AD data.
17. a kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages as claimed in claim 1,
It is characterized in that, in the step (4), it is described to array of data XLThe separating treatment process of AD data is carried out, including it is following
Step：
Step (41)：If to array of data XLThe count number of operation is R1, the count number to final AD array of data X operations is R2,
R3To separate count number, R1、R2And R3Equal initialization value is 0, and sets θ as K2Bit wide every is all 1 binary number；
Step (42)：By array XLWith R1It is K that the data of index, which are assigned to bit wide,3Operation data δ, and judge R1With N3Complementation
Remainder whether be equal to N3- 1, it is to enter step (43)；Otherwise enter step (44)；
Step (43)：Judge N4Whether it is equal to 0, is to enter step (44)；Otherwise enter step (47)；
Step (44)：δ and θ are subjected to step-by-step and retain its low K for obtained with operation2The new data of position data is assigned to array X
With R2The data of index, R2Add 1, R3Add 1, enter step (45)；
Step (45)：Judge R3Whether N is equal to2, it is then R3Assignment 0, R1Add 1, be then transferred to step (410)；Otherwise enter step
(46)；
Step (46)：δ is moved right K2Position, then carries out step-by-step with θ and retains its low K for obtained with operation2Position data it is new
Data are assigned to array X with R2The data of index, R2Add 1, R3Add 1, be then back to step (45)；
Step (47)：δ and θ are subjected to step-by-step and retain its low K for obtained with operation2The new data of position data is assigned to array X
With R2The data of index, R2Add 1, R3Add 1, enter step (48)；
Step (48)：Judge R3Whether N is equal to4, it is then R3Assignment 0, R1Add 1, be then transferred to step (410)；Otherwise enter step
(49)；
Step (49)：δ is moved right K2Position, then carries out step-by-step with θ and retains its low K for obtained with operation2Position data it is new
Data are assigned to array X with R2The data of index, R2Add 1, R3Add 1, be then back to step (48)；
Step (410)：Judge R1Whether N is less than5, it is then return to step (42), otherwise represents the separating treatment work of N number of AD data
Complete.
18. a kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages as claimed in claim 1,
It is characterized in that, the PXI address bus, the bus data variable quantity of its address increment is calculated as K3, for being carried out with byte
The situation of incremental computations, need byBit wide is as lowest order address increment, other corresponding address fields are to moving to left
Position.
19. a kind of high-speed AD data PXI bus transfer analytic methods based on wide opening SRAM storages as claimed in claim 11,
It is characterized in that, the timing really of PXI bus address is carried out, need to be with count number in the case of using byte as incrementAs
Address change is calculated.
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| CN103150129A (en) * | 2013-04-02 | 2013-06-12 | 哈尔滨工业大学 | PXIe interface Nand Flash data steam disc access accelerating method |
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| CN103138676A (en) * | 2012-12-19 | 2013-06-05 | 电子科技大学 | Motor compound control system and control method thereof |
| CN103150129A (en) * | 2013-04-02 | 2013-06-12 | 哈尔滨工业大学 | PXIe interface Nand Flash data steam disc access accelerating method |
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