CN105045559B - Binary logic circuits, the method and its manufacturing method for obtaining the expression of its hardware - Google Patents
Binary logic circuits, the method and its manufacturing method for obtaining the expression of its hardware Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/17—Function evaluation by approximation methods, e.g. inter- or extrapolation, smoothing, least mean square method
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/556—Logarithmic or exponential functions
Abstract
Binary logic circuits, the method and its manufacturing method for obtaining the expression of its hardware.It provides a kind of for approaching the binary logic circuits of mathematical function in predefined scope as a series of straightways, every straightway all has one of predetermined one group of fixed slope and corresponding base value, the binary logic circuits include: input, for receiving the input variable in predefined scope；A plurality of logic chain, every logic chain all include: binary multiplier, suitable for using h-1 binary adder to execute the multiplication with each slope this group of fixed slope, wherein h is extension Hamming weight；And binary adder, suitable for base value to be added to the input or output of binary multiplier；And selection logic, it is configured to according to one of Input variable selection logic chain, to provide the approximation of mathematical function for received input variable.
Description
Technical field
The present invention relates to a series of binary logics for approaching mathematic curve in predefined scope as straightways
The method that circuit and the hardware for obtaining such binary logic circuits indicate.
Background technique
It is generally desirable to execute certain functions at a high speed within hardware.For example, for executing computer graphical processing and number letter
The integrated circuit of number processing may be frequently necessary to give the value that input value calculates logarithm or gamma function.It is such for executing
The hardware of calculating usually input value as defined in the range of operate, and usually require that calculate the function reach the accurate of specific grade
Degree.This allows hardware designer to approach using to given function, to provide the amount of area not consumed excessively on integrated circuit
Low latency solution.
log2Function is such function, is usually realized with silicon, and by convention, usually in section [1,2]
It is interior to be approached by straight line.Michele (Mitchell) is shown in FIG. 1 and approaches 102.Although being mentioned when realizing within hardware
For quickly approaching, but it can be seen that especially in the near middle of section [1,2], Michele is approached different from log2Function
Curve 101.
The poor accuracy that Michele approaches leads to the exploitation of the method based on look-up table, such as in United States Patent (USP) 4,583,
Described in 180.These methods are used in the meter for replacing function approximation in the big table for precalculating value to the lookup of function itself
It calculates (for example, straight line of Michele).Such method is accurate, but integrated to the request memory of look-up table consumption large area
Circuit, and may be relatively slow.
Develop the further refining of LUT Method, using the interpolation between the value in smaller look-up table, with
While reducing the size of table, the accuracy of similar degree is provided.By Suganth Paul et al. in their paper " A fast
hardware approach for approximate,efficient logarithm and antilogarithm
Computations ", IEEE Transactions on VLSI are proposed in Systems, Vol.17, No.2,2009 2 months
A kind of fresh approach of the type.However, this method requires multiplying using the multiplication for being adapted for carrying out two variables within hardware
Method array.Such structure is complicated, and consumes large area on the integrated.
Summary of the invention
According to the first aspect of the invention, a kind of binary logic circuits are provided, for existing as a series of straightways
Approach mathematical function in predefined scope, every straightway all has a slope in predetermined one group of fixed slope and corresponding
Base value, the binary logic circuits include:
Input, for receiving the input variable in predefined scope；
A plurality of logic chain, every logic chain all include:
Binary multiplier, suitable for use h-1 binary adder execute with it is corresponding this group of fixed slope
The multiplication of one slope, wherein h is the minimum Hamming weight of the following terms:
The binary representation of fixed slope；
The ternary of fixed slope indicates；And
Two binary numbers of conduct, two trits or the binary number of the fixed slope and one three into
The expression of the product of number processed；
H-1 binary adder is logically constructed such that with the fixed slope with minimum Hamming weight h
It indicates to execute multiplication；And
Binary adder, one suitable for the input or output that base value is added to binary multiplier；And
Logic is selected, is configured to according to one in Input variable selection logic chain, to become for the received input of institute
Amount provides the approximation of mathematical function.
Each fixed slope in scheduled one group of fixed slope may have less than or equal to threshold value it is corresponding most
Small Hamming weight h, wherein threshold value determines the limitation for being suitable for being used to execute the quantity of the adder of multiplication to binary multiplier.
Threshold value can be 2 or 3.
Minimum Hamming weight h can be less than or equal to 3.
Selection logic can be configured to by the way that the received input variable of institute compares with predetermined one group of break value, to select
One in logic chain is selected, each break value indicates the value for the input variable demarcated to one or more straightways.
Selection logic can be configured to determine a pair of adjacent break value, and the received input variable of institute is located at this to adjacent disconnected
Between point value, and the selection logical response, in the determination, selection corresponds to this to the straightway between adjacent break value
Logic chain.
Each break value in one group of break value can be used in selection logic in the form of following:
The binary representation of break value；
The ternary of break value indicates；Or
Two binary numbers of conduct, two trits or the binary number of break value and a trit
Product expression；
Form for each break value is the expression of the break value with minimum Hamming weight.
The minimum Hamming weight of each break value in one group of break value can be less than or equal to 3.
Mathematical function can be expressed as the form of y=f (x), wherein x and y indicates the value along each cartesian axis.
The binary adder of every logic chain, which can be arranged to, is added to binary multiplier for corresponding base value
Output.
Every straightway all indicates a part of the line intersected at base value with y-axis.
The binary adder of every logic chain, which can be arranged to, is added to the received input of institute for corresponding base value
Variable.
Every straightway can indicate a part of the line intersected at base value with x-axis.
Multiple binary multipliers may include at least three binary multipliers.
Mathematical function can be continuous smooth function in predefined scope.
Mathematical function can be the logarithm with 2 bottom of for, and predefined scope can be between 1 and 2.
Mathematical function can be gamma function, and predefined scope can be between zero and one.
At least one logic chain in a plurality of logic chain may include being adapted for carrying out and having the minimum Hamming weight greater than 1
The binary multiplier of the multiplication of the fixed slope of weight.
Machine readable code can be provided, for generating binary logic circuits.It can be provided in thereon to non-transitory
The machine readable storage medium of computer-readable code coding, for generating binary logic circuits.
According to the second aspect of the invention, a kind of method that the hardware for obtaining binary logic circuits indicates is provided, this two
System logic circuit is configured as a series of straightways and approaches mathematical function in predefined scope, this method comprises:
A plurality of straightway is set to be fitted to mathematical function in predefined scope, every straightway all prolongs between a pair of of breakpoint
It stretches and there is the fixed slope in scheduled one group of fixed slope；
Determine the base value for being used for every straightway；And
Obtaining indicates for the hardware of binary logic circuits comprising:
For every straightway in a plurality of straightway:
Binary multiplier, suitable for using h-1 binary adder to execute and the selected fixed slope of straightway
Multiplication, wherein h is the minimum Hamming weight of following item:
The binary representation of fixed slope；
The ternary of fixed slope indicates；And
Two binary numbers of conduct, two trits or the binary number of fixed slope and a ternary
The expression of several products；
Wherein, h-1 binary adder is logically constructed such that with the fixed slope with minimum Hamming weight h
Expression execute multiplication；And
Binary adder, suitable for identified base value to be added to the input or output of binary multiplier；
And
Logic is selected, is suitable for, for the given input variable in predefined scope, being selected more according to identified breakpoint
One in a binary multiplier.
Each fixed slope in scheduled one group of fixed slope may have the minimum Hamming less than or equal to threshold value
Weight h, wherein threshold value determines the limitation for being used to execute the quantity of the adder of multiplication to binary multiplier.
Threshold value can be 2 or 3.
Minimum Hamming weight h can be less than or equal to 3.
This method may further include:
For every straightway in a plurality of straightway, the G-bar between the breakpoint demarcated to straightway is calculated；With
And
The fixed slope closest to G-bar calculated is selected from scheduled one group of fixed slope, the group is fixed oblique
Rate includes being represented as binary representation, ternary expression and as two binary numbers, two trits or one
The slope of the expression of the product of a binary number and a trit.
This method may further include: the sufficient amount of a plurality of straightway of selection so that binary logic circuits with
In basically reaching at least predetermined accuracy in the predefined scope of the value of input variable.
Hardware expression can be RTL, hardware description language or gate level description language.
Hardware description language can be Verilog or VDHL.
Gate level description language can be OASIS or GDSII.
Machine readable code can be provided, the method indicated for realizing the hardware for obtaining binary logic circuits.It can be with
It provides on it to the machine readable storage medium of non-transitory machine readable code coding, for realizing binary logic is obtained
The method that the hardware of circuit indicates.
Data processing equipment can be provided, indicated for generating hardware according to the above method.
The method for indicating manufacture binary logic circuits according to the hardware for using the above method to obtain can also be provided.
Detailed description of the invention
Now with reference to attached drawing, description is of the invention by way of example.In the accompanying drawings:
Fig. 1 is shown in section [1,2] superior function log2(x) curve graph that Michele approaches.
Fig. 2 is the schematic diagram for calculating the binary logic circuits of function approached.
Fig. 3 is shown using a series of straightways through binary logic circuits to function log2(x) the curve approached
Figure.
Fig. 4 is the flow chart for showing the processing for designing binary logic circuits.
Specific embodiment
Illustrate to present by way of example below, so that any person skilled in the art can make and use the present invention.
The present invention is not limited to embodiments described herein, and to a variety of modifications of disclosed embodiment for art technology
It will be apparent from for personnel.
With can supercomputing mathematical function to desired grade accuracy and more efficiently use integration logic electricity
The binary logic of road surface product is beneficial.
Estimation for calculating function in predefined scope is provided.Logic described herein is suitable for approaching a variety of extensively
Function, these functions include but is not limited to logarithm or gamma function.
Fig. 2 shows be configured in the given range of input value x 202 approach mathematical function f as a series of straightways
(x) binary logic circuits.The logic circuit includes logic arrangement, in the example shown comprising three logic chains
213-215, every logic chain correspond to one of the line segment used in approaching.At its output end 211, logic circuit provides use
In the approximation of function f (x).
The binary logic circuits that Fig. 2 is shown in FIG. 3 can be configured to the example approached executed.In the example
In, function f (x) 301 is the function log in x ∈ [1,2] range2(x), but more generally, can be can be by for the function
Any function that a series of line segment of finite slopes approaches.It is approached shown in Fig. 3 including three line segments 303,304 and 305.Choosing
The starting point and ending point for selecting slope, every line segment, so that the curve of line segment approximating function.It can be seen that line segment (303,304
With 305) approach 302 curves for more closely following function than traditional Michele.Due to function log2It (x) is continuous function, institute
By line segment, head and the tail connection is arranged in the form of chain.For discontinuous function, situation be not it is such, the chain of line segment is discontinuously being located
It is interrupted preferably to approach (at hand) function nearby.
In the example depicted in fig. 3, the log for the x between 1 and 22(x) curve is by being chosen to have institute in following table
Three line segments of the slope shown approach:
| Line segment | Slope | Binary system slope | Hamming weight | Intercept |
| 303 | 1.3125 | 1.0101 | 3 | -1.3125 |
| 304 | 1.0625 | 1.0001 | 2 | -1 |
| 305 | 0.8125 | 0.1101 | 3 | -0.625 |
Table 1
Since the binary integer of each slope indicates the low Hamming weight for having for 2 or 3, so these slopes are
Beneficial.By the combination that each slope is rewritten as to 2 power, it is possible to understand that when with binary representation shown in the above table
The simplicity of slope:
1.3125=1+1/4+1/16
1.0625=1+1/16
0.8125=1/2+1/4+1/16=1-1/8-1/16
It should be noted that being the multiplication that the quantity of the item of the binary value of 1 (rather than 0) is operand for binary value
The hard-wired complexity of operation is of great significance.The index of binary value can be expressed as the appropriate number of left/right displacement
The position of amount can be realized by using the appropriate connection in hardware.Logic circuit is not required to execute this left/right and move
Position.
Although when with a series of line segment approximating functions, however, it would be possible to the slope of every line segment of unrestricted choice, starting point
And terminating point, but select slope of the specific fixed value for line segment that ought can realize within hardware shown in Fig. 2 in design
Binary logic circuits when obvious benefit is provided.The slope of every line segment in line segment 303,304 and 305 is all selected as having
There is the binary value of low extension Hamming weight.The extension Hamming weight of binary number occurs from the expression of following binary number
Non-zero symbol minimum number: (a) its normal binary indicate, (b) its ternary indicate (for example, specification position indicate,
In, number can be 0 ,+1 or -1) or (c) its expression as two binary numbers or the multiplication of trit.
N-1 adder/subtracter list is required using the hardware realization of the multiplying of the operand of extension Hamming weight n
Member.To require m-1+n-1 with the multiplication of the product of two binary numbers or trit with extension Hamming weight m and n
A adder/subtracter unit, and it is equivalent to the multiplication with the operand of extension Hamming weight m+n-1.
The example for showing the extension Hamming weight of binary number includes:
The Hamming weight that binary number 1.0001 has for 2, and since normal binary indicates to include indicating type
(a) minimum number of-(c) non-zero symbol, therefore this is also that it extends Hamming weight.
The Hamming weight that binary number 0.1111 has for 4, but it can be in the form of ternary by more effective earth's surface
It is shown as(that is, 1-0.0001) has the Hamming weight for 2.Therefore, the extension Hamming weight of binary number 0.1111
It is 2.
The Hamming weight that binary number 1101001 has for 4, but it can be more effectively expressed as each Hamming
Weight is all the product of 2 two tritsTherefore, the extension Hamming weight of binary number 1101001 is
3。
Single adder/subtracter can be used with the multiplication of the extension Hamming weight binary system for being 2 or trit to exist
It realizes in logic, and two adders/subtract can be used with the multiplication of the extension Hamming weight binary system for being 3 or trit
Musical instruments used in a Buddhist or Taoist mass is logically realized.It also can be used two with the multiplication of extension Hamming weight two binary systems for being 2 or trit
Adder/subtracter is logically realized, therefore is consumed with the multiplication with the extension Hamming weight binary system for being 3 or trit
Identical silicon area.
It is true that slope in each of line segment 303,304 and 305 is selected as the binary value with low extension Hamming weight
Having protected the multiplying with fixed slope can be efficiently implemented within hardware, while still provide to the good of object function
Approach.It can be realized by the multiplication array with h-1 row with the multiplication for extending the fixed slope that Hamming weight is h, often
Row indicates the add operation that operand is shifted to suitable number of position.For low extension Hamming weight, such binary system multiplies
Method array provides compact realization, only consumes the very little area of integrated circuit and provides high-performance.
Multiplier 203-205 in Fig. 2 is configured to (patrolling selected from above-mentioned (a) to (c)) using the expression of fixed slope
Upper execution multiplying is collected, the expression of fixed slope has minimum Hamming weight, and thereby determines that the binary system fixed slope
The extension Hamming weight of value.For example, if being binary value 1101001 for the fixed slope of line segment, within hardware with this
The multiplication of fixed slope is executed using the fixed slope of minimum Hamming weight form, isAnd limit extension
For 2, for the fixed slope, (therefore, in this example, multiplier logic includes two multipliers sequentially to Hamming weight, each
Multiplier is structured to execute the multiplication for the trit for being 2 with Hamming weight).
Have found the line segment that can use the fixed slope with the extension Hamming weight less than or equal to 3 within hardware,
Effectively approaching for broad range of function is provided.In other examples, approaching according to the principle construction instructed herein
The fixed slope of line segment can have the extension Hamming weight less than or equal to 2.In general, the extension Hamming weight of slope is got over
It is low, it realizes more effective with the given multiplication array of the multiplication of the slope.The quantity of line segment can be relative to every line in design
The extension Hamming weight of section balances, to minimize the complexity of hardware.In general, can be changed by using a large amount of line segments
The accuracy approached surely is fed, every line segment all has oblique in one group of slope for being known as having low extension Hamming weight
Rate.Can it is preferable to use with the function it is more acurrate match but its slope have it is biggish extension Hamming weight line segment.This is
Because obtained hardware is approached can want in terms of accuracy and hardware are in the area of speed and consumed integrated circuit
Preferably balance is provided between asking.When integrated circuit will be included in mobile device, the requirement to hardware is especially high, this be because
It may be very limited for silicon area and power consumption.
In Fig. 2, each of multiplier array 203,204 and 205 correspond to Fig. 3 shown in line segment 303,
One of 304 and 305, each multiplier array is structured to defeated in the predefined scope to the range for corresponding to each line segment
Enter Value Operations.Multiplier array can be referred to simply as " multiplier " herein.The model of line segment 303 of the multiplier 203 in Fig. 3
The operation (from 1 to 1.25) in enclosing, multiplier 204 operates (from 1.25 to 1.5) in the range of line segment 304, and multiplier 205
The operation in the range (from 1.5 to 2) of line segment 305.
Every line segment shown in Fig. 3 all forms a part for the line that can be indicated in the form of y=mx+c, wherein y is f
(x) estimated value, m is the fixed slope of line, and c is to extend section of the line segment and y-axis in the case where intersection with y-axis in line segment
Away from.Therefore, given line segment can be limited by four parameters: its slope m, its intercept c and the x for limiting its starting point and ending point
The value value 1,1.25,1.5 and 2 of three line segments (in Fig. 3 constrain).
Can line segment by using fixed slope and corresponding to input value x values of intercept, calculate the given value for x
" mx+c " calculates the estimation of function f (x).Therefore, in order to calculate to the function log for giving x value2(x) approach, first
The value of x is compared with breakpoint (1,1.25,1.5 and 2), to determine which line segment is related to input value x.Then, it selects in Fig. 2
The output being configured to by input value x 202 multiplied by the corresponding multiplier of the fixed slope m of each line segment, for logic electricity
It is used in the output 211 on road.The adder provided in logic chain 213-215 can be used for executing the addition of intercept parameter c.It is existing
It will describe to provide the arrangement for the logic for being used to execute the calculating in Fig. 2.
After receiving the input value x 202 being located in the range of definition between 1 and 2, selecting unit 201 identifies multiplication
Which of device 203-205 provides the appropriate calculating for approaching.This can be by by input value x and the side of line segment that is stored
Dividing value compares, and is formed with to identify which line segment at the given value of x and to be realized to approaching for curve f (x).For example, checking figure
3, consider to have on curve to calculate at the P point for 1.3 x value and f (x) is approached.The value be located at breakpoint 1.25 and 1.5 it
Between Article 2 line segment in the range of, and therefore in this example, the output of second multiplier 204 provides relevant calculation.
In general, every line segment belong to without origin line — that is, have non-zero intercept value c.This can be by multiplying
It, will using adder 210-212 or by being adjusted after multiplier array using adder 207-209 before musical instruments used in a Buddhist or Taoist mass array
The input of multiplier array or output one group of base value of displacement, as shown in Figure 2.Fig. 2 shows before and after multiplier array
Adder, but in some instances, there may be before multiplier array without adder after which, and
In some other examples, there may be after multiplier array without adder before it.Each of after multiplier
Adder could be configured to be used for the fixation intercept parameter c of each line segment and be added.For example, for shown in Fig. 3
Two-lines section, adder 208 can subtract fixed base value 1, be the values of intercept for the line segment provided in the above table 1.
Each adder before multiplier could be configured to that base value is added to x before carrying out multiplication, to realize identical knot
Fruit.This can be understood by rewriteeing the general formula for line as follows:
Therefore, in order to continue example relevant to line segment 304, before multiplier 204 configure adder 211 with will be worth-
The input value x that 1/1.0625=-0.941176 is added to before it is with the multiplication of fixed slope m will realize with multiplier it
The identical result of adder 208 is used afterwards.It will be understood that identical result also may be implemented in other arrangements, it is included in front of multiplier
Utilize adder later, to modify x before its multiplication with fixed slope, and by value be added to the multiplication as a result,
To provide final output 211.
In fact, logic shown in Fig. 2 is generally implemented as, together with selecting unit 201, in logic chain 213-215
Each of its calculating is executed to input value x.Selecting unit 201 can be configured to control multiplexer in such layout
206 only select the output from selected logic chain, for being provided as the approximation of f (x) 211.Selecting unit is together with multiplexer
It indicates selection logic, function is approached for selecting appropriate output valve to be used as.Skill in binary logic circuits design field
Art personnel will expect that other layouts are also possible.
As shown in figure 3, when the slope of this group of line segment 303-305 is limited to the binary value with low extension Hamming weight
When, it may be implemented to function log2(x) close approximation.The value of the breakpoint 306 and 307 of adjacent segments intersection is not too important, and
And line segment and function can be selected to allow most to be closely matched.However, in possible place, if the value of breakpoint is also chosen
It is selected as the binary value with low extension Hamming weight, is advantageous.This can be reduced at selecting unit 201 for determining
Which multiplier is used to give the complexity of the logic of input value x.In Fig. 3, breakpoint 306 and 307 is respectively provided with 1.25 He of value
1.5, correspond to binary value 1.01 and 1.1.
When designing binary logic circuits according to principle described herein, the fixation with low extension Hamming weight is constructed
The line segment of slope, with approximating function nearby.Using required many line segments, to meet the accurate of the desired grade approached
Degree.However, using most in the region changed more slowly in the region that quickly changes of slope of function than the slope in function
The shorter line segment of amount.This leads to the uneven distribution of breakpoint.For example, in the example depicted in fig. 3, two breakpoints appear in x's
In the first half of range, wherein the slope of function log2 (x) most rapidly changes.
As it is known in the art, the ternary of binary number or specification position can be used sometimes to be indicated to realize hardware,
To provide there is the value of lower Hamming weight to use in binary arithmetic operation.For example, having the binary number of the Hamming weight for 4
0.1111 can be expressed as with its canonical formIt indicates binary value 1-0.0001, and corresponds to decimal value
0.9375.The Hamming weight that the canonical form has for 2, and therefore, it can be said that the extension that binary number 0.1111 has for 2
Hamming weight.
It can be indicated using ternary or specification position according to the binary logic of principle configuration described herein.When suitable
When, line segment slope is within hardware so as to being represented as its canonical form.The case where using the canonical form of line segment slope
Under, the extension Hamming weight of line segment slope is the Hamming weight of the line segment slope for its canonical form.
Note that being consolidated according to the binary logic of principle configuration set forth herein using what can effectively be realized within hardware
Determine multiplying.Since the framework that each slope multiplication factor passes through each array is fixed, multiplier battle array is not required
The gradient of column inputs.Furthermore, it is not required that look-up table calculates approaching for function.According to the binary system of principle configuration described herein
Logic provides the high speed solution for the approximating function in the case where not consuming large scale integrated circuit.
It is illustrated by the process of Fig. 4 for designing binary logic circuits (in such as Fig. 2 according to principle described herein
Shown in circuit) processing.Receive require the function approached in some defined ranges of value when 401, selection is appropriate
The line segment of quantity and the breakpoint 402 demarcated to those line segments.The given predefined scope approached and in the range of providing
Function complexity-for example, greater amount of line segment can be used in the region that faster changes of slope of function, this can be with
It is completed by view, to provide approaching for desired accuracy.For simple monotonic function, such as log () curve, two
Item can provide the good approximation for much applying to the somewhere between five straightways.For example, the mistake for passing through repetition test
Journey is searched for using the computerization of the low extension Hamming weight coefficient precalculated based on one group, can choose the number of straightway
Amount and distribution.
It then, will be with the fixed slope extracted from one group of slope value with low extension Hamming weight at 403
The straightway of selected quantity is fitted to function.It describes by way of example now a kind of from one group of slope with low extension Hamming weight
Appropriate gradient method is selected in value.
1, determine breakpoint and in function by the value of the function at the endpoint for the defined range approached.
2, using breakpoint and endpoint value, the G-bar of the curve between adjacent endpoint/breakpoint is calculated (for example, will be in phase
Difference between the value of function at neighboring terminal point/breakpoint is divided by the difference between corresponding x value).
3, it is each pair of adjacent endpoint/breakpoint, selects slope from one group of slope value with low extension Hamming weight, as
The slope of each straightway, selected slope is close to (and preferably as close possible to) G-bar calculated.
Once the slope of straightway is selected, so that it may determine the base value 404-of every line segment for example, straightway and axis
The value of intersection.This can be by the selection straightway one or more reference points fixed in function space about it come real
It is existing.In general, these reference points may be the starting point and/or terminating point of the function in defined range.For example, in Fig. 2,
First line segment 303 is selected as the point x=1 on log function and starts, log (x)=0, and last line segment 305 is selected as
Terminate at point x=2 on log function, log (x)=1 is terminated.Fix these point also just secure with the first line segment and finally
The end to end midium line segment 304 of line segment.Then, every line segment, which can be extrapolated, returns to axis, for example, with determine for
The mode of this description base value used in hardware calculating.
It will be understood that for every straightway, all exist the range for selecting low extension Hamming weight slope value and line segment about
It is the leeway (scope) of fixed reference point.The step 402-404 in Fig. 4 is repeated nearby to determine to the best of function
Approach can be advantageous-for example, select low extension Hamming weight slope and reference point by making small change to breakpoint, with
Obtain the best fit between line segment and function.It is for example, executable such optimization, approaching in limited range is total
Mean square error is reduced to minimum.
This can help to handle the case where its slope monotonically increasing function reduced with the increase of x.For such
Function generally means that every straight line according to the selection that starting point and ending point is located at the slope that the above example on function determines
Section is all located substantially on function slightly lower section.By executing Optimization Steps so that the overall mean square error approached in defined range subtracts
Less to minimum, it can determine that preferably fitting-selects the first slightly higher gradient and slightly lower final gradient for example, passing through sometimes,
So that every line segment all has some parts below curve and the other parts above curve.This can be in the model
Lower mean square error is obtained in enclosing.
Particular example shown in Fig. 3 is more fully described now.It is approached using three line segments 1,1.25,1.5 and 2
Locate the function log with breakpoint and breakpoint2(x)。log2(x) value of the function at those points and the curve in the expression function
G-bar between those of upper point is as shown in table 2.From these G-bars, immediate low extension Hamming weight is selected
Tuple, the slope as each line segment.Therefore, the first line segment as indicated in Fig. 3, between the x value 1 and 1.25 on curve
303 are chosen to have slope 1.3125, and the second line segment 304 between the x value 1.25 and 1.5 on curve is chosen to have
Slope 1.0625, and third line segment 305 between the x value 1.5 and 2 on curve are chosen to have slope 0.8125.
Table 2
When the slope and base value parameter to the given straightway approached of function has been determined, so that it may use every line segment
The minimum extension Hamming weight of fixed slope indicate, obtain the hardware expression by approaching of indicating of straightway.Such hardware
Indicate can according to fig. 2 shown in and example described above define binary logic circuits.Hardware expression, which can be obtained, is
It is required that formed for execute the logic circuit approached hardware element logical expressions, for example, Method at Register Transfer Level (RTL),
Or any other appropriate expression as logic circuit.
As elaboration and design treatment described herein can be realized in software for designing binary logic electricity in Fig. 4
The hardware on road indicates.For example, the processing can be realized in software, the Method at Register Transfer Level (RTL) for integrated design circuit
Definition.Follow principle described herein, such software can provide the faster and more effective hardware in space of binary logic
It realizes, is used for approaching for given function for calculating.
It can be manufactured according to any appropriate manufacturing process according to the binary ciruit that principles above obtains.For example, can be with
The integrated circuit of the form of silicon semiconductor device is fabricated to according to one group of Conventional processing steps, this group of conventional steps may relate to
The deposition of Silicon Wafer is integrated circuit followed by patterning and by chip package.
Note that adder refers to the logic for addition and subtraction.Since the addition of negative is equivalent to subtraction, term
Addition, adder and addition all broadly refer to subtracting for the addition or negative of the addition of positive number or the subtraction of positive number and negative
Method.
The binary logic circuits of Fig. 2 are shown as including multiple functional blocks.This is only illustrative, and is not intended to
Stringent divide is defined between the Different Logic element of integrated circuit.Each functional block can provide in any appropriate manner.
Term software as used herein and computer readable program code include for processor (for example, CPU and/or
GPU executable code), firmware, the programming language code of bytecode, such as C or OpenCL and such as FPGA for can
Reconfigure the module of logical device.Machine readable code includes software and the hardware list for defining integrated circuit in any rank
The code shown, be included in Method at Register Transfer Level (RTL), such as Verilog or VHDL level circuit indicate and such as
The lower level of OASIS and GDSII indicates.
Algorithm described herein and method can be executed by one or more physical processing units so that the unit is held
Row algorithm/method software executes.The or each physical processing unit can be any suitable processor, such as CPU or
GPU (or its kernel) or fixed function or programmable hardware.Software can be stored in machine readable media in the form of nonvolatile
In, such as integrated circuit memory or light or magnetic memory.Machine readable media may include multiple memories, such as on piece
Memory, computer operation memory and non-volatile memory device.
Applicant separately discloses appointing for feature as each individually feature and two or more described herein as a result,
What is combined, and in this sense, such feature or combination can be according to the common knowledges of those skilled in the art, as one
Whole to be implemented based on this specification, whether the combination but regardless of such feature or feature solves disclosed herein any ask
Topic, and do not limit the scope of the claims.Applicant indicate that many aspects of the invention can be by any such independent spy
The structure of sign or feature is constituted.Consider preceding description, a variety of modifications can be made within the scope of the invention, for this field skill
It is obvious for art personnel.
Claims (20)
1. a kind of binary logic circuits, for approaching mathematical function in predefined scope as a series of straightways, every
Straightway all has a slope and corresponding base value in scheduled one group of fixed slope, the binary logic circuits packet
It includes:
Input, for receiving the input variable in the predefined scope；
A plurality of logic chain, every logic chain all include:
Binary multiplier, suitable for use h-1 binary adder execute with it is corresponding one group of fixed slope
The multiplication of one slope, wherein h is the minimum Hamming weight of the following terms:
The binary representation of the fixed slope；
The ternary of the fixed slope indicates；And
Two binary numbers of conduct, two trits or the binary number of the fixed slope and a ternary
The expression of several products；
The h-1 binary adder is logically constructed such that oblique with the fixation with minimum Hamming weight h
The expression of rate executes the multiplication；And
Binary adder, suitable for one be added to base value the outputting and inputting of the binary multiplier；And
Select logic, one be configured in the logic chain according to the Input variable selection, with received defeated for institute
Enter variable and the approximation of the mathematical function is provided.
2. binary logic circuits according to claim 1, wherein each institute in scheduled one group of fixed slope
State fixed slope all and have the corresponding minimum Hamming weight h less than or equal to threshold value, wherein the threshold value is determined to described two
System multiplier is suitable for being used to execute the limitation of the quantity of the adder of multiplication.
3. binary logic circuits according to claim 2, wherein the threshold value is 2 or 3.
4. binary logic circuits according to claim 1, wherein the minimum Hamming weight h is less than or equal to 3.
5. binary logic circuits according to claim 1, the selection logic is configured to by the way that institute is received defeated
Enter variable compared with scheduled one group of break value, to select one in the logic chain, each break value is indicated to one
The value for the input variable that item or more straightway is demarcated.
6. binary logic circuits according to claim 5, the selection logic is configured to determine a pair of adjacent breakpoint
Value, the received input variable of institute are located at this between adjacent break value, and the selection logical response is in the determination, select pair
Ying Yu is located at the logic chain to the straightway between adjacent break value.
7. binary logic circuits according to claim 5 or 6, wherein each break value in one group of break value
It is used in the form of following in the selection logic:
The binary representation of the break value；
The ternary of the break value indicates；Or
Two binary numbers of conduct, two trits or the binary number of the break value and a trit
Product expression；
Form for each break value is that have the expression of the break value of the minimum Hamming weight.
8. binary logic circuits according to claim 7, wherein the institute of each break value in one group of break value
Minimum Hamming weight is stated less than or equal to 3.
9. the binary adder of binary logic circuits according to claim 1, every logic chain is all arranged
At the output that corresponding base value is added to the binary multiplier, and for being expressed as y=f about cartesian axis x and y
(x) mathematical function of form, every straightway all indicate a part of the line intersected at the base value with y-axis.
10. the binary adder of binary logic circuits according to claim 1, every logic chain is all arranged
It is added to the received input variable of institute at by corresponding base value, and for being expressed as y=f (x) shape about cartesian axis x and y
The mathematical function of formula, every straightway all indicate a part of the line intersected at the base value with x-axis.
11. binary logic circuits according to claim 1, wherein the mathematical function is in the predefined scope
It is continuous smooth function.
12. binary logic circuits according to claim 1, wherein at least one logic in a plurality of logic chain
Chain includes: binary multiplier, is adapted for carrying out the multiplication with the fixed slope with the minimum Hamming weight greater than 1.
13. a kind of method that the hardware for obtaining binary logic circuits indicates, the binary logic circuits are configured as
A series of straightways approach mathematical function in predefined scope, the described method comprises the following steps:
A plurality of straightway is fitted to the mathematical function in predefined scope, every straightway all prolongs between a pair of of breakpoint
It stretches and there is the fixed slope in scheduled one group of fixed slope；
Determine the base value for being used for every straightway；And
Obtaining indicates for the hardware of the binary logic circuits comprising:
For every straightway in a plurality of straightway:
Binary multiplier is oblique with the selected fixation of the straightway suitable for using h-1 binary adder to execute
The multiplication of rate, wherein h is the minimum Hamming weight of following item:
The binary representation of the fixed slope；
The ternary of the fixed slope indicates；And
Two binary numbers of conduct, two trits or the binary number of the fixed slope and a ternary
The expression of several products；
Wherein, the h-1 binary adder is logically constructed such that with the described of the minimum Hamming weight h
The expression of fixed slope executes multiplication；And
Binary adder, suitable for identified base value to be added to the input or output of the binary multiplier；
And
Logic is selected, is suitable for, for the given input variable in predefined scope, being selected multiple according to identified breakpoint
One in binary multiplier.
14. according to the method for claim 13, wherein the fixation of each of described scheduled one group of fixed slope is oblique
Rate all has the minimum Hamming weight h less than or equal to threshold value, wherein the threshold value determination is used to the binary multiplier
Execute the limitation of the quantity of the adder of multiplication.
15. according to the method for claim 14, wherein the threshold value is 2 or 3.
16. according to the method for claim 13, wherein the minimum Hamming weight h is less than or equal to 3.
17. method described in any one of 3 to 16, this method further comprise according to claim 1:
For every straightway in a plurality of straightway, the G-bar between the breakpoint demarcated to the straightway is calculated；
And
The fixed slope closest to G-bar calculated is selected from scheduled one group of fixed slope, described one group solid
Determine slope include be represented as binary representation, ternary indicate and for two binary numbers, two trits or
The slope of the expression of the product of one binary number and a trit.
18. method described in any one of 3 to 16, this method further comprise according to claim 1: selecting sufficient amount of institute
A plurality of straightway is stated, so that predefined scope Nei Jibenda of the binary logic circuits in the value for the input variable
To at least predetermined accuracy.
19. method described in any one of 3 to 16 according to claim 1, wherein the hardware expression is RTL, Hardware description language
It makes peace one or more in gate level description language.
20. a kind of for manufacturing two according to the hardware expression for using method described in any one of claim 13 to 19 to obtain
The method of system logic circuit.
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| CN107220025B (en) * | 2017-04-24 | 2020-04-21 | 华为机器有限公司 | Apparatus for processing multiply-add operation and method for processing multiply-add operation |
| CN108984149B (en) * | 2018-08-07 | 2023-03-03 | 电子科技大学 | Approximate 4-2 compressor with high speed and low power consumption |
| GB2580177B (en) * | 2018-12-21 | 2021-03-24 | Imagination Tech Ltd | Iterative estimation hardware |
| TWI698759B (en) | 2019-08-30 | 2020-07-11 | 創鑫智慧股份有限公司 | Curve function device and operation method thereof |
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| US20150317126A1 (en) | 2015-11-05 |
| CN110069239B (en) | 2022-10-11 |
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| GB201712598D0 (en) | 2017-09-20 |
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| US20170364329A1 (en) | 2017-12-21 |
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| US9785406B2 (en) | 2017-10-10 |
| EP2940576B1 (en) | 2022-10-19 |
| EP2940576A2 (en) | 2015-11-04 |
| EP2940576A3 (en) | 2015-12-16 |
| US10402167B2 (en) | 2019-09-03 |
| CN110069239A (en) | 2019-07-30 |
| US10268450B2 (en) | 2019-04-23 |
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