CN105024703A - Short code length LDPC, coder, decoder and coding method based on quasi-cyclic - Google Patents

Abstract

The invention discloses short code length LDPC (Low Density Parity Check), a coder, a decoder and a coding method based on quasi-cyclic. A codon structure is H=[H'1 II P'], wherein H'1 is an information bit matrix, P' is a check bit matrix, and II P' is row transformation of the check bit matrix. The information bit matrix H'1 comprises a plurality of cyclic submatrixes pi, j, and each cyclic submatrix can only be a unit cyclic bias matrix or a zero matrix. According to the technical scheme, a lot of analogue simulations are performed, so as to find an LDPC codon information bit matrix structure which is more suitable for an HSS (horizontal shuffle scheduling) decoding algorithm, and the coder and decoder using LDPC codes, thereby improving LDPC codon performance.

Description

Based on quasi-cyclic short-and-medium code length LDPC and codec and coding method

Technical field

The present invention relates to a kind of LDPC code word and use the encoder of this code word, decoder, corresponding coding method, more particularly, relate to a kind of based on quasi-cyclic short-and-medium code length LDPC and codec and coding method.

Background technology

Low density parity check codewords (Low density Parity Check, LDPC) mainly two classes can be divided into according to its structure, one class is random code word, the most classical surely belongs to MacKay code, and he also has special webpage to provide his various code words (MacKay1999) (Richardson2001) (Luby2001) (Richardson and Urbanke2001); An other class is the code word designed based on algebraic combination structure (Combinatorial).Random code word extraordinaryly can approach shannon limit, but due to ' 1 ' randomness distributed, cause the design of the design of encoder and decoder not have parallel or regular feasible, so be not suitable for needs to possess certain throughput systems, be not therefore also just widely used.

And the problem of this respect is well solved based on the appearance of the code word of algebraic combination structure, this wherein, a class is had to have good performance (Y.Kou and S.Lin2001) based on the code word that finite field (Finite Geometry) designs, but the shortcoming of this kind of code word is due to its H matrix density higher (large row is rearranged heavy), so when using the class algorithm based on belief propagation, complexity is very high.And another kind of quasi-cyclic code word (Quasi-cyclicLDPC, QC-LDPC) to be a class very important based on the code word of algebraic combination structure.The main structure of QC-LDPC code word is based on quasi-cyclic unit submatrix.(J.L.Fan2000) (R.M.Tanner2001) (R.M.Tanner2001) (T.Okamura2003) (R.M.Tanner2004) this quasi-cyclic unit submatrix structure is applicable to the hardware realizing parallel work-flow very much, such as realizes the decoder of the large and then high-throughput of degree of parallelism.Although traditional this QC-LDPC code word is applicable to degree of parallelism, high decoder realizes, improve throughput, but the generator matrix being obtained QC structure by reverse method may not be sparse, even if or it is sparse, it is encoded with generator matrix, and to obtain check bit be not obvious, will by asking system of linear equations to obtain, the encoder of therefore traditional QC-LDPC code word or relative complex.In order to address this problem, structurized repeat accumulated code (the Structured Irregular Repeat Accumulator code that first scholar Zhang and Ryan propose, S-IRA) LDPC code word (Zhang and Ryan2006), this structure, while the realization being applicable to high parallel decoder, can complete coding with the method for unusual simple and effective.This kind of codeword structure has following features, and the matrix part corresponding to information bit is made up of standard circulation submatrix, and the matrix part corresponding to check bit is made up of bidiagonal matrix.

Current S-IRA code word has been widely used in each large communication standard, mainly comprises, European second generation digital broadcast television transmission standard DVB series (ETSI, 2006, DVBT22009, DVB-C22009, DVB-NGH2012); IEEE802.11n WLAN standard (IEEE802.11n2009); IEEE802.11e wireless wide area network standard (IEEE802.16e2006); China Digital TV ground transmission standard (DTTB) (GB20600-2006); Mobile Multimedia Broadcasting (CMMB2006); The near-earth deep space communication system (CCSDS2007) of North America CCSDS; And the standard of some disk storage devices etc.From the developing state of whole international coverage digital communicating field, also have more standard and or in the future use LDPC code word.

From the standard submitted at present, particularly commercial extremely successful DVBT2, DVBS2 standard, and just fix standard recently and the commercial DVB-NGH standard (end of the year 2012 finalized a text) having bright prospects, the structure that its check matrix corresponding to S-IRA code word used mainly uses is as follows:

H＝[ΠH ₁P]

Wherein H ₁be the matrix part that information bit is corresponding, Π is to H ₁the line translation of certain form, and the P matrix part that to be check bit corresponding.

And:

By L × J the circulation submatrix of size or 0 matrix composition.

Such as, P _i,jthe first structure as follows:

now, P _i,jbe made up of two unit offset battle arrays.Further, P _i,jcan also be made up of N number of unit circle matrix, the integer of N > 2.

P _i,jthe second structure as follows:

at this time P _i,jbe made up of full null matrix.

Due to P _i,jcan be made up of more than one unit circle battle array, cause it and be not suitable for the hardware implementation of HSS (Horizontal shuffle scheduling) decoding algorithm.Have in the document of the implementation method of DVBT2 and S2 about this and be much mentioned to, and propose the solution of relevant sacrifice complexity.

And the P matrix part that to be check bit corresponding, it is following bidiagonal matrix:

Summary of the invention

Object of the present invention aims to provide a kind of based on quasi-cyclic short-and-medium code length LDPC and codec and coding method, and what the structure solving the check matrix of S-IRA LDPC code common in prior art was brought is not suitable for HSS (Horizontal shuffle scheduling) decoding algorithm, affects the problem of whole LDPC code word performance.

Namely this patent proposes a kind of P _i,jonly has the structure of 0 or 1 unit circle matrix composition.Under the condition of retention, be applicable to HSS decoding.A kind of code word of design parameter is proposed simultaneously, and code table, and propose corresponding encoding method encodes device, interpretation method and decoder.

According to above-mentioned purpose, implement a kind of S-IRA LDPC code word for codec of the present invention, the structure of its code word is: H=[H ' ₁Π P '], H ₁' be information bit matrix, P ' is check bit matrix, and Π P ' does line translation to check bit matrix.Wherein, information bit matrix H ₁' comprise multiple circulation submatrix p _i,j, each circulation submatrix can only be unit circle excursion matrix or full null matrix.

According to above-mentioned purpose, implement a kind of LDPC encoder of the present invention, it adopts a kind of LDPC code word of S-IRA structure, and the structure of S-IRA LDPC code word is: H=[H ' ₁Π P '], H ₁' be information bit matrix, P ' is check bit matrix, and Π P ' does line translation to check bit matrix.Wherein, information bit matrix H ₁' comprise multiple circulation submatrix p _i,j, each circulation submatrix can only be unit circle excursion matrix or full null matrix.

According to above-mentioned purpose, implement a kind of LDPC decoder of the present invention, it adopts a kind of LDPC code word of S-IRA structure, and the structure of S-IRA LDPC code word is: H=[H ' ₁Π P '], H ₁' be information bit matrix, P ' is check bit matrix, and Π P ' does line translation to check bit matrix.Wherein, information bit matrix H ₁' comprise multiple circulation submatrix p _i,j, each circulation submatrix can only be unit circle excursion matrix or full null matrix.

According to above-mentioned principal character, the information bit matrix of inventive encoder, decoder and S-IRA LDPC code word be wherein m capable × matrix of n-m row:

wherein each circulation submatrix p _i,jsize be

According to above-mentioned principal character, the check bit matrix P ' of inventive encoder, decoder and S-IRA LDPC code word wherein for m capable × matrix of m row: its leading diagonal and minor diagonal are 1, and all the other positions are 0.

According to above-mentioned purpose, the coding method implementing S-IRA LDPC code word of the present invention comprises the following steps:

Obtain information bit { i ₀, i ₁, i ₂, i ₃, i ₄, i ₅..., i _n-m-1;

Initiation verification bit p ₀=0, p ₁=0, p ₂=0, p ₃=0, p ₄=0 ..., p _m-1=0;

By each check bit p _iand coupled information bit does mould 2 He, i=0,1,2 ... m-1, and rearrange, obtain the check bit sequence after resetting ${\stackrel{\→}{p}}^{\′}=\{p_0^{\′},p_1^{\′},p_2^{\′},...,p_{m-1}^{\′}\};$

By the check bit sequence after rearrangement do following cumulative:

p′ ₀＝p′ ₀

${p^{\′}}_1={p^{\′}}_1\⊕{p^{\′}}_0$

${p^{\′}}_{k-1}={p^{\′}}_{k-1}\⊕{p^{\′}}_{k-2}.$

${p^{\′}}_k={p^{\′}}_k\⊕{p^{\′}}_{k-1}$

${p^{\′}}_{k+1}={p^{\′}}_{k+1}\⊕{p^{\′}}_k$

${p^{\′}}_{m-1}={p^{\′}}_{m-1}\⊕{p^{\′}}_{m-2}$

According to above-mentioned purpose, implement LDPC coding method of the present invention and encoder, the encoding operation module that wherein encoder is built-in have employed the coding method of described LDPC, and it comprises:

Computation of parity bits wherein, j=0,1,2,3 ..., m-1; represent in low-density parity check (LDPC) matrix with p _jassociated information bit; y _jit is information bit sequence number, obtain according to following formula:

Wherein, q=24, m=192 (for code length n=1920) or m=576 (for code length n=5760), x represent the address participating in the information bit that Parity Check Bits adds up, and the code table of x is the code table of following two different code lengths:

Code table 1: code check 9/10m=192, code length n=1920

Code table 2: code check 9/10m=576, code length n=5760

Have employed technical scheme of the present invention, by a large amount of analogue simulation, have found the information bit matrix structure of a kind of S-IRALDPC code word being more suitable for HSS (Horizontal shuffle scheduling) decoding algorithm than prior art, and use encoder, the decoder of this S-IRA LDPC code, thus create the lifting in beyond thought S-IRALDPC codeword performance.

Embodiment

Technical scheme of the present invention is further illustrated below in conjunction with drawings and Examples.

HSS (Horizontal Shuffle Scheduling) algorithm is compared to the difference of flood (Flooding) algorithm, Flooding algorithm be must wait until that all line operates are complete after, the data obtained are disposable to be upgraded, then use in next iteration and go, and in HSS algorithm in certain iteration, the result obtained after every operation line by line can upgrade immediately, use and still go in the upper once line operate of current iteration, greatly can improve the convergence rate of decoding algorithm like this.On the other hand, HSS algorithm only needs to preserve n (n is code length) Soft Inform ation data, and the result soft value information of m × 2 (m is the line number of check matrix) line operate, compared to Flooding algorithm, save very many chip areas.

But existing HSS algorithm is when selecting circulation sub-block, and circulation sub-block usual Bu Shi unit sub-block, but two or more unit sub-block, this certainly will cause the conflict of internal storage access in the process of parallel work-flow.If this is because circulation sub-block is made up of plural unit sub-block, so when circulation sub-block operates at parallel-by-bit time, the line operate input having two row requires to read same internal memory simultaneously, and writes same internal memory after having operated simultaneously.This had not both reached the original intention of HSS algorithm, can cause internal storage conflict yet.

Therefore, based on the shortcoming of LDPC code word structure in existing standard, specifically, that circulation submatrix in information bit matrix may by being made up of the problem causing being not suitable for HSS decoding algorithm and realize multiple circulating unit battle array, the present invention proposes a kind of structure of new S-IRA LDPC code word, and the structure of its check matrix is as follows:

H＝[H′ ₁ΠP′]

Wherein, H ₁' be information bit matrix, P ' is check bit matrix, and Π P ' is the line translation to certain form that check bit matrix P ' does.

Information bit matrix H ₁' be m capable × matrix of n-m row, its concrete structure is as follows:

In the present invention, information bit matrix H ₁' comprise multiple circulation submatrix p _i,j, H ₁' in each circulation submatrix p _i,jsize be each circulation submatrix can only be unit circle excursion matrix or full null matrix, i.e. H here ₁' be by L × J the unit circle excursion matrix of size or 0 matrix are formed.Here unit circle excursion matrix refers to and is obtained by the skew to the right that circulates of onesize unit matrix.

According to above-mentioned p _i,jthe restriction of structure can obtain, circulation submatrix p of the present invention _i,jmay be only the version that the following two kinds is concrete:

now p _i,jbe made up of unit circle excursion matrix.

2) now p _i,jbe made up of full null matrix.

On the other hand, in order to mating information bit matrix H ₁' structure, check bit matrix P ' of the present invention be m capable × matrix of m row, its concrete structure is as follows:

As can be seen from said structure, check bit matrix P ' is a kind of special dual-diagonal matrix, and its main diagonal angle is all ' 1 ', minor diagonal is also ' 1 ', the remainder position of each row, column is ' 0 '.

The present invention also discloses a kind of LDPC encoder in addition, and what it adopted is exactly above-mentioned S-IRALDPC code word, and specifically, the concrete structure of its check matrix is:

H=[H ' ₁Π P '], wherein, H ₁' be information bit matrix, P ' is check bit matrix, and Π P ' does line translation to check bit matrix.Especially, information bit matrix H ₁' comprise multiple circulation submatrix p _i,j, each circulation submatrix can only be unit circle excursion matrix or full null matrix.

The present invention also discloses a kind of LDPC decoder in addition, and what it adopted is exactly above-mentioned S-IRALDPC code word, and specifically, the concrete structure of its check matrix is:

H=[H ' ₁Π P '], wherein, H ₁' be information bit matrix, P ' is check bit matrix, and Π P ' does line translation to check bit matrix.Especially, information bit matrix H ₁' comprise multiple circulation submatrix p _i,j, each circulation submatrix can only be unit circle excursion matrix or full null matrix.

Because encoder of the present invention all adopts above-mentioned disclosed LDPC code word, therefore other details characteristics of its LDPC code word are open in the above specification, no longer repeat specification here.

In addition, the invention also discloses the coding method of above-mentioned LDPC code word, its key step is as follows:

Step S1: obtain information bit, arranging known information bit is { i ₀, i ₁, i ₂, i ₃, i ₄, i ₅..., i _n-m-1, namely so-called coding utilizes check matrix H to obtain check bit:

$\stackrel{\→}{p}=\{p_0,p_1,p_2,p_3,p_4,p_5,...,p_{m-1}\}$

Step S2: initiation verification bit p ₀=0, p ₁=0, p ₂=0, p ₃=0, p ₄=0 ..., p _m-1=0;

Step S3: by each check bit p _iand coupled information bit does mould 2 He, wherein i=0,1,2 ... m-1.Afterwards, by above-mentioned mould 2 and check bit p afterwards _irearrange:

p _iQ'＝p _i；p _iQ+1'＝p _i+q；p _iQ+2'＝p _i+2q；p _iQ+3'＝p _i+3q；

p _iQ+4'＝p _i+4q,...,p _iQ+Q-1'＝p _i+(Q-1)q；

Wherein i=0,1,2,3 ..., q-1 and wherein

Thus, the check bit sequence after resetting is obtained

Step S4: by the check bit sequence after rearrangement do following cumulative:

p′ ₀＝p′ ₀

${p^{\′}}_1={p^{\′}}_1\⊕{p^{\′}}_0$

${p^{\′}}_{k-1}={p^{\′}}_{k-1}\⊕{p^{\′}}_{k-2}.$

${p^{\′}}_k={p^{\′}}_k\⊕{p^{\′}}_{k-1}$

${p^{\′}}_{k+1}={p^{\′}}_{k+1}\⊕{p^{\′}}_k$

${p^{\′}}_{m-1}={p^{\′}}_{m-1}\⊕{p^{\′}}_{m-2}$

Finally obtain check bit sequence:

$\stackrel{\→}{p}=\{p_0,p_1,p_2,p_3,p_4,p_5,...,p_{m-1}\}.$

Visible by the technical scheme disclosed in specification of the present invention, the feature of S-IRALDPC code word of the present invention is that circulation submatrix in its information bit matrix is except the structure of 0 matrix, only may be made up of unit circle excursion matrix, it is technical characteristic based on circulation sub-block that the selection of this circulation submatrix has adapted to the parallel computation of HSS algorithm, therefore when circulation sub-block operates at parallel-by-bit time, the line operate input that there are not two row requires to read same internal memory simultaneously, do not exist after having operated and write same content simultaneously yet, internal storage conflict can be avoided like this.

The S-IRALDPC code formed according to information bit matrix of the present invention and check bit matrix, the encoder of application LDPC code of the present invention, decoder can have preferably codeword performance in HSS algorithm.

In addition, the present invention also discloses the corresponding coding method of a kind of and above-mentioned S-IRA LDPC code word and encoder, and can corresponding said structure.Encoder is built-in with encoding operation module, and encoding operation module have employed following LDPC coding method:

In encoding operation module,

Computation of parity bits wherein, j=0,1,2,3 ..., m-1; represent in low-density parity check (LDPC) matrix with p _jassociated information bit; y _jit is information bit sequence number, obtain according to following formula:

Wherein, q=24, m=192 (for code length n=1920) or m=576 (for code length n=5760), x represent the address participating in the information bit that Parity Check Bits adds up, and the code table of x is the code table of following two different code lengths:

Code table 1: code check 9/10m=192, code length n=1920

Code table 2: code check 9/10m=576, code length n=5760

Specifically, the code word of LDPC is made to be:

C=(i ₀, i ₁..., i _j..., i _k-1, p ₀, p ₁..., p _m-1); Wherein, (i ₀, i ₁..., i _n-m-1) be information bit bit, be known { 1,0} sequence.(p ₀, p ₁, p ₂..., p _m-1) be check bit, be bit to be calculated.

First each check bit described in initialization corresponding to check part,

I.e. p ₀=0, p ₁=0, p ₂=0, p ₃=0, p ₄=0, p ₅=0 ..., p _m-1=0, wherein each p _irepresent a line in check matrix, such as p _mthe m represented in check matrix is capable.

Check bit is one group according to q bit carry out dividing into groups to obtain multiple check bit group.

Particularly, first, arranging described check bit is:

{p ₀,p ₁,p ₂,p ₃,p ₄,p ₅,...,p _m-1}。Then, described check bit is one group with q bit in order to carry out dividing into groups to obtain multiple check bit group.

Such as, check bit group is:

{ p _jq+0, p _jq+1..., p _{jq+ (q-1)}, wherein, j value be (0,1,2 ..., Q-1), wherein $Q=\frac{m}{q}.$

Secondly, the check bit in each check bit group and its information bit associated in low-density parity check (LDPC) matrix are carried out accumulation process.

Particularly, to q bit p in each check bit group _mmake following XOR:

wherein, j=0,1,2,3 ..., m-1; represent in low-density parity check (LDPC) matrix with p _jassociated information bit; y _jit is information bit sequence number, obtain according to following formula:

Wherein, q=24, m=192 (for code length n=1920) or m=576 (for code length n=5760), x represent the address participating in the information bit that Parity Check Bits adds up

X represents that in each check bit group, first check bit (can be such as p ₀, p _q+0, p _2q+0..., p _jq+0...) and representated by described low-density parity check (LDPC) matrix in row the (the corresponding 0th, q, 2q, 3q ..., jq ... the OK) position of inner " 1 " column, but do not comprise the position of the row of " 1 " in described low-density parity check (LDPC) matrix in check part.

For the code word of code table 1, q=24, check bit number m=192, information bit n-m=1728.

The first row numeral in code table 1:

5 115 143 209 220 252 287 331 388 490 650 755 785 819 892 974 1072 11031112 1211 1292 1298 1334 1444 1481 1510 1525 1554 1580 1605 1620 1652

The first row (corresponding first check bit p in each digitized representation low-density parity check (LDPC) matrix ₀) in the position (position namely arranged) of " 1 ", but this position does not comprise the position of the row of " 1 " of the check part of low-density parity check (LDPC) matrix.

The numeral of this row is x in addition, represents first bit p in first check bit block ₀the position (position namely arranged, row start counting with 0 equally) of " 1 " of the 0th row in representative check matrix.

So have:

$p_0=p_0\⊕i_5\⊕i_{115}\⊕i_{143}\⊕i_{209}\⊕i_{220}\⊕i_{252}\⊕i_{287}\⊕i_{331}\⊕......\⊕i_{1605}\⊕i_{1620}\⊕i_{1652}$ Then, then according to formula have:

$p_1=p_1\⊕i_6\⊕i_{116}\⊕i_{144}\⊕i_{210}\⊕i_{221}\⊕i_{253}\⊕i_{288}\⊕i_{332}\⊕......\⊕i_{1606}\⊕i_{1621}\⊕i_{1653}$

$p_{23}=p_{23}\⊕i_4\⊕i_{114}\⊕i_{142}\⊕i_{208}\⊕i_{219}\⊕i_{251}\⊕i_{286}\⊕i_{330}\⊕......\⊕i_{1604}\⊕i_{1619}\⊕i_{1651}$ For other row according to above-mentioned formula, do not enumerate at this.

Afterwards interleaving treatment is done to each check bit after cumulative.

Particularly, comprising: make interleaving treatment to each check bit after cumulative according to permutation format, wherein said permutation format is realized by following formula:

p _iQ'＝p _i；p _iQ+1'＝p _i+q；p _iQ+2'＝p _i+2q；p _iQ+3'＝p _i+3q；

p _iQ+4'＝p _i+4q,...,p _iQ+Q-1'＝p _i+(Q-1)q；

Wherein, i=0,1,2,3 ..., q-1.

Such as,

p ₀'＝p ₀；p ₁'＝p _0+q；p ₂'＝p _0+2q；p ₃'＝p _0+3q；

p ₄'＝p _0+4q,...,p _Q-1'＝p _0+(Q-1)q；

p _Q'＝p ₁；p _Q+1'＝p _1+q；p _Q+2'＝p _1+2q；p _Q+3'＝p _1+3q；

p _Q+4'＝p _1+4q,...,p _2Q-1'＝p _1+(Q-1)q；

.

.

.

p _(q-1)Q'＝p _q-1；p _(q-1)Q+1'＝p _(q-1)+q；p _(q-1)Q+2'＝p _(q-1)+2q；

p _(q-1)Q+3'＝p _(q-1)+3q；

p _(q-1)Q+4'＝p _(q-1)+4q,...,p _(q-1)Q+Q-1'＝p _(q-1)+(Q-1)q；

Wherein, $Q=\frac{m}{q}.$

In the present embodiment, { p ₀, p ₁, p ₂, p ₃, p ₄, p ₅..., p _m-1represent the check bit before interweaving;

{ p ₀', p ₁', p ₂', p ₃', p ₄', p ₅' ..., p _m-1' represent the check bit after interweaving.

Finally each check bit after interleaving treatment is carried out mould 2 and add computing to obtain final check bit.

Particularly, this step is realized by following formula:

p′ ₀＝p′ ₀

${p^{\′}}_1={p^{\′}}_1\⊕{p^{\′}}_0$

${p^{\′}}_{k-1}={p^{\′}}_{k-1}\⊕{p^{\′}}_{k-2}.$

${p^{\′}}_k={p^{\′}}_k\⊕{p^{\′}}_{k-1}$

${p^{\′}}_{k+1}={p^{\′}}_{k+1}\⊕{p^{\′}}_k$

${p^{\′}}_{m-1}={p^{\′}}_{m-1}\⊕{p^{\′}}_{m-2}$

(the p obtained ₀', p ₁' ... p _m-1') be the check bit after finally encoding, the LDPC code c=(i finally obtained ₀, i ₁..., i _j..., i _n-m-1, p ₀', p ₁' ..., p _m-1').

The problem of LDPC code for internal storage conflict during HSS algorithm is solved by sacrificing complexity in prior art, S-IRA LDPC code of the present invention, use the selection of the information bit matrix in the encoder of S-IRA LDPC code, decoder design can produce beyond thought technique effect, from codeword structure originally with it, significantly reduce the complexity of HSS algorithm, solve the technical barrier existed in above-mentioned prior art.

It will be understood to one skilled in the art that, above specification is only one or more execution modes in the numerous embodiment of the present invention, and not uses limitation of the invention.Any equalization for the above embodiment changes, modification and the equivalent technical scheme such as to substitute, as long as spirit according to the invention, all will drop in scope that claims of the present invention protect.

Claims (8)

1. a LDPC code word for S-IRA structure, is characterized in that, the structure of described LDPC code word is:

H=[H ' ₁Π P '], wherein H ₁' be information bit matrix, P ' is check bit matrix, and Π P ' does line translation to described check bit matrix, wherein:

Described information bit matrix H ₁' comprise multiple circulation submatrix p _i,j, the submatrix that circulates described in each can only be unit circle excursion matrix or full null matrix.

2. the LDPC code word of a kind of S-IRA structure as claimed in claim 1, is characterized in that, described information bit matrix be m capable × n-m row matrix:

wherein each circulation submatrix p _i,jsize be

3. the LDPC code word of a kind of S-IRA structure as claimed in claim 1, is characterized in that, described check bit matrix P ' for m capable × m row matrix:

it is 0 that its leading diagonal and minor diagonal are 1 all the other positions.

4. a LDPC encoder, described LDPC encoder adopts the LDPC code word of S-IRA structure as claimed any one in claims 1 to 3.

5. a LDPC decoder, described LDPC decoder adopts the LDPC code word of S-IRA structure as claimed any one in claims 1 to 3.

6. a coding method for the LDPC code word of S-IRA structure as claimed in claim 1, is characterized in that, comprise the following steps:

Obtain information bit { i ₀, i ₁, i ₂, i ₃, i ₄, i ₅..., i _n-m-1;

Initiation verification bit p ₀=0, p ₁=0, p ₂=0, p ₃=0 ..., p _m-1=0;

By each check bit p _iand coupled information bit does mould 2 He, i=0,1,2 ... m-1, and do and rearrange as follows,

p _iQ'＝p _i；p _iQ+1'＝p _i+q；p _iQ+2'＝p _i+2q；p _iQ+3'＝p _i+3q；

p _iQ+4'＝p _i+4q,...,p _iQ+Q-1'＝p _i+(Q-1) _q；

Wherein i=0,1,2,3 ..., q-1 and wherein

Obtain the check bit sequence after resetting

By the check bit sequence after described rearrangement do following cumulative:

p′ ₀＝p′ ₀

。

7. a coding method for LDPC code, is characterized in that, comprises the following steps:

Computation of parity bits wherein, j=0,1,2,3 ..., m-1; represent in low-density parity check (LDPC) matrix with p _jassociated information bit; y _jit is information bit sequence number, obtain according to following formula:

Wherein, q=24, m=192 (for code length n=1920) or m=576 (for code length n=5760), x represent the address participating in the information bit that Parity Check Bits adds up, and the code table of x is the code table of following two different code lengths:

Code table 1: code check 9/10m=192, code length n=1920

Code table 2: code check 9/10m=576, code length n=5760

。

8. a LDPC encoder, is characterized in that, described encoder comprises:

Encoding operation module, in order to computation of parity bits wherein, represent in low-density parity check (LDPC) matrix with p _jassociated information bit; y _jit is information bit sequence number, obtain according to following formula:

Wherein, q=24, m=192 (for code length n=1920) or m=576 (for code length n=5760), x represent the address participating in the information bit that Parity Check Bits adds up, and the code table of x is the code table of following two different code lengths:

Code table 1: code check 9/10m=192, code length n=1920

Code table 2: code check 9/10m=576, code length n=5760

。