CN105019770A - Remote tracking control type safety box - Google Patents

Abstract

The invention discloses a remote tracking control type safety box. The remote tracking control type safety box comprises a control center, a safety box body, an electromagnetic lock, a smoke alarm, a sound alarm, a fall handle, a high-voltage defibrillator, a master control board and a sub control board. The electromagnetic lock, the smoke alarm, the sound alarm, the fall handle and the high-voltage defibrillator are arranged on the safety box body. The master control board and the sub control board are arranged in the safety box body. The master control board and the sub control board are each provided with a DC-DC/LDO power conversion structure. The master control board is connected with a 7.4 V charge and discharge management structure through the corresponding DC-DC/LDO power conversion structure. The sub control board is connected with a 12 V charge and discharge management structure through the corresponding DC-DC/LDO power conversion structure. The remote tracking control type safety box has more protection measures and more accurate positioning and locking capacity; meanwhile, the remote tracking control type safety box is opened through remote control, so that the box opening difficulty of criminals is further increased, and the use safety of the remote tracking control type safety box is better guaranteed.

Description

Remote tracing controls formula safety box

Technical field

The invention belongs to security fields, particularly a kind of remote tracing that can realize remote tracing and control controls formula safety box.

Background technology

Ministry of Public Security GA746-2008 standard has corresponding standard to define to the cash drawing box used for finance, security service industry, enterprise, public institution's cash drawing box, fortune paper money, and present situation is escorted in the arms that A, B, C level protection cash drawing box that this standard defines can meet China substantially.But it still exists following shortcoming: 1, alarm form is single, only have audible alarm a kind of; 2, not rechargeable battery, electric power that is sufficient, that continue not only can not be provided to carry out reporting to the police and switch-box operation, and its battery altering is comparatively complicated; 3, without intelligent processing capacity; 4, lack active protecting device, after cash drawing box is obtained by offender, can be taken away easily by offender and destroy; 5, can not locate in real time, even if use the C level protection cash drawing box of band positioning function, still cannot grasp the real-time status in cash drawing box transportation; 6, the circuit of uncontrollable cash drawing box transport; 7, adopt mechanical key, be easy to be opened; 8, authentication is simple, and major part is just locked by mechanical key, and the cash drawing box of part C level protection also has nfc card, but still cannot guarantee its safety.

In sum, the cash drawing box that current people make still can not meet the secondary demand of people's modern tall, and its security performance still awaits improving.

Summary of the invention

The object of the invention is to overcome above-mentioned defect, provide a kind of remote tracing with more preventive means and precise positioning and lock function to control formula safety box.

To achieve these goals, the present invention realizes by the following technical solutions:

Remote tracing controls formula safety box, comprise control centre, safety box main body, be arranged on the electromagnetic lock in safety box main body, smoke alarm, voice guard, come off handle and high-voltage electric shock device, and be arranged on the master board be connected by UART bus of safety body interior and sub-control panel; Master board and sub-control panel are respectively arranged with a DC-DC/LDO Power convert structure, master board has 7.4V management of charging and discharging structure by DC-DC/LDO Power convert anatomical connectivity, and sub-control panel has 12V management of charging and discharging structure by DC-DC/LDO Power convert anatomical connectivity; Described master board comprises main control singlechip, respectively by NFC circuit, GPS/BD circuit, 3G/GPRS circuit, fingerprint detection circuit and RF remote control circuit that UART bus is connected with this main control singlechip, the SD memory circuit be connected with main control singlechip by spi bus and OLED screen circuit, and by gyroscope block that iic bus is connected with main control singlechip; Described sub-control panel comprises son control single-chip microcomputer, and the SD memory circuit, NFC circuit, gyroscope block, GPS/BD circuit, 3G/GPRS circuit and the fingerprint detection circuit that are connected on this son control single-chip microcomputer, described son control single-chip microcomputer is connected respectively by different power on-off control circuits and electromagnetic lock, smoke alarm, voice guard, come off handle and high-voltage electric shock device; Master board is controlled single-chip microcomputer with son and is connected by UART bus; Be provided with DC-DC/LDO power-switching circuit in DC-DC/LDO Power convert structure, in 12V management of charging and discharging structure, be provided with 12V management of charging and discharging circuit; 3G/GPRS circuit is made up of 3G circuit and GPRS circuit again.

Further, above-mentioned 12V management of charging and discharging circuit is by management of charging and discharging chip U1, connector P1, metal-oxide-semiconductor Q2, metal-oxide-semiconductor Q3, metal-oxide-semiconductor Q4, metal-oxide-semiconductor Q5, one end is connected with the drain electrode of metal-oxide-semiconductor Q3, the resistance R8 of other end ground connection after electric capacity C6, the resistance R9 in parallel with resistance R8, one end is connected with the drain electrode of metal-oxide-semiconductor Q3, the resistance R10 of other end ground connection after resistance R17, the electric capacity C13 in parallel with resistance R17, be serially connected in the electric capacity C7 between the drain electrode of metal-oxide-semiconductor Q3 and grid, be serially connected in the electric capacity C4 between the grid of metal-oxide-semiconductor Q3 and source electrode, the resistance R11 in parallel with electric capacity C4, one of them P pole is connected with the drain electrode of metal-oxide-semiconductor, the VBAT pin that single-chip microcomputer is controlled with son in another P pole is connected, the Zener diode group D2 that two N are extremely all connected with the AVCC pin of management of charging and discharging chip U1 after resistance R28, one end is connected with the grid of metal-oxide-semiconductor Q3, the resistance R15 that the other end is connected with the ACDRV pin of management of charging and discharging chip U1, one end is connected with the source electrode of metal-oxide-semiconductor Q3, the resistance R16 that the other end is connected with the CMSRC pin of management of charging and discharging chip U1, one end is connected with the drain electrode of metal-oxide-semiconductor Q2, the electric capacity C8 that the other end is connected with the AVCC of management of charging and discharging chip U1 after electric capacity C17, one end is connected with the drain electrode of metal-oxide-semiconductor Q2, the resistance R5 that the other end is connected with the CAN pin of management of charging and discharging chip U1 after resistance R12, be serially connected in the electric capacity C5 between the ACP pin of management of charging and discharging chip U1 and CAN pin, N pole is connected with two SW pins of management of charging and discharging chip U1, the Zener diode D1 that P pole is connected with the tie point of resistance R12 with resistance R5 after electric capacity C2, the polar capacitor C1 in parallel with electric capacity C2, positive pole is connected with the source electrode of metal-oxide-semiconductor Q4, the electric capacity C3 of minus earth, one end is connected with the SW pin of management of charging and discharging chip U1, the inductance L 1 that the other end is connected with the drain electrode of metal-oxide-semiconductor Q4 after resistance R21, one end is connected with the SW pin of management of charging and discharging chip U1, the electric capacity C14 that the other end is connected with the BTST pin of management of charging and discharging chip U1 after resistance R27, one end is connected with the REGN pin of management of charging and discharging chip U1, the electric capacity C19 of other end ground connection, one end ground connection, the electric capacity C16 that one end is connected with the SRP pin of management of charging and discharging chip U1, be serially connected in the electric capacity C18 between the SRP pin of management of charging and discharging chip U1 and SRN pin, one end is connected with the SRN pin of management of charging and discharging chip U1, the resistance R23 that the other end is connected with the drain electrode of metal-oxide-semiconductor Q4, one end is connected with the drain electrode of metal-oxide-semiconductor Q4, the polar capacitor C9 of other end ground connection, polar capacitor C10 in parallel with polar capacitor C9 respectively and electric capacity C11, one end is connected with the grid of metal-oxide-semiconductor Q4, the resistance R7 of other end ground connection, one end is connected with the grid of metal-oxide-semiconductor Q4, the resistance R13 that the other end is connected with the BATDRV pin of management of charging and discharging chip U1, one end is connected with the drain electrode of metal-oxide-semiconductor Q4, the electric capacity C12 of other end ground connection, one end is connected with the grid of metal-oxide-semiconductor Q4, the other end is in turn through resistance R24, the resistance R22 of ground connection after R29, the electric capacity C15 in parallel with resistance R24, one end is connected with the NTC pin of connector P1, the resistance R30 that the other end is connected with the VREF pin of management of charging and discharging chip U1, one end is connected with the NTC pin of connector P1, the resistance R32 of other end ground connection, one end is connected with the NTC pin of connector P1, the resistance R31 that the other end is connected with the TS pin of management of charging and discharging chip U1, one end is connected with the TTC pin of management of charging and discharging chip U1, the electric capacity C21 of other end ground connection, one end is connected with the VREF pin of management of charging and discharging chip U1, the electric capacity C20 that the other end is connected with the earth terminal of electric capacity C21, one end is connected with the VREF pin of management of charging and discharging chip U1, the resistance R1 of other end ground connection, one termination 3.3V input voltage, the resistance R2 that the other end is connected with the PB12 pin that son controls single-chip microcomputer with the STAT pin of management of charging and discharging chip U1 simultaneously, the PB11 pin that single-chip microcomputer is controlled with son in one end is connected, the resistance R14 that the other end is connected with the source electrode of metal-oxide-semiconductor Q5, one end ground connection, the resistance R18 that the other end is connected with the source electrode of metal-oxide-semiconductor Q5, one end is connected with the grid of metal-oxide-semiconductor Q5, the other end is as the resistance R6 of input, be serially connected in the resistance R19 between the ISET pin of management of charging and discharging chip U1 and VREF pin, one end ground connection, the resistance R25 that the other end is connected with the ISET pin of management of charging and discharging chip U1, be serially connected in the resistance R20 between the VRET pin of management of charging and discharging chip U1 and ACSET pin, and one end is connected with the ACSET pin of management of charging and discharging chip U1, the resistance R26 of other end ground connection forms, wherein, the source electrode of metal-oxide-semiconductor Q3 is connected with grid with the source electrode of metal-oxide-semiconductor Q2 respectively with grid, the drain electrode of metal-oxide-semiconductor Q2 is connected with the ACP pin of management of charging and discharging chip U1, the tie point ground connection of electric capacity C8 and electric capacity C17, resistance R5 is connected with two PVCC pins of management of charging and discharging chip U1 with the tie point of resistance R12 simultaneously, the minus earth of polar capacitor C1, the positive pole of polar capacitor C1 is connected with the positive pole of polar capacitor C3, the SRP pin of management of charging and discharging chip U1 is connected with the tie point of inductance L 1 with resistance R21, resistance R24 is connected with the CELL pin of management of charging and discharging chip U1 with the tie point of resistance R29, the VCC pin of connector P1 is connected with the drain electrode of metal-oxide-semiconductor Q4, the GND pin ground connection of connector P1, three PGND pins of management of charging and discharging chip U1 and the equal ground connection of AGND pin, the drain electrode of metal-oxide-semiconductor Q5 connects the input voltage of 3.3V, the drain electrode of metal-oxide-semiconductor Q3 is input, the source electrode of metal-oxide-semiconductor Q4 is connected with the VSYS pin of connector P1.

Further, above-mentioned switch-box testing circuit is by power management chip U2, one end is as input, the protective tube F1 that the other end is connected with the VIN pin of power management chip U2 after inductance L 5, positive pole is connected with the tie point of inductance L 5 with protective tube F1, the electric capacity C24 of minus earth, one end ground connection, the electric capacity C22 that the other end is connected with the VIN pin of power management chip U2, the electric capacity C23 in parallel with electric capacity C22, be serially connected in the electric capacity C29 between the VIN pin of power management chip U2 and UGND pin, one end is connected with the VCC pin of power management chip U2, the electric capacity C31 of other end ground connection, N pole is connected with two LX pins of power management chip U2 simultaneously, the Zener diode D3 of P pole ground connection, one end is connected with the P pole of Zener diode D3, the electric capacity C32 that the other end is connected with the COMP pin of power management chip U2 after resistance R34, be serially connected in the electric capacity C30 between the COMP pin of power management chip U2 and GND pin, one end is connected with the FB pin of power management chip U2, the resistance R33 that the other end is connected with the LX pin of power management chip U2 after inductance L 2, the electric capacity C25 in parallel with resistance R33, be serially connected in the resistance R35 on the FB pin of power management chip U2 and GND pin, positive pole is connected with the tie point of inductance L 2 with resistance R33, the electric capacity C27 of minus earth, and the electric capacity C26 in parallel with electric capacity C27 and electric capacity C28 forms respectively, wherein, the GND pin ground connection of power management chip U2, the just very output of electric capacity C27.

Further, the DC-DC/LDO power-switching circuit that above-mentioned sub-control panel connects is by step-down chip U3, power management chip U4, be serially connected in the resistance R36 between the VIN pin of power management chip U4 and EN pin, be serially connected in the electric capacity C44 between the VIN pin of power management chip U4 and UGND pin, one end ground connection, the electric capacity C47 that the other end is connected with the VCC pin of power management chip U4, N pole is connected with two LX pins of power management chip U4 simultaneously, the Zener diode D5 of P pole ground connection, be serially connected in the electric capacity C45 between the COMP pin of power management chip U4 and GND pin, one end is connected with the P pole of Zener diode D5, the electric capacity C48 that the other end is connected with the COMP pin of power management chip U4 after resistance R43, one end is connected with the N pole of Zener diode D5, the inductance L 4 that the other end is connected with the FB pin of power management chip U4 after resistance R37, the electric capacity C40 in parallel with resistance R37, be serially connected in the resistance R43 on the FB pin of power management chip U4 and GND pin, be serially connected in the resistance R39 on the IN pin of step-down chip U3 and EN pin, be serially connected in the electric capacity C43 on the IN pin of step-down chip U3 and GND pin, electric capacity C41 in parallel with electric capacity C43 respectively and electric capacity C42, positive pole is connected with the OUT pin of step-down chip U3, the polar capacitor C39 that negative pole is connected with the BYP pin of step-down chip U3 after electric capacity C46, and the electric capacity C37 in parallel with this polar capacitor C39 respectively, electric capacity C38 and electric capacity C39 forms, wherein, the VIN pin of power management chip U4 connects the input voltage of 12V, the GND pin ground connection of power management chip U4, resistance R37 is connected with the IN pin of step-down chip U3 with the tie point of inductance L 4, the GND pin ground connection of step-down chip U3, the IN pin of step-down chip U3 connects the input voltage of 5V, the minus earth of polar capacitor C39, its positive pole connects the input voltage of 3.3V.

As preferably, described power on-off control circuit is by triode Q12, metal-oxide-semiconductor Q6, the resistance R55 that one termination 12V input voltage, the other end are connected with the colelctor electrode of triode Q12, and the diode D7 that N pole is connected with the drain electrode of metal-oxide-semiconductor Q6, P pole is connected with the emitter stage of triode Q12 forms; Wherein, the base stage of triode Q12 is as input, and the drain electrode of metal-oxide-semiconductor is as output, and the P pole ground connection of diode D7, the colelctor electrode of triode Q12 is connected with the grid of metal-oxide-semiconductor Q6, the source electrode of metal-oxide-semiconductor Q6 connects 12V input voltage.

In addition, the DC-DC/LDO power-switching circuit that described master board connects is by power management chip U5, step-down chip U3, one end is as input, the protective tube F2 that the other end is connected with the VIN pin of power management chip U5, positive pole is connected with the VIN pin of power management chip U5, the electric capacity C49 of minus earth, one end is connected with the negative pole of electric capacity C49, the inductance L 2 of other end ground connection, electric capacity C50 in parallel with electric capacity C49 respectively and electric capacity C51, be serially connected in the resistance R44 between the VIN pin of power management chip U5 and EN pin, be serially connected in the electric capacity C52 between the VIN pin of power management chip U5 and UGND pin, one end is connected with the VCC pin of power management chip U5, the electric capacity C53 of other end ground connection, N pole is connected with two LX pins of power management chip U5 simultaneously, the Zener diode D6 of P pole ground connection, one end is connected with the P pole of Zener diode D6, the electric capacity C55 that the other end is connected with the COMP pin of power management chip U5 through resistance R45, be serially connected in the electric capacity C54 between the COMP pin of power management chip U5 and GND pin, one end is connected with the LX pin of power management chip U5, the inductance L 3 that the other end is connected with the FB pin of power management chip U5 after resistance R46, the electric capacity C56 in parallel with resistance R46, be serially connected in the resistance R47 between the FB pin of power management chip U5 and GND pin, be serially connected in the resistance R48 between the IN pin of step-down chip U6 and EN pin, be serially connected in the electric capacity C61 between the IN pin of step-down chip U6 and GND pin, be serially connected in the electric capacity C57 between the IN pin of step-down chip U6 and GND pin respectively, electric capacity C58, electric capacity C59 and electric capacity C60, positive pole is connected with the OUT pin of step-down chip U6, the polar capacitor C63 that negative pole is connected with the BYP pin of step-down chip U6 after electric capacity C62, electric capacity C64 in parallel with polar capacitor C63 respectively, electric capacity C65, electric capacity C66, electric capacity C67, electric capacity C68, electric capacity C69 and electric capacity C70, and N pole ground connection, the LED 1 that P pole is connected with the positive pole of polar capacitor C63 after resistance R49 forms, wherein, the positive pole of electric capacity C49 connects 7.4V input voltage, the GND pin ground connection of power management chip U5, the IN pin of step-down chip U6 connects 3.8V input voltage and is connected with the tie point of inductance L 3 with resistance 46, the GND pin ground connection of step-down chip U6, the minus earth of polar capacitor C63, positive pole connect 3.3V input voltage.

As preferably, described 3G/GPRS circuit is also provided with the 3G input power circuit be connected with 3G circuit, this 3G input power circuit is by metal-oxide-semiconductor Q1, one end is connected with 3G circuit, the resistance R50 that the other end is connected with the grid of metal-oxide-semiconductor Q1, one termination 3.8V input voltage, the resistance R51 that the other end is connected with the grid of metal-oxide-semiconductor Q1, one end is connected with the grid of metal-oxide-semiconductor Q1, the electric capacity C71 that the other end is connected with the drain electrode of metal-oxide-semiconductor Q1 after electric capacity C72, the electric capacity C73 in parallel with electric capacity C72, and the resistance R52 be serially connected between the drain electrode of metal-oxide-semiconductor Q1 and source electrode forms, wherein, the tie point ground connection of electric capacity C71 and electric capacity C72, the source electrode of metal-oxide-semiconductor Q1 connects in 3.8V input voltage, drain electrode and connects 3.8V input voltage.

As preferably, described 3G/GPRS circuit is also provided with the GPRS input power circuit be connected with GPRS circuit, this GPRS input power circuit regulates chip U7 by voltage stabilizing, one end and voltage stabilizing regulate the VIN pin of chip U7 to be connected, the electric capacity C74 that the other end and voltage stabilizing regulate the GND pin of chip U7 to be connected, one end and voltage stabilizing regulate the EN pin of chip U7 to be connected, the resistance R53 that the other end and voltage stabilizing regulate the GND pin of chip U7 to be connected, positive pole and voltage stabilizing regulate the VOUT pin of chip U7 to be connected, the polar capacitor C77 of minus earth, and the electric capacity C75 in parallel with polar capacitor C77 and electric capacity C76 forms respectively, wherein, voltage stabilizing regulates on the VIN pin of chip U7 and connects 3.8V input voltage, EN pin is connected with GPRS circuit, GND pin ground connection, the positive pole of polar capacitor C77 connects 3V input voltage.

Wherein, described main control singlechip model is STM32F103VET6, the model of son control single-chip microcomputer is STM32F051C8T6, the model of management of charging and discharging chip U1 is BQ24172RGYR-VQFN24, the model of power management chip U2, power management chip U4 and power management chip U5 is APW7080KAI-TRG, the model of step-down chip U3 and step-down chip U6 is MIC5219, and voltage stabilizing regulates the model of chip U7 to be SP6201.

The present invention comparatively prior art compares, and has the following advantages and beneficial effect:

(1) master board of the present invention is powered respectively by different charge power supplies from sub-control panel, the independently-powered running time that improve product, more ensure that master board can the operation of lasting stability, thus control centre can be positioned it for a long time, further increase the safety of product; Location adopts GPS/BD dual chip to position, sends locating information to control centre in real time, further increase the reliability of product orientation.

(2) the present invention is provided with single-chip microcomputer, can intelligence complete control to inside and the communication to outside, improve the intelligent of product, also by Long-distance Control, its range of movement is limited simultaneously, just can report to the police voluntarily once exceed limited field.

(3) the present invention is provided with multiple type of alarm, can be reported to the police by sound, smog or control centre, thus improve the safety of product, can be reported to the police by every mode after product is stolen, then carry out quick position according to location structure, greatly ensure the safe handling process of product.

(4) the present invention is provided with high-voltage electric shock device, can carry out product protection when offender steals and robs, and what arrange that the handle that comes off then can increase product carries difficulty, reduce further the translational speed of offender, product can be recovered faster.

(5) the present invention completes the switch of electromagnetic lock by Long-distance Control, does not adopt mechanical key, further increases the difficulty of unblanking, better protect product.

(6) the present invention adopts the multiple-authentication modes such as fingerprint, nfc card and remote control, only just can open after proving identity through multiple confirmation, improve the reliability of product.

Accompanying drawing explanation

Fig. 1 is structured flowchart of the present invention.

Fig. 2 is the circuit diagram of 12V management of charging and discharging circuit of the present invention.

Fig. 3 is the circuit diagram of switch-box testing circuit of the present invention.

Fig. 4 is the circuit diagram of the DC-DC/LDO power-switching circuit that the present invention is connected with sub-control panel.

Fig. 5 is the circuit diagram of power on-off control circuit of the present invention.

Fig. 6 is the circuit diagram of the DC-DC/LDO power-switching circuit that the present invention is connected with master board.

Fig. 7 is the 3G input power circuit that the present invention is connected with 3G circuit.

Fig. 8 is the GPRS input power circuit that the present invention is connected with GPRS circuit.

Detailed description of the invention

Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited thereto.

Embodiment

As shown in Figure 1, the present invention includes control centre, safety box main body, is arranged on the electromagnetic lock in safety box main body, smoke alarm, voice guard, comes off handle and high-voltage electric shock device, and is arranged on the master board be connected by UART bus of safety body interior and sub-control panel; Master board and sub-control panel are respectively arranged with a DC-DC/LDO Power convert structure, master board has 7.4V management of charging and discharging structure by DC-DC/LDO Power convert anatomical connectivity, and sub-control panel has 12V management of charging and discharging structure by DC-DC/LDO Power convert anatomical connectivity; Described master board comprises main control singlechip, respectively by NFC circuit, GPS/BD circuit, 3G/GPRS circuit, fingerprint detection circuit and RF remote control circuit that UART bus is connected with this main control singlechip, the SD memory circuit be connected with main control singlechip by spi bus and OLED screen circuit, and by gyroscope block that iic bus is connected with main control singlechip; Described sub-control panel comprises son control single-chip microcomputer, and the SD memory circuit, NFC circuit, gyroscope block, GPS/BD circuit, 3G/GPRS circuit and the fingerprint detection circuit that are connected on this son control single-chip microcomputer, described son control single-chip microcomputer is connected respectively by different power on-off control circuits and electromagnetic lock, smoke alarm, voice guard, come off handle and high-voltage electric shock device; Master board is controlled single-chip microcomputer with son and is connected by UART bus; Be provided with DC-DC/LDO power-switching circuit in DC-DC/LDO Power convert structure, in 12V management of charging and discharging structure, be provided with 12V management of charging and discharging circuit; 3G/GPRS circuit is made up of 3G circuit and GPRS circuit again.

Master board is powered respectively by different power supplys from sub-control panel, can be good at the supply guaranteeing its electricity, further ensures master board never power-off, improves the ability of its time run and continuation of the journey.Master board arranges location structure and every control structure, long range positioning and the control of safety box can be realized, and multinomial safety verification structure better can guarantee that safety box is not cracked by people intentionally, further increases the safety of product; In addition, sub-control panel is provided with multiple warning device and protector, can reports to the police by instant carrying out, also come off by the handle of control centre's operated from a distance safety box and produce electric shock simultaneously, the further safety ensureing safety box, add its stolen time move difficulty.

As shown in Figure 2, above-mentioned 12V management of charging and discharging circuit is by management of charging and discharging chip U1, connector P1, metal-oxide-semiconductor Q2, metal-oxide-semiconductor Q3, metal-oxide-semiconductor Q4, metal-oxide-semiconductor Q5, resistance R1, resistance R2, resistance R5, resistance R6, resistance R7, resistance R8, resistance R9, resistance R10, resistance R11, resistance R12, resistance R13, resistance R14, resistance R15, resistance R16, resistance R17, resistance R18, resistance R19, resistance R20, resistance R21, resistance R22, resistance R23, resistance R24, resistance R25, resistance R26, resistance R27, resistance R28, resistance R29, resistance R30, resistance R31, resistance R32, polar capacitor C1, electric capacity C2, polar capacitor C3, electric capacity C4, electric capacity C5, electric capacity C6, electric capacity C7, electric capacity C8, polar capacitor C9, polar capacitor C10, electric capacity C11, electric capacity C12, electric capacity C13, electric capacity C14, electric capacity C15, electric capacity C16, electric capacity C17, electric capacity C18, electric capacity C19, electric capacity C20, electric capacity C21, Zener diode D1, Zener diode group D2, and inductance L 1 forms.

During connection, one end of resistance R8 is connected with the drain electrode of metal-oxide-semiconductor Q3, the other end is ground connection after electric capacity C6, resistance R9 is in parallel with resistance R8, one end of resistance R10 is connected with the drain electrode of metal-oxide-semiconductor Q3, the other end is ground connection after resistance R17, electric capacity C13 is in parallel with resistance R17, between the drain electrode that electric capacity C7 is serially connected in metal-oxide-semiconductor Q3 and grid, between the grid that electric capacity C4 is serially connected in metal-oxide-semiconductor Q3 and source electrode, resistance R11 is in parallel with electric capacity C4, one of them P pole of Zener diode group D2 is connected with the drain electrode of metal-oxide-semiconductor, the VBAT pin that single-chip microcomputer is controlled with son in another P pole is connected, two N are extremely all connected with the AVCC pin of management of charging and discharging chip U1 after resistance R28, one end of resistance R15 is connected with the grid of metal-oxide-semiconductor Q3, the other end is connected with the ACDRV pin of management of charging and discharging chip U1, one end of resistance R16 is connected with the source electrode of metal-oxide-semiconductor Q3, the other end is connected with the CMSRC pin of management of charging and discharging chip U1, one end of electric capacity C8 is connected with the drain electrode of metal-oxide-semiconductor Q2, the other end is connected with the AVCC of management of charging and discharging chip U1 after electric capacity C17, one end of resistance R5 is connected with the drain electrode of metal-oxide-semiconductor Q2, the other end is connected with the CAN pin of management of charging and discharging chip U1 after resistance R12, between the ACP pin that electric capacity C5 is serially connected in management of charging and discharging chip U1 and CAN pin, the N pole of Zener diode D1 is connected with two SW pins of management of charging and discharging chip U1, P pole is connected with the tie point of resistance R12 with resistance R5 after electric capacity C2, polar capacitor C1 is in parallel with electric capacity C2, the positive pole of electric capacity C3 is connected with the source electrode of metal-oxide-semiconductor Q4, minus earth, one end of inductance L 1 is connected with the SW pin of management of charging and discharging chip U1, the other end is connected with the drain electrode of metal-oxide-semiconductor Q4 after resistance R21, one end of electric capacity C14 is connected with the SW pin of management of charging and discharging chip U1, the other end is connected with the BTST pin of management of charging and discharging chip U1 after resistance R27, one end of electric capacity C19 is connected with the REGN pin of management of charging and discharging chip U1, other end ground connection, one end ground connection of electric capacity C16, one end is connected with the SRP pin of management of charging and discharging chip U1, between the SRP pin that electric capacity C18 is serially connected in management of charging and discharging chip U1 and SRN pin, one end of resistance R23 is connected with the SRN pin of management of charging and discharging chip U1, the other end is connected with the drain electrode of metal-oxide-semiconductor Q4, one end of polar capacitor C9 is connected with the drain electrode of metal-oxide-semiconductor Q4, other end ground connection, polar capacitor C10 and electric capacity C11 is in parallel with polar capacitor C9 respectively, one end of resistance R7 is connected with the grid of metal-oxide-semiconductor Q4, other end ground connection, one end of resistance R13 is connected with the grid of metal-oxide-semiconductor Q4, the other end is connected with the BATDRV pin of management of charging and discharging chip U1, one end of electric capacity C12 is connected with the drain electrode of metal-oxide-semiconductor Q4, other end ground connection, one end of resistance R22 is connected with the grid of metal-oxide-semiconductor Q4, the other end is in turn through resistance R24, ground connection after R29, electric capacity C15 is in parallel with resistance R24, one end of resistance R30 is connected with the NTC pin of connector P1, the other end is connected with the VREF pin of management of charging and discharging chip U1, one end of resistance R32 is connected with the NTC pin of connector P1, other end ground connection, one end of resistance R31 is connected with the NTC pin of connector P1, the other end is connected with the TS pin of management of charging and discharging chip U1, one end of electric capacity C21 is connected with the TTC pin of management of charging and discharging chip U1, other end ground connection, one end of electric capacity C20 is connected with the VREF pin of management of charging and discharging chip U1, the other end is connected with the earth terminal of electric capacity C21, one end of resistance R1 is connected with the VREF pin of management of charging and discharging chip U1, other end ground connection, the one termination 3.3V input voltage of resistance R2, the other end is connected with the PB12 pin that son controls single-chip microcomputer with the STAT pin of management of charging and discharging chip U1 simultaneously, the PB11 pin that one end and the son of resistance R14 control single-chip microcomputer is connected, the other end is connected with the source electrode of metal-oxide-semiconductor Q5, one end ground connection of resistance R18, the other end is connected with the source electrode of metal-oxide-semiconductor Q5, one end of resistance R6 is connected with the grid of metal-oxide-semiconductor Q5, the other end is as input, between the ISET pin that resistance R19 is serially connected in management of charging and discharging chip U1 and VREF pin, one end ground connection of resistance R25, the other end is connected with the ISET pin of management of charging and discharging chip U1, between the VRET pin that resistance R20 is serially connected in management of charging and discharging chip U1 and ACSET pin, one end of resistance R26 is connected with the ACSET pin of management of charging and discharging chip U1, other end ground connection.

Wherein, the source electrode of metal-oxide-semiconductor Q3 is connected with grid with the source electrode of metal-oxide-semiconductor Q2 respectively with grid, the drain electrode of metal-oxide-semiconductor Q2 is connected with the ACP pin of management of charging and discharging chip U1, the tie point ground connection of electric capacity C8 and electric capacity C17, resistance R5 is connected with two PVCC pins of management of charging and discharging chip U1 with the tie point of resistance R12 simultaneously, the minus earth of polar capacitor C1, the positive pole of polar capacitor C1 is connected with the positive pole of polar capacitor C3, the SRP pin of management of charging and discharging chip U1 is connected with the tie point of inductance L 1 with resistance R21, resistance R24 is connected with the CELL pin of management of charging and discharging chip U1 with the tie point of resistance R29, the VCC pin of connector P1 is connected with the drain electrode of metal-oxide-semiconductor Q4, the GND pin ground connection of connector P1, three PGND pins of management of charging and discharging chip U1 and the equal ground connection of AGND pin, the drain electrode of metal-oxide-semiconductor Q5 connects the input voltage of 3.3V, the drain electrode of metal-oxide-semiconductor Q3 is input, the source electrode of metal-oxide-semiconductor Q4 is connected with the VSYS pin of connector P1.

As shown in Figure 3, above-mentioned switch-box testing circuit by power management chip U2, protective tube F1, resistance R33, resistance R34, resistance R35, electric capacity C22, electric capacity C23, electric capacity C24, electric capacity C25, electric capacity C26, electric capacity C27, electric capacity C28, electric capacity C30, electric capacity C31, electric capacity C32, inductance L 2, and inductance L 5 forms.

During connection, one end of protective tube F1 is as input, the other end is connected with the VIN pin of power management chip U2 after inductance L 5, the positive pole of electric capacity C24 is connected with the tie point of inductance L 5 with protective tube F1, minus earth, one end ground connection of electric capacity C22, the other end is connected with the VIN pin of power management chip U2, electric capacity C23 is in parallel with electric capacity C22, electric capacity C29 is serially connected between the VIN pin of power management chip U2 and UGND pin, one end of electric capacity C31 is connected with the VCC pin of power management chip U2, other end ground connection, the N pole of Zener diode D3 is connected with two LX pins of power management chip U2 simultaneously, P pole ground connection, one end of electric capacity C32 is connected with the P pole of Zener diode D3, the other end is connected with the COMP pin of power management chip U2 after resistance R34, electric capacity C30 is serially connected between the COMP pin of power management chip U2 and GND pin, one end of resistance R33 is connected with the FB pin of power management chip U2, the other end is connected with the LX pin of power management chip U2 after inductance L 2, electric capacity C25 is in parallel with resistance R33, on the FB pin that resistance R35 is serially connected in power management chip U2 and GND pin, the positive pole of electric capacity C27 is connected with the tie point of inductance L 2 with resistance R33, minus earth, electric capacity C26 and electric capacity C28 is in parallel with electric capacity C27 respectively, wherein, the GND pin ground connection of power management chip U2, the just very output of electric capacity C27.

As shown in Figure 4, the DC-DC/LDO power-switching circuit of above-mentioned sub-control panel connection is by step-down chip U3, power management chip U4, resistance R36, resistance R37, resistance R39, resistance R42, resistance R43, electric capacity C40, electric capacity C36, electric capacity C37, electric capacity C38, polar capacitor C39, electric capacity C40, electric capacity C41, electric capacity C42, electric capacity C43, electric capacity C44, electric capacity C45, electric capacity C46, electric capacity C47, electric capacity C48, inductance L 4, and Zener diode D5 forms.

During connection, resistance R36 is serially connected between the VIN pin of power management chip U4 and EN pin, electric capacity C44 is serially connected between the VIN pin of power management chip U4 and UGND pin, one end ground connection of electric capacity C47, the other end is connected with the VCC pin of power management chip U4, the N pole of Zener diode D5 is connected with two LX pins of power management chip U4 simultaneously, P pole ground connection, electric capacity C45 is serially connected between the COMP pin of power management chip U4 and GND pin, one end of electric capacity C48 is connected with the P pole of Zener diode D5, the other end is connected with the COMP pin of power management chip U4 after resistance R43, one end of inductance L 4 is connected with the N pole of Zener diode D5, the other end is connected with the FB pin of power management chip U4 after resistance R37, electric capacity C40 is in parallel with resistance R37, on the FB pin that resistance R43 is serially connected in power management chip U4 and GND pin, on the IN pin that resistance R39 is serially connected in step-down chip U3 and EN pin, on the IN pin that electric capacity C43 is serially connected in step-down chip U3 and GND pin, electric capacity C41 and electric capacity C42 is in parallel with electric capacity C43 respectively, the positive pole of polar capacitor C39 is connected with the OUT pin of step-down chip U3, negative pole is connected with the BYP pin of step-down chip U3 after electric capacity C46, electric capacity C37, electric capacity C38 and electric capacity C39 is in parallel with this polar capacitor C39 respectively.

Wherein, the VIN pin of power management chip U4 connects the input voltage of 12V, the GND pin ground connection of power management chip U4, resistance R37 is connected with the IN pin of step-down chip U3 with the tie point of inductance L 4, the GND pin ground connection of step-down chip U3, the IN pin of step-down chip U3 connects the input voltage of 5V, the minus earth of polar capacitor C39, its positive pole connects the input voltage of 3.3V.

As shown in Figure 5, described power on-off control circuit is by triode Q12, and metal-oxide-semiconductor Q6, resistance R55, diode D7 form.During connection, a termination 12V input voltage of resistance R55, the other end are connected with the colelctor electrode of triode Q12, and the N pole of diode D7 is connected with the drain electrode of metal-oxide-semiconductor Q6, P pole is connected with the emitter stage of triode Q12; Wherein, the base stage of triode Q12 is as input, and the drain electrode of metal-oxide-semiconductor is as output, and the P pole ground connection of diode D7, the colelctor electrode of triode Q12 is connected with the grid of metal-oxide-semiconductor Q6, the source electrode of metal-oxide-semiconductor Q6 connects 12V input voltage.

As shown in Figure 6, the DC-DC/LDO power-switching circuit that described master board connects is by power management chip U5, step-down chip U3, protective tube F2, electric capacity C49, electric capacity C50, electric capacity C51, electric capacity C52, electric capacity C53, electric capacity C54, electric capacity C55, electric capacity C56, electric capacity C57, electric capacity C58, electric capacity C59, electric capacity C60, electric capacity C61, electric capacity C62, polar capacitor C63, electric capacity C64, electric capacity C65, electric capacity C66, electric capacity C67, electric capacity C68, electric capacity C69, electric capacity C70, resistance R44, resistance R45, resistance R46, resistance R47, resistance R48, resistance R49, Zener diode D6, LED 1, inductance L 2, and inductance L 3 forms.

During connection, one end of protective tube F2 is as input, the other end is connected with the VIN pin of power management chip U5, the positive pole of electric capacity C49 is connected with the VIN pin of power management chip U5, minus earth, one end of inductance L 2 is connected with the negative pole of electric capacity C49, other end ground connection, electric capacity C50 and electric capacity C51 is in parallel with electric capacity C49 respectively, resistance R44 is serially connected between the VIN pin of power management chip U5 and EN pin, electric capacity C52 is serially connected between the VIN pin of power management chip U5 and UGND pin, one end of electric capacity C53 is connected with the VCC pin of power management chip U5, other end ground connection, the N pole of Zener diode D6 is connected with two LX pins of power management chip U5 simultaneously, P pole ground connection, one end of electric capacity C55 is connected with the P pole of Zener diode D6, the other end is connected with the COMP pin of power management chip U5 through resistance R45, electric capacity C54 is serially connected between the COMP pin of power management chip U5 and GND pin, one end of inductance L 3 is connected with the LX pin of power management chip U5, the other end is connected with the FB pin of power management chip U5 after resistance R46, electric capacity C56 is in parallel with resistance R46, resistance R47 is serially connected between the FB pin of power management chip U5 and GND pin, between the IN pin that resistance R48 is serially connected in step-down chip U6 and EN pin, between the IN pin that electric capacity C61 is serially connected in step-down chip U6 and GND pin, electric capacity C57, electric capacity C58, between the IN pin that electric capacity C59 and electric capacity C60 is serially connected in step-down chip U6 respectively and GND pin, the positive pole of polar capacitor C63 is connected with the OUT pin of step-down chip U6, negative pole is connected with the BYP pin of step-down chip U6 after electric capacity C62, electric capacity C64, electric capacity C65, electric capacity C66, electric capacity C67, electric capacity C68, electric capacity C69 and electric capacity C70 is in parallel with polar capacitor C63 respectively, the N pole ground connection of LED 1, P pole is connected with the positive pole of polar capacitor C63 after resistance R49.

Wherein, the positive pole of electric capacity C49 connects 7.4V input voltage, the GND pin ground connection of power management chip U5, the IN pin of step-down chip U6 connects 3.8V input voltage and is connected with the tie point of inductance L 3 with resistance 46, the GND pin ground connection of step-down chip U6, the minus earth of polar capacitor C63, positive pole connect 3.3V input voltage.

As shown in Figure 7, described 3G/GPRS circuit is also provided with the 3G input power circuit be connected with 3G circuit, this 3G input power circuit by metal-oxide-semiconductor Q1, resistance R50, resistance R51, resistance R52, electric capacity C71, electric capacity C72, and electric capacity C73 forms; During connection, one end of resistance R50 is connected with 3G circuit, the other end is connected with the grid of metal-oxide-semiconductor Q1, the one termination 3.8V input voltage of resistance R51, the other end are connected with the grid of metal-oxide-semiconductor Q1, one end of electric capacity C71 is connected with the grid of metal-oxide-semiconductor Q1, the other end is connected with the drain electrode of metal-oxide-semiconductor Q1 after electric capacity C72, electric capacity C73 is in parallel with electric capacity C72, between the drain electrode that resistance R52 is serially connected in metal-oxide-semiconductor Q1 and source electrode; Wherein, the tie point ground connection of electric capacity C71 and electric capacity C72, the source electrode of metal-oxide-semiconductor Q1 connects in 3.8V input voltage, drain electrode and connects 3.8V input voltage.

As shown in Figure 8, described 3G/GPRS circuit is also provided with the GPRS input power circuit be connected with GPRS circuit, this GPRS input power circuit regulates chip U7 by voltage stabilizing, resistance R53, electric capacity C74, electric capacity C75, electric capacity C76, and polar capacitor C77 forms; During connection, one end and the voltage stabilizing of electric capacity C74 regulate that the VIN pin of chip U7 is connected, the other end regulates the GND pin of chip U7 to be connected with voltage stabilizing, one end and the voltage stabilizing of resistance R53 regulate that the EN pin of chip U7 is connected, the other end regulates the GND pin of chip U7 to be connected with voltage stabilizing, positive pole and the voltage stabilizing of polar capacitor C77 regulate that the VOUT pin of chip U7 is connected, minus earth, and electric capacity C75 and electric capacity C76 is in parallel with polar capacitor C77 respectively; Wherein, voltage stabilizing regulates on the VIN pin of chip U7 and connects 3.8V input voltage, EN pin is connected with GPRS circuit, GND pin ground connection, the positive pole of polar capacitor C77 connects 3V input voltage.

The preferred model of main control singlechip is STM32F103VET6, the preferred model of son control single-chip microcomputer is STM32F051C8T6, the preferred model of management of charging and discharging chip U1 is BQ24172RGYR-VQFN24, the preferred model of power management chip U2, power management chip U4 and power management chip U5 is APW7080KAI-TRG, the preferred model of step-down chip U3 and step-down chip U6 is MIC5219, and voltage stabilizing regulates the preferred model of chip U7 to be SP6201.

By said method, just well the present invention can be realized.

Claims (9)

1. remote tracing controls formula safety box, it is characterized in that, comprise control centre, safety box main body, be arranged on the electromagnetic lock in safety box main body, smoke alarm, voice guard, come off handle and high-voltage electric shock device, and be arranged on the master board be connected by UART bus of safety box body interior and sub-control panel; Master board and sub-control panel are respectively arranged with a DC-DC/LDO Power convert structure, master board has 7.4V management of charging and discharging structure by DC-DC/LDO Power convert anatomical connectivity, and sub-control panel has 12V management of charging and discharging structure by DC-DC/LDO Power convert anatomical connectivity; Described master board comprises main control singlechip, respectively by NFC circuit, GPS/BD circuit, 3G/GPRS circuit, fingerprint detection circuit and RF remote control circuit that UART bus is connected with this main control singlechip, the SD memory circuit be connected with main control singlechip by spi bus and OLED screen circuit, and by gyroscope block that iic bus is connected with main control singlechip; Described sub-control panel comprises son control single-chip microcomputer, and controls with this son SD memory circuit, NFC circuit, gyroscope block, GPS/BD circuit, 3G/GPRS circuit and the fingerprint detection circuit that single-chip microcomputer is connected; Described son control single-chip microcomputer is connected respectively by different power on-off control circuits and electromagnetic lock, smoke alarm, voice guard, come off handle and high-voltage electric shock device; Master board is controlled single-chip microcomputer with son and is connected by UART bus; Be provided with DC-DC/LDO power-switching circuit in DC-DC/LDO Power convert structure, in 12V management of charging and discharging structure, be provided with 12V management of charging and discharging circuit; 3G/GPRS circuit is made up of 3G circuit and GPRS circuit again.

2. remote tracing according to claim 1 controls formula safety box, it is characterized in that, described 12V management of charging and discharging circuit is by management of charging and discharging chip U1, connector P1, metal-oxide-semiconductor Q2, metal-oxide-semiconductor Q3, metal-oxide-semiconductor Q4, metal-oxide-semiconductor Q5, one end is connected with the drain electrode of metal-oxide-semiconductor Q3, the resistance R8 of other end ground connection after electric capacity C6, the resistance R9 in parallel with resistance R8, one end is connected with the drain electrode of metal-oxide-semiconductor Q3, the resistance R10 of other end ground connection after resistance R17, the electric capacity C13 in parallel with resistance R17, be serially connected in the electric capacity C7 between the drain electrode of metal-oxide-semiconductor Q3 and grid, be serially connected in the electric capacity C4 between the grid of metal-oxide-semiconductor Q3 and source electrode, the resistance R11 in parallel with electric capacity C4, one of them P pole is connected with the drain electrode of metal-oxide-semiconductor, the VBAT pin that single-chip microcomputer is controlled with son in another P pole is connected, the Zener diode group D2 that two N are extremely all connected with the AVCC pin of management of charging and discharging chip U1 after resistance R28, one end is connected with the grid of metal-oxide-semiconductor Q3, the resistance R15 that the other end is connected with the ACDRV pin of management of charging and discharging chip U1, one end is connected with the source electrode of metal-oxide-semiconductor Q3, the resistance R16 that the other end is connected with the CMSRC pin of management of charging and discharging chip U1, one end is connected with the drain electrode of metal-oxide-semiconductor Q2, the electric capacity C8 that the other end is connected with the AVCC of management of charging and discharging chip U1 after electric capacity C17, one end is connected with the drain electrode of metal-oxide-semiconductor Q2, the resistance R5 that the other end is connected with the CAN pin of management of charging and discharging chip U1 after resistance R12, be serially connected in the electric capacity C5 between the ACP pin of management of charging and discharging chip U1 and CAN pin, N pole is connected with two SW pins of management of charging and discharging chip U1, the Zener diode D1 that P pole is connected with the tie point of resistance R12 with resistance R5 after electric capacity C2, the polar capacitor C1 in parallel with electric capacity C2, positive pole is connected with the source electrode of metal-oxide-semiconductor Q4, the electric capacity C3 of minus earth, one end is connected with the SW pin of management of charging and discharging chip U1, the inductance L 1 that the other end is connected with the drain electrode of metal-oxide-semiconductor Q4 after resistance R21, one end is connected with the SW pin of management of charging and discharging chip U1, the electric capacity C14 that the other end is connected with the BTST pin of management of charging and discharging chip U1 after resistance R27, one end is connected with the REGN pin of management of charging and discharging chip U1, the electric capacity C19 of other end ground connection, one end ground connection, the electric capacity C16 that one end is connected with the SRP pin of management of charging and discharging chip U1, be serially connected in the electric capacity C18 between the SRP pin of management of charging and discharging chip U1 and SRN pin, one end is connected with the SRN pin of management of charging and discharging chip U1, the resistance R23 that the other end is connected with the drain electrode of metal-oxide-semiconductor Q4, one end is connected with the drain electrode of metal-oxide-semiconductor Q4, the polar capacitor C9 of other end ground connection, polar capacitor C10 in parallel with polar capacitor C9 respectively and electric capacity C11, one end is connected with the grid of metal-oxide-semiconductor Q4, the resistance R7 of other end ground connection, one end is connected with the grid of metal-oxide-semiconductor Q4, the resistance R13 that the other end is connected with the BATDRV pin of management of charging and discharging chip U1, one end is connected with the drain electrode of metal-oxide-semiconductor Q4, the electric capacity C12 of other end ground connection, one end is connected with the grid of metal-oxide-semiconductor Q4, the other end is in turn through resistance R24, the resistance R22 of ground connection after R29, the electric capacity C15 in parallel with resistance R24, one end is connected with the NTC pin of connector P1, the resistance R30 that the other end is connected with the VREF pin of management of charging and discharging chip U1, one end is connected with the NTC pin of connector P1, the resistance R32 of other end ground connection, one end is connected with the NTC pin of connector P1, the resistance R31 that the other end is connected with the TS pin of management of charging and discharging chip U1, one end is connected with the TTC pin of management of charging and discharging chip U1, the electric capacity C21 of other end ground connection, one end is connected with the VREF pin of management of charging and discharging chip U1, the electric capacity C20 that the other end is connected with the earth terminal of electric capacity C21, one end is connected with the VREF pin of management of charging and discharging chip U1, the resistance R1 of other end ground connection, one termination 3.3V input voltage, the resistance R2 that the other end is connected with the PB12 pin that son controls single-chip microcomputer with the STAT pin of management of charging and discharging chip U1 simultaneously, the PB11 pin that single-chip microcomputer is controlled with son in one end is connected, the resistance R14 that the other end is connected with the source electrode of metal-oxide-semiconductor Q5, one end ground connection, the resistance R18 that the other end is connected with the source electrode of metal-oxide-semiconductor Q5, one end is connected with the grid of metal-oxide-semiconductor Q5, the other end is as the resistance R6 of input, be serially connected in the resistance R19 between the ISET pin of management of charging and discharging chip U1 and VREF pin, one end ground connection, the resistance R25 that the other end is connected with the ISET pin of management of charging and discharging chip U1, be serially connected in the resistance R20 between the VRET pin of management of charging and discharging chip U1 and ACSET pin, and one end is connected with the ACSET pin of management of charging and discharging chip U1, the resistance R26 of other end ground connection forms, wherein, the source electrode of metal-oxide-semiconductor Q3 is connected with grid with the source electrode of metal-oxide-semiconductor Q2 respectively with grid, the drain electrode of metal-oxide-semiconductor Q2 is connected with the ACP pin of management of charging and discharging chip U1, the tie point ground connection of electric capacity C8 and electric capacity C17, resistance R5 is connected with two PVCC pins of management of charging and discharging chip U1 with the tie point of resistance R12 simultaneously, the minus earth of polar capacitor C1, the positive pole of polar capacitor C1 is connected with the positive pole of polar capacitor C3, the SRP pin of management of charging and discharging chip U1 is connected with the tie point of inductance L 1 with resistance R21, resistance R24 is connected with the CELL pin of management of charging and discharging chip U1 with the tie point of resistance R29, the VCC pin of connector P1 is connected with the drain electrode of metal-oxide-semiconductor Q4, the GND pin ground connection of connector P1, three PGND pins of management of charging and discharging chip U1 and the equal ground connection of AGND pin, the drain electrode of metal-oxide-semiconductor Q5 connects the input voltage of 3.3V, the drain electrode of metal-oxide-semiconductor Q3 is input, the source electrode of metal-oxide-semiconductor Q4 is connected with the VSYS pin of connector P1.

3. remote tracing according to claim 2 controls formula safety box, it is characterized in that, described switch-box testing circuit is by power management chip U2, one end is as input, the protective tube F1 that the other end is connected with the VIN pin of power management chip U2 after inductance L 5, positive pole is connected with the tie point of inductance L 5 with protective tube F1, the electric capacity C24 of minus earth, one end ground connection, the electric capacity C22 that the other end is connected with the VIN pin of power management chip U2, the electric capacity C23 in parallel with electric capacity C22, be serially connected in the electric capacity C29 between the VIN pin of power management chip U2 and UGND pin, one end is connected with the VCC pin of power management chip U2, the electric capacity C31 of other end ground connection, N pole is connected with two LX pins of power management chip U2 simultaneously, the Zener diode D3 of P pole ground connection, one end is connected with the P pole of Zener diode D3, the electric capacity C32 that the other end is connected with the COMP pin of power management chip U2 after resistance R34, be serially connected in the electric capacity C30 between the COMP pin of power management chip U2 and GND pin, one end is connected with the FB pin of power management chip U2, the resistance R33 that the other end is connected with the LX pin of power management chip U2 after inductance L 2, the electric capacity C25 in parallel with resistance R33, be serially connected in the resistance R35 on the FB pin of power management chip U2 and GND pin, positive pole is connected with the tie point of inductance L 2 with resistance R33, the electric capacity C27 of minus earth, and the electric capacity C26 in parallel with electric capacity C27 and electric capacity C28 forms respectively, wherein, the GND pin ground connection of power management chip U2, the just very output of electric capacity C27.

4. remote tracing according to claim 3 controls formula safety box, it is characterized in that, the DC-DC/LDO power-switching circuit that described sub-control panel connects is by step-down chip U3, power management chip U4, be serially connected in the resistance R36 between the VIN pin of power management chip U4 and EN pin, be serially connected in the electric capacity C44 between the VIN pin of power management chip U4 and UGND pin, one end ground connection, the electric capacity C47 that the other end is connected with the VCC pin of power management chip U4, N pole is connected with two LX pins of power management chip U4 simultaneously, the Zener diode D5 of P pole ground connection, be serially connected in the electric capacity C45 between the COMP pin of power management chip U4 and GND pin, one end is connected with the P pole of Zener diode D5, the electric capacity C48 that the other end is connected with the COMP pin of power management chip U4 after resistance R43, one end is connected with the N pole of Zener diode D5, the inductance L 4 that the other end is connected with the FB pin of power management chip U4 after resistance R37, the electric capacity C40 in parallel with resistance R37, be serially connected in the resistance R43 on the FB pin of power management chip U4 and GND pin, be serially connected in the resistance R39 on the IN pin of step-down chip U3 and EN pin, be serially connected in the electric capacity C43 on the IN pin of step-down chip U3 and GND pin, electric capacity C41 in parallel with electric capacity C43 respectively and electric capacity C42, positive pole is connected with the OUT pin of step-down chip U3, the polar capacitor C39 that negative pole is connected with the BYP pin of step-down chip U3 after electric capacity C46, and the electric capacity C37 in parallel with this polar capacitor C39 respectively, electric capacity C38 and electric capacity C39 forms, wherein, the VIN pin of power management chip U4 connects the input voltage of 12V, the GND pin ground connection of power management chip U4, resistance R37 is connected with the IN pin of step-down chip U3 with the tie point of inductance L 4, the GND pin ground connection of step-down chip U3, the IN pin of step-down chip U3 connects the input voltage of 5V, the minus earth of polar capacitor C39, its positive pole connects the input voltage of 3.3V.

5. remote tracing according to claim 4 controls formula safety box, it is characterized in that, described power on-off control circuit is by triode Q12, metal-oxide-semiconductor Q6, the resistance R55 that one termination 12V input voltage, the other end are connected with the colelctor electrode of triode Q12, and the diode D7 that N pole is connected with the drain electrode of metal-oxide-semiconductor Q6, P pole is connected with the emitter stage of triode Q12 forms; Wherein, the base stage of triode Q12 is as input, and the drain electrode of metal-oxide-semiconductor is as output, and the P pole ground connection of diode D7, the colelctor electrode of triode Q12 is connected with the grid of metal-oxide-semiconductor Q6, the source electrode of metal-oxide-semiconductor Q6 connects 12V input voltage.

6. remote tracing according to claim 5 controls formula safety box, it is characterized in that, the DC-DC/LDO power-switching circuit that described master board connects is by power management chip U5, step-down chip U3, one end is as input, the protective tube F2 that the other end is connected with the VIN pin of power management chip U5, positive pole is connected with the VIN pin of power management chip U5, the electric capacity C49 of minus earth, one end is connected with the negative pole of electric capacity C49, the inductance L 2 of other end ground connection, electric capacity C50 in parallel with electric capacity C49 respectively and electric capacity C51, be serially connected in the resistance R44 between the VIN pin of power management chip U5 and EN pin, be serially connected in the electric capacity C52 between the VIN pin of power management chip U5 and UGND pin, one end is connected with the VCC pin of power management chip U5, the electric capacity C53 of other end ground connection, N pole is connected with two LX pins of power management chip U5 simultaneously, the Zener diode D6 of P pole ground connection, one end is connected with the P pole of Zener diode D6, the electric capacity C55 that the other end is connected with the COMP pin of power management chip U5 through resistance R45, be serially connected in the electric capacity C54 between the COMP pin of power management chip U5 and GND pin, one end is connected with the LX pin of power management chip U5, the inductance L 3 that the other end is connected with the FB pin of power management chip U5 after resistance R46, the electric capacity C56 in parallel with resistance R46, be serially connected in the resistance R47 between the FB pin of power management chip U5 and GND pin, be serially connected in the resistance R48 between the IN pin of step-down chip U6 and EN pin, be serially connected in the electric capacity C61 between the IN pin of step-down chip U6 and GND pin, be serially connected in the electric capacity C57 between the IN pin of step-down chip U6 and GND pin respectively, electric capacity C58, electric capacity C59 and electric capacity C60, positive pole is connected with the OUT pin of step-down chip U6, the polar capacitor C63 that negative pole is connected with the BYP pin of step-down chip U6 after electric capacity C62, electric capacity C64 in parallel with polar capacitor C63 respectively, electric capacity C65, electric capacity C66, electric capacity C67, electric capacity C68, electric capacity C69 and electric capacity C70, and N pole ground connection, the LED 1 that P pole is connected with the positive pole of polar capacitor C63 after resistance R49 forms, wherein, the positive pole of electric capacity C49 connects 7.4V input voltage, the GND pin ground connection of power management chip U5, the IN pin of step-down chip U6 connects 3.8V input voltage and is connected with the tie point of inductance L 3 with resistance 46, the GND pin ground connection of step-down chip U6, the minus earth of polar capacitor C63, positive pole connect 3.3V input voltage.

7. remote tracing according to claim 6 controls formula safety box, it is characterized in that, described 3G/GPRS circuit is also provided with the 3G input power circuit be connected with 3G circuit, this 3G input power circuit is by metal-oxide-semiconductor Q1, one end is connected with 3G circuit, the resistance R50 that the other end is connected with the grid of metal-oxide-semiconductor Q1, one termination 3.8V input voltage, the resistance R51 that the other end is connected with the grid of metal-oxide-semiconductor Q1, one end is connected with the grid of metal-oxide-semiconductor Q1, the electric capacity C71 that the other end is connected with the drain electrode of metal-oxide-semiconductor Q1 after electric capacity C72, the electric capacity C73 in parallel with electric capacity C72, and the resistance R52 be serially connected between the drain electrode of metal-oxide-semiconductor Q1 and source electrode forms, wherein, the tie point ground connection of electric capacity C71 and electric capacity C72, the source electrode of metal-oxide-semiconductor Q1 connects in 3.8V input voltage, drain electrode and connects 3.8V input voltage.

8. remote tracing according to claim 7 controls formula safety box, it is characterized in that, described 3G/GPRS circuit is also provided with the GPRS input power circuit be connected with GPRS circuit, this GPRS input power circuit regulates chip U7 by voltage stabilizing, one end and voltage stabilizing regulate the VIN pin of chip U7 to be connected, the electric capacity C74 that the other end and voltage stabilizing regulate the GND pin of chip U7 to be connected, one end and voltage stabilizing regulate the EN pin of chip U7 to be connected, the resistance R53 that the other end and voltage stabilizing regulate the GND pin of chip U7 to be connected, positive pole and voltage stabilizing regulate the VOUT pin of chip U7 to be connected, the polar capacitor C77 of minus earth, and the electric capacity C75 in parallel with polar capacitor C77 and electric capacity C76 forms respectively, wherein, voltage stabilizing regulates on the VIN pin of chip U7 and connects 3.8V input voltage, EN pin is connected with GPRS circuit, GND pin ground connection, the positive pole of polar capacitor C77 connects 3V input voltage.

9. remote tracing according to claim 8 controls formula safety box, it is characterized in that, described main control singlechip model is STM32F103VET6, the model of son control single-chip microcomputer is STM32F051C8T6, the model of management of charging and discharging chip U1 is BQ24172RGYR-VQFN24, the model of power management chip U2, power management chip U4 and power management chip U5 is APW7080KAI-TRG, the model of step-down chip U3 and step-down chip U6 is MIC5219, and voltage stabilizing regulates the model of chip U7 to be SP6201.