CN104993754A - Double closed-loop-control direct-current speed regulation system based on loss suppression - Google Patents
Double closed-loop-control direct-current speed regulation system based on loss suppression Download PDFInfo
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- CN104993754A CN104993754A CN201510324055.2A CN201510324055A CN104993754A CN 104993754 A CN104993754 A CN 104993754A CN 201510324055 A CN201510324055 A CN 201510324055A CN 104993754 A CN104993754 A CN 104993754A
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Abstract
The invention discloses a double closed-loop-control direct-current speed regulation system based on loss suppression. The system is formed by a transformer T, a rectification filter circuit, a double closed-loop control circuit connected to an output terminal of the rectification filter circuit, a fine tuning circuit connected to the double closed-loop control circuit, a linear driving circuit connected to a secondary side of the transformer T, a voltage stabilizing circuit connected to the linear driving circuit, an operation amplification circuit connected to an output terminal of the voltage stabilizing circuit and an output circuit connected to an output terminal of the operation amplification circuit. The system is characterized in that a loss suppression circuit is arranged between the double closed-loop control circuit and the output circuit; the double closed-loop control circuit and the fine tuning circuit are connected to a primary side of the transformer T; the loss suppression circuit is formed by a suppression chip U3, a triode VT7, a triode VT8, a triode VT9 and the like. The loss suppression circuit is used in the invention. By using the circuit, losses during working are reduced so that a speed and accuracy of a speed regulation system are increased.
Description
Technical field
The present invention relates to electronic applications, specifically refer to a kind of double-closed-loop control Direct Current Governor System suppressed based on loss.
Background technology
At present, all mechanization is used in many activities in production, due to the requirement of machining and operation, make motor often be in the transient process of startup, braking, reversion, therefore to start and time in braking procedure determines mechanical production efficiency to a great extent.In order to shorten the time of this part, all the speed feedback single closed-loop KZ-D system of usage ratio integral controller realizes at present.But its dynamic and static performance of existing governing system is not fine, and stability is not high, is easily subject to the interference of electrical network, thus has an impact to the rotating speed of machinery.
Summary of the invention
The governing system stability that the object of the invention is to overcome current manufacturing machine is not high, to the defect that the rotating speed of machinery has an impact, provides a kind of dynamic and static functional, the double-closed-loop control Direct Current Governor System suppressed based on loss that stability is high.
Object of the present invention is achieved through the following technical solutions: a kind of double-closed-loop control Direct Current Governor System suppressed based on loss, by transformer T, current rectifying and wave filtering circuit, the Double-closed-loop control circuit be connected with rectification filter circuit output end, the trimming circuit be connected with Double-closed-loop control circuit, the linear drive circuit be connected with transformer T secondary, the voltage stabilizing circuit be connected with linear drive circuit, the operational amplification circuit be connected with circuit output end of pressure-stabilizing, the output circuit be connected with operational amplification circuit output, and between Double-closed-loop control circuit and output circuit, be also provided with loss suppression circuit composition, described Double-closed-loop control circuit and trimming circuit are all connected with the former limit of transformer T, described loss suppresses electric Route Flap Damping chip U3, triode VT7, triode VT8, triode VT9, positive pole is in turn through resistance R31, be connected with the emitter of triode VT8 after resistance R34, the polar capacitor C14 that negative pole is connected with Double-closed-loop control circuit after resistance R30, N pole is connected with suppressing the SW pin of chip U3 after resistance R23, P pole is in turn through resistance R33, diode D9, resistance R24, with the diode D8 suppressing the SENSE1 pin of chip U3 to be connected after polar capacitor C16, positive pole is connected with the base stage of triode VT7 after fusible resistor R32, the polar capacitor C15 that negative pole is connected with the pole of triode VT8 after resistance R35, positive pole is connected with the N pole of diode D8, negative pole and the polar capacitor C17 suppressing the IN pin of chip U3 to be connected, P pole is connected with suppressing the COMP pin of chip U3, the diode D10 that N pole is connected with the base stage of triode VT9 after variable resistor R27, negative pole is connected with suppressing the PWM pin of chip U3 after resistance R25, the polar capacitor C17 that positive pole is connected with the emitter of triode VT9 after resistance R26, P pole is connected with the collector electrode of triode VT9 after polar capacitor C13, N pole is in turn through resistance R29, with the diode D13 suppressing the VDD pin of chip U3 to be connected after diode D11, and P pole is connected with the collector electrode of triode VT8 after resistance R28, the diode D12 that N pole is connected with output circuit forms, the emitter of described triode VT7 is connected with the positive pole of polar capacitor C16, its collector electrode is then connected with the P pole of diode D10, the grounded collector of triode VT8, the SENSE2 pin of described suppression chip U3 is connected with the tie point of resistance R24 with diode D9, its GND pin ground connection, its PWM pin are also connected with the P pole of diode D12 with the N pole of diode D13 simultaneously.
Described linear drive circuit is by driving chip U2, triode VT3, triode VT4, triode VT5, triode VT6, positive pole is connected with the Same Name of Ends of transformer T secondary inductance coil L3, the polar capacitor C10 that negative pole is connected with the IN1 pin of driving chip U2 after resistance R16, one end is connected with the collector electrode of triode VT6, the resistance R17 that the other end is connected with the base stage of triode VT3 after resistance R18, positive pole is connected with the base stage of triode VT6, the polar capacitor C12 that negative pole is connected with the IN1 pin of driving chip U2, positive pole is connected with the IN2 pin of driving chip U2, the polar capacitor C11 of minus earth, one end is connected with the emitter of triode VT6, the resistance R20 that the other end is connected with the base stage of triode VT5, one end is connected with the base stage of triode VT5, the resistance R19 that the other end is connected with the base stage of triode VT3, N pole is connected with the collector electrode of triode VT6, the diode D6 that P pole is connected with the collector electrode of triode VT5, positive terminal is connected with the collector electrode of triode VT6, the not gate K that end of oppisite phase is connected with triode VT4 collector electrode, one end is connected with triode VT4 emitter, the resistance R22 that the other end is connected with the emitter of triode VT3 after resistance R21, the end of oppisite phase of P pole NAND gate K is connected, the diode D7 that N pole is connected with the tie point of resistance R22 with resistance R21 forms, the VCC pin of described driving chip U2 is connected with the base stage of triode VT6, END pin ground connection, OUT pin are connected with the collector electrode of triode VT5, the collector electrode of triode VT5 is also connected with the base stage of triode VT4, its emitter is connected with the base stage of triode man VT3, the grounded collector of triode VT3, the N pole of diode D7 is connected with voltage stabilizing circuit.
Described current rectifying and wave filtering circuit comprises fuse FU1, fuse FU2, diode bridge rectifier U, electric capacity C0; Fuse FU1 and fuse FU2 are connected with two inputs of diode bridge rectifier U respectively, and one end of electric capacity C0 is simultaneously with the output of diode bridge rectifier U and Double-closed-loop control circuit is connected, other end ground connection; Another output head grounding of described diode bridge rectifier U.
Described Double-closed-loop control circuit is by control chip U1, field effect transistor MOS, one end is connected with electric capacity C0, the resistance R4 that the other end is connected with the VCC pin of control chip U1 after potentiometer R5, N pole is connected with the tie point of potentiometer R5 with resistance R4, the diode D1 that P pole is connected with the Same Name of Ends of transformer T former limit inductance coil L2, one end is connected with the N pole of diode D1, the electric capacity C1 of other end ground connection, one end is connected with the N pole of diode D1, the resistance R1 of other end ground connection after resistance R2, one end is connected with the COMP pin of control chip U1, the electric capacity C2 that the other end is connected with the tie point of resistance R2 with resistance R1, one end is connected with the VREF pin of control chip U1, the electric capacity C3 of other end ground connection, one end is connected with the VREF pin of control chip U1, the other end is in parallel with electric capacity C3 resistance R3 after electric capacity C4, one end is connected with the GD pin of control chip U1, the resistance R7 that the other end is connected with the grid of field effect transistor MOS, one end is connected with the grid of field effect transistor MOS, the resistance R8 of other end ground connection, one end is connected with the IS pin of control chip U1, the resistance R9 of other end ground connection after resistance R10, and one end is connected with the IS pin of control chip U1, the electric capacity C5 of other end ground connection forms, the drain electrode of described field effect transistor MOS is connected with the Same Name of Ends of inductance coil L2 with the non-same polarity of transformer T former limit inductance coil L1 respectively, and its source electrode is then connected with the tie point of resistance R10 with resistance R9, the VFB pin of control chip U1 is connected with the tie point of resistance R2 with resistance R1, and its RC pin is connected with the tie point of electric capacity C4 with resistance R3, its GND pin ground connection, the non-same polarity ground connection of described transformer T former limit inductance coil L2, the source electrode of described field effect transistor MOS is also connected with the negative pole of electric capacity C14 after resistance R31, described control chip U1 is NE556 integrated chip.
Described trimming circuit is by diode D2, and electric capacity C6, resistance R6 form; Its P pole is got back in the N pole of diode D2 after electric capacity C6 and resistance R6; The P pole of described diode D2 is connected with the tie point of resistance R4 and the Same Name of Ends of transformer T former limit inductance coil L1 with electric capacity C0 simultaneously, and its N pole is then connected with the Same Name of Ends of transformer T former limit inductance coil L1; Resistance R6 is connected with the non-same polarity of transformer T former limit inductance coil L1 with the tie point of electric capacity C6.
Described voltage stabilizing circuit is by voltage stabilizing didoe D4, and resistance R11, electric capacity C7, diode D3 form; Its P pole is got back in the N pole of voltage stabilizing didoe D4 after resistance R11 and electric capacity C7; The N pole of diode D3 is connected with the tie point of electric capacity C7 with resistance R11, and its P pole is then connected with the non-same polarity of transformer T secondary inductance coil L3; The N pole of voltage stabilizing didoe D4 is also connected with output circuit, and its P pole is then connected with the N pole of output circuit and diode D7 simultaneously.
Described operational amplification circuit comprises operational amplifier P1, operational amplifier P2, resistance R13, resistance R12, diode D5, electric capacity C8, electric capacity C9; The negative pole ground connection after resistance R13 and diode D5 and electric capacity C8 in turn of operational amplifier P1, its positive pole is connected with the P pole of voltage stabilizing didoe D4, and output stage is then connected with the positive pole of operational amplifier P2; The negative pole of described operational amplifier P2 is connected with its output stage; Between the positive pole that resistance R12 is serially connected in operational amplifier P1 and output stage; One end of electric capacity C9 is connected with the output of operational amplifier P2, and its other end is then connected with output circuit with the P pole of voltage stabilizing didoe D4 simultaneously.
Described output circuit by triode VT1, triode VT2, and the resistance R15 that one end is connected with the collector electrode of triode VT2, the other end is then connected with the N pole of voltage stabilizing didoe D4 after resistance R14 forms; The base stage of described triode VT2 is connected with the N pole of voltage stabilizing didoe D4, grounded emitter; The base stage of triode VT1 is connected with the N pole of diode D12 with the P pole of voltage stabilizing didoe D4 simultaneously, and its collector electrode is connected with the base stage of triode VT2, and its emitter is then connected with the emitter of triode VT2.
For guaranteeing result of use of the present invention, described driving chip U2 is LM387 integrated chip; Described suppression chip U3 is SD42560 integrated chip.
The present invention comparatively prior art compares, and has the following advantages and beneficial effect:
(1) the present invention is provided with loss suppression circuit, and this circuit can be the electric current and voltage that governing system provides stable, reduces loss during its acting, thus improves speed and the accuracy of governing system.
(2) the present invention adopts linear drive circuit, makes governing system more stable.
(3) the present invention adopts Double-closed-loop control circuit, makes system more stable by its effect, and electrical network can be suppressed to disturb impact on motor speed, makes motor start-up, braking, reversion more smooth and easy, enhances productivity.
(4) Double-closed-loop control circuit of the present invention can also use as switching power circuit, has protective effect to system, prevents because overtension causes damage to system and motor.
Accompanying drawing explanation
Fig. 1 is overall structure schematic diagram of the present invention.
Fig. 2 is the structural representation of linear drive circuit of the present invention.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited thereto.
Embodiment
As shown in Figure 1, the present invention is by transformer T, current rectifying and wave filtering circuit, the Double-closed-loop control circuit be connected with rectification filter circuit output end, the trimming circuit be connected with Double-closed-loop control circuit, the linear drive circuit be connected with transformer T secondary, the voltage stabilizing circuit be connected with linear drive circuit, the operational amplification circuit be connected with circuit output end of pressure-stabilizing, the output circuit be connected with operational amplification circuit output, and between Double-closed-loop control circuit and output circuit, be also provided with loss suppression circuit composition.Wherein, described Double-closed-loop control circuit and trimming circuit are all connected with the former limit of transformer T.
Described loss suppresses electric Route Flap Damping chip U3, triode VT7, triode VT8, triode VT9, resistance R23, resistance R24, resistance R25, resistance R26, resistance R27, resistance R28, resistance R29, resistance R30, resistance R31, resistance R32, resistance R33, resistance R34, resistance R35, diode D8, diode D9, diode D10, diode D11, diode D12, diode D13, polar capacitor C13, polar capacitor C14, polar capacitor C15, polar capacitor C16, polar capacitor C17, and polar capacitor C18 forms.
During connection, the positive pole of polar capacitor C14 is connected with the emitter of triode VT8 in turn after resistance R31, resistance R34, negative pole is connected with Double-closed-loop control circuit after resistance R30.The N pole of diode D8 is connected with the SW pin of suppression chip U3 after resistance R23, P pole is connected with suppressing the SENSE1 pin of chip U3 in turn after resistance R33, diode D9, resistance R24, polar capacitor C16.
Wherein, the positive pole of polar capacitor C15 is connected with the base stage of triode VT7 after fusible resistor R32, negative pole is connected with the pole of triode VT8 after resistance R35.The positive pole of polar capacitor C17 is connected with the N pole of diode D8, negative pole is connected with the IN pin of suppression chip U3.The P pole of diode D10 is connected with the COMP pin of suppression chip U3, N pole is connected with the base stage of triode VT9 after variable resistor R27.The negative pole of polar capacitor C17 is connected with the PWM pin of suppression chip U3 after resistance R25, positive pole is connected with the emitter of triode VT9 after resistance R26.
The P pole of diode D13 is connected with the collector electrode of triode VT9 after polar capacitor C13, N pole is connected with suppressing the VDD pin of chip U3 in turn after resistance R29, diode D11.The P pole of diode D12 is connected with the collector electrode of triode VT8 after resistance R28, N pole is connected with output circuit.
For better implementing the present invention, described suppression chip U3 is SD42560 integrated chip, and this integrated chip has the functions such as overtemperature prote, overcurrent protection, constant current, voltage regulate automatically.Its input voltage range is 5 ~ 36V, and operating current is 1.5 ~ 2mA, and when input/output voltage changes, the change of full voltage range output current controls within ± 0.5 ﹪.This integrated chip effectively can suppress the useless acting loss of governing system, thus the speed governing that improve this system is more accurate.
During enforcement, the emitter of described triode VT7 is connected with the positive pole of polar capacitor C16, its collector electrode is then connected with the P pole of diode D10, the grounded collector of triode VT8; The SENSE2 pin of described suppression chip U3 is connected with the tie point of resistance R24 with diode D9, its GND pin ground connection, its PWM pin are also connected with the P pole of diode D12 with the N pole of diode D13 simultaneously;
As shown in Figure 2, described linear drive circuit is by driving chip U2, triode VT3, triode VT4, triode VT5, triode VT6, positive pole is connected with the Same Name of Ends of transformer T secondary inductance coil L3, the polar capacitor C10 that negative pole is connected with the IN1 pin of driving chip U2 after resistance R16, one end is connected with the collector electrode of triode VT6, the resistance R17 that the other end is connected with the base stage of triode VT3 after resistance R18, positive pole is connected with the base stage of triode VT6, the polar capacitor C12 that negative pole is connected with the IN1 pin of driving chip U2, positive pole is connected with the IN2 pin of driving chip U2, the polar capacitor C11 of minus earth, one end is connected with the emitter of triode VT6, the resistance R20 that the other end is connected with the base stage of triode VT5, one end is connected with the base stage of triode VT5, the resistance R19 that the other end is connected with the base stage of triode VT3, N pole is connected with the collector electrode of triode VT6, the diode D6 that P pole is connected with the collector electrode of triode VT5, positive terminal is connected with the collector electrode of triode VT6, the not gate K that end of oppisite phase is connected with triode VT4 collector electrode, one end is connected with triode VT4 emitter, the resistance R22 that the other end is connected with the emitter of triode VT3 after resistance R21, the end of oppisite phase of P pole NAND gate K is connected, the diode D7 that N pole is connected with the tie point of resistance R22 with resistance R21 forms.
The VCC pin of described driving chip U2 is connected with the base stage of triode VT6, END pin ground connection, OUT pin are connected with the collector electrode of triode VT5, the collector electrode of triode VT5 is also connected with the base stage of triode VT4, its emitter is connected with the base stage of triode man VT3, the grounded collector of triode VT3, the N pole of diode D7 is connected with voltage stabilizing circuit.
The present invention adopts linear drive circuit, makes governing system more stable.In order to ensure implementation result, described driving chip U is preferably LM387 integrated chip, its highly sensitive and low price.
Described current rectifying and wave filtering circuit by fuse FU1, fuse FU2, diode bridge rectifier U, and electric capacity C0 forms.
During connection, fuse FU1 and fuse FU2 are connected with two inputs of diode bridge rectifier U respectively, and one end of electric capacity C0 is simultaneously with the output of diode bridge rectifier U and Double-closed-loop control circuit is connected, other end ground connection.Another output head grounding of described diode bridge rectifier U.
Described Double-closed-loop control circuit is by control chip U1, field effect transistor MOS, one end is connected with electric capacity C0, the resistance R4 that the other end is connected with the VCC pin of control chip U1 after potentiometer R5, N pole is connected with the tie point of potentiometer R5 with resistance R4, the diode D1 that P pole is connected with the Same Name of Ends of transformer T former limit inductance coil L2, one end is connected with the N pole of diode D1, the electric capacity C1 of other end ground connection, one end is connected with the N pole of diode D1, the resistance R1 of other end ground connection after resistance R2, one end is connected with the COMP pin of control chip U1, the electric capacity C2 that the other end is connected with the tie point of resistance R2 with resistance R1, one end is connected with the VREF pin of control chip U1, the electric capacity C3 of other end ground connection, one end is connected with the VREF pin of control chip U1, the other end is in parallel with electric capacity C3 resistance R3 after electric capacity C4, one end is connected with the GD pin of control chip U1, the resistance R7 that the other end is connected with the grid of field effect transistor MOS, one end is connected with the grid of field effect transistor MOS, the resistance R8 of other end ground connection, one end is connected with the IS pin of control chip U1, the resistance R9 of other end ground connection after resistance R10, and one end is connected with the IS pin of control chip U1, the electric capacity C5 of other end ground connection forms.
The drain electrode of described field effect transistor MOS is connected with the Same Name of Ends of inductance coil L2 with the non-same polarity of transformer T former limit inductance coil L1 respectively, and its source electrode is then connected with the tie point of resistance R10 with resistance R9; The VFB pin of control chip U1 is connected with the tie point of resistance R2 with resistance R1, and its RC pin is connected with the tie point of electric capacity C4 with resistance R3, its GND pin ground connection.
The non-same polarity ground connection of described transformer T former limit inductance coil L2; The source electrode of described field effect transistor MOS is also connected with the negative pole of electric capacity C14 after resistance R31
For better implementing the present invention, described control chip U1 is NE556 integrated chip.Described trimming circuit by diode D2, electric capacity C6, and resistance R6 forms.
During enforcement, its P pole is got back in the N pole of diode D2 after electric capacity C6 and resistance R6; The P pole of described diode D2 is connected with the tie point of resistance R4 and the Same Name of Ends of transformer T former limit inductance coil L1 with electric capacity C0 simultaneously, and its N pole is then connected with the Same Name of Ends of transformer T former limit inductance coil L1
Further, resistance R6 is connected with the non-same polarity of transformer T former limit inductance coil L1 with the tie point of electric capacity C6.Described voltage stabilizing circuit by voltage stabilizing didoe D4, resistance R11, electric capacity C7, and diode D3 forms.
During connection, its P pole is got back in the N pole of voltage stabilizing didoe D4 after resistance R11 and electric capacity C7; The N pole of diode D3 is connected with the tie point of electric capacity C7 with resistance R11, and its P pole is then connected with the non-same polarity of transformer T secondary inductance coil L3; The N pole of voltage stabilizing didoe D4 is also connected with output circuit, and its P pole is then connected with the N pole of output circuit and diode D7 simultaneously.
Described operational amplification circuit by operational amplifier P1, operational amplifier P2, resistance R13, resistance R12, diode D5, electric capacity C8, and electric capacity C9 forms.
During enforcement, the negative pole ground connection after resistance R13 and diode D5 and electric capacity C8 in turn of operational amplifier P1, its positive pole is connected with the P pole of voltage stabilizing didoe D4, and output stage is then connected with the positive pole of operational amplifier P2.
The negative pole of described operational amplifier P2 is connected with its output stage; Between the positive pole that resistance R12 is serially connected in operational amplifier P1 and output stage; One end of electric capacity C9 is connected with the output of operational amplifier P2, and its other end is then connected with output circuit with the P pole of voltage stabilizing didoe D4 simultaneously.
Described output circuit by triode VT1, triode VT2, and the resistance R15 that one end is connected with the collector electrode of triode VT2, the other end is then connected with the N pole of voltage stabilizing didoe D4 after resistance R14 forms.
The base stage of described triode VT2 is connected with the N pole of voltage stabilizing didoe D4, grounded emitter; The base stage of triode VT1 is connected with the N pole of diode D12 with the P pole of voltage stabilizing didoe D4 simultaneously, and its collector electrode is connected with the base stage of triode VT2, and its emitter is then connected with the emitter of triode VT2.
As mentioned above, just the present invention can well be realized.
Claims (8)
1. the double-closed-loop control Direct Current Governor System suppressed based on loss, by transformer T, current rectifying and wave filtering circuit, the Double-closed-loop control circuit be connected with rectification filter circuit output end, the trimming circuit be connected with Double-closed-loop control circuit, the linear drive circuit be connected with transformer T secondary, the voltage stabilizing circuit be connected with linear drive circuit, the operational amplification circuit be connected with circuit output end of pressure-stabilizing, and the output circuit be connected with operational amplification circuit output forms, it is characterized in that: between Double-closed-loop control circuit and output circuit, be also provided with loss suppress circuit, described Double-closed-loop control circuit and trimming circuit are all connected with the former limit of transformer T, described loss suppresses electric Route Flap Damping chip U3, triode VT7, triode VT8, triode VT9, positive pole is in turn through resistance R31, be connected with the emitter of triode VT8 after resistance R34, the polar capacitor C14 that negative pole is connected with Double-closed-loop control circuit after resistance R30, N pole is connected with suppressing the SW pin of chip U3 after resistance R23, P pole is in turn through resistance R33, diode D9, resistance R24, with the diode D8 suppressing the SENSE1 pin of chip U3 to be connected after polar capacitor C16, positive pole is connected with the base stage of triode VT7 after fusible resistor R32, the polar capacitor C15 that negative pole is connected with the pole of triode VT8 after resistance R35, positive pole is connected with the N pole of diode D8, negative pole and the polar capacitor C17 suppressing the IN pin of chip U3 to be connected, P pole is connected with suppressing the COMP pin of chip U3, the diode D10 that N pole is connected with the base stage of triode VT9 after variable resistor R27, negative pole is connected with suppressing the PWM pin of chip U3 after resistance R25, the polar capacitor C17 that positive pole is connected with the emitter of triode VT9 after resistance R26, P pole is connected with the collector electrode of triode VT9 after polar capacitor C13, N pole is in turn through resistance R29, with the diode D13 suppressing the VDD pin of chip U3 to be connected after diode D11, and P pole is connected with the collector electrode of triode VT8 after resistance R28, the diode D12 that N pole is connected with output circuit forms, the emitter of described triode VT7 is connected with the positive pole of polar capacitor C16, its collector electrode is then connected with the P pole of diode D10, the grounded collector of triode VT8, the SENSE2 pin of described suppression chip U3 is connected with the tie point of resistance R24 with diode D9, its GND pin ground connection, its PWM pin are also connected with the P pole of diode D12 with the N pole of diode D13 simultaneously,
Described linear drive circuit is by driving chip U2, triode VT3, triode VT4, triode VT5, triode VT6, positive pole is connected with the Same Name of Ends of transformer T secondary inductance coil L3, the polar capacitor C10 that negative pole is connected with the IN1 pin of driving chip U2 after resistance R16, one end is connected with the collector electrode of triode VT6, the resistance R17 that the other end is connected with the base stage of triode VT3 after resistance R18, positive pole is connected with the base stage of triode VT6, the polar capacitor C12 that negative pole is connected with the IN1 pin of driving chip U2, positive pole is connected with the IN2 pin of driving chip U2, the polar capacitor C11 of minus earth, one end is connected with the emitter of triode VT6, the resistance R20 that the other end is connected with the base stage of triode VT5, one end is connected with the base stage of triode VT5, the resistance R19 that the other end is connected with the base stage of triode VT3, N pole is connected with the collector electrode of triode VT6, the diode D6 that P pole is connected with the collector electrode of triode VT5, positive terminal is connected with the collector electrode of triode VT6, the not gate K that end of oppisite phase is connected with triode VT4 collector electrode, one end is connected with triode VT4 emitter, the resistance R22 that the other end is connected with the emitter of triode VT3 after resistance R21, the end of oppisite phase of P pole NAND gate K is connected, the diode D7 that N pole is connected with the tie point of resistance R22 with resistance R21 forms, the VCC pin of described driving chip U2 is connected with the base stage of triode VT6, END pin ground connection, OUT pin are connected with the collector electrode of triode VT5, the collector electrode of triode VT5 is also connected with the base stage of triode VT4, its emitter is connected with the base stage of triode man VT3, the grounded collector of triode VT3, the N pole of diode D7 is connected with voltage stabilizing circuit.
2. a kind of double-closed-loop control Direct Current Governor System suppressed based on loss according to claim 1, is characterized in that: described current rectifying and wave filtering circuit comprises fuse FU1, fuse FU2, diode bridge rectifier U, electric capacity C0; Fuse FU1 and fuse FU2 are connected with two inputs of diode bridge rectifier U respectively, and one end of electric capacity C0 is simultaneously with the output of diode bridge rectifier U and Double-closed-loop control circuit is connected, other end ground connection; Another output head grounding of described diode bridge rectifier U.
3. a kind of double-closed-loop control Direct Current Governor System suppressed based on loss according to claim 2, it is characterized in that: described Double-closed-loop control circuit is by control chip U1, field effect transistor MOS, one end is connected with electric capacity C0, the resistance R4 that the other end is connected with the VCC pin of control chip U1 after potentiometer R5, N pole is connected with the tie point of potentiometer R5 with resistance R4, the diode D1 that P pole is connected with the Same Name of Ends of transformer T former limit inductance coil L2, one end is connected with the N pole of diode D1, the electric capacity C1 of other end ground connection, one end is connected with the N pole of diode D1, the resistance R1 of other end ground connection after resistance R2, one end is connected with the COMP pin of control chip U1, the electric capacity C2 that the other end is connected with the tie point of resistance R2 with resistance R1, one end is connected with the VREF pin of control chip U1, the electric capacity C3 of other end ground connection, one end is connected with the VREF pin of control chip U1, the other end is in parallel with electric capacity C3 resistance R3 after electric capacity C4, one end is connected with the GD pin of control chip U1, the resistance R7 that the other end is connected with the grid of field effect transistor MOS, one end is connected with the grid of field effect transistor MOS, the resistance R8 of other end ground connection, one end is connected with the IS pin of control chip U1, the resistance R9 of other end ground connection after resistance R10, and one end is connected with the IS pin of control chip U1, the electric capacity C5 of other end ground connection forms, the drain electrode of described field effect transistor MOS is connected with the Same Name of Ends of inductance coil L2 with the non-same polarity of transformer T former limit inductance coil L1 respectively, and its source electrode is then connected with the tie point of resistance R10 with resistance R9, the VFB pin of control chip U1 is connected with the tie point of resistance R2 with resistance R1, and its RC pin is connected with the tie point of electric capacity C4 with resistance R3, its GND pin ground connection, the non-same polarity ground connection of described transformer T former limit inductance coil L2, the source electrode of described field effect transistor MOS is also connected with the negative pole of electric capacity C14 after resistance R31, described control chip U1 is NE556 integrated chip.
4. a kind of double-closed-loop control Direct Current Governor System suppressed based on loss according to claim 3, is characterized in that: described trimming circuit is by diode D2, and electric capacity C6, resistance R6 form; Its P pole is got back in the N pole of diode D2 after electric capacity C6 and resistance R6; The P pole of described diode D2 is connected with the tie point of resistance R4 and the Same Name of Ends of transformer T former limit inductance coil L1 with electric capacity C0 simultaneously, and its N pole is then connected with the Same Name of Ends of transformer T former limit inductance coil L1; Resistance R6 is connected with the non-same polarity of transformer T former limit inductance coil L1 with the tie point of electric capacity C6.
5. a kind of double-closed-loop control Direct Current Governor System suppressed based on loss according to claim 4, is characterized in that: described voltage stabilizing circuit is by voltage stabilizing didoe D4, and resistance R11, electric capacity C7, diode D3 form; Its P pole is got back in the N pole of voltage stabilizing didoe D4 after resistance R11 and electric capacity C7; The N pole of diode D3 is connected with the tie point of electric capacity C7 with resistance R11, and its P pole is then connected with the non-same polarity of transformer T secondary inductance coil L3; The N pole of voltage stabilizing didoe D4 is also connected with output circuit, and its P pole is then connected with the N pole of output circuit and diode D7 simultaneously.
6. a kind of double-closed-loop control Direct Current Governor System suppressed based on loss according to claim 5, is characterized in that: described operational amplification circuit comprises operational amplifier P1, operational amplifier P2, resistance R13, resistance R12, diode D5, electric capacity C8, electric capacity C9; The negative pole ground connection after resistance R13 and diode D5 and electric capacity C8 in turn of operational amplifier P1, its positive pole is connected with the P pole of voltage stabilizing didoe D4, and output stage is then connected with the positive pole of operational amplifier P2; The negative pole of described operational amplifier P2 is connected with its output stage; Between the positive pole that resistance R12 is serially connected in operational amplifier P1 and output stage; One end of electric capacity C9 is connected with the output of operational amplifier P2, and its other end is then connected with output circuit with the P pole of voltage stabilizing didoe D4 simultaneously.
7. a kind of double-closed-loop control Direct Current Governor System suppressed based on loss according to claim 6, it is characterized in that: described output circuit is by triode VT1, triode VT2, and the resistance R15 that one end is connected with the collector electrode of triode VT2, the other end is then connected with the N pole of voltage stabilizing didoe D4 after resistance R14 forms; The base stage of described triode VT2 is connected with the N pole of voltage stabilizing didoe D4, grounded emitter; The base stage of triode VT1 is connected with the N pole of diode D12 with the P pole of voltage stabilizing didoe D4 simultaneously, and its collector electrode is connected with the base stage of triode VT2, and its emitter is then connected with the emitter of triode VT2.
8. a kind of double-closed-loop control Direct Current Governor System suppressed based on loss according to any one of claim 1 ~ 7, is characterized in that: described driving chip U2 is LM387 integrated chip; Described suppression chip U3 is SD42560 integrated chip.
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| CN201510324055.2A CN104993754A (en) | 2014-11-29 | 2015-06-14 | Double closed-loop-control direct-current speed regulation system based on loss suppression |
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| CN201410715298.4A CN104467569A (en) | 2014-11-29 | 2014-11-29 | Double closed loop control direct-current speed regulation system based on linear driving |
| CN201510324055.2A CN104993754A (en) | 2014-11-29 | 2015-06-14 | Double closed-loop-control direct-current speed regulation system based on loss suppression |
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| CN201510324055.2A Withdrawn CN104993754A (en) | 2014-11-29 | 2015-06-14 | Double closed-loop-control direct-current speed regulation system based on loss suppression |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105307362A (en) * | 2015-12-02 | 2016-02-03 | 成都思博特科技有限公司 | Sound control energy saving illumination system based on noise reduction circuit and linear driving circuit |
| CN108696212A (en) * | 2017-03-31 | 2018-10-23 | 三星电机株式会社 | Equipment for driving actuator |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104467569A (en) * | 2014-11-29 | 2015-03-25 | 成都思茂科技有限公司 | Double closed loop control direct-current speed regulation system based on linear driving |
| CN104898552A (en) * | 2015-03-30 | 2015-09-09 | 成都颉隆科技有限公司 | Closed-Loop machine tool control system based on precise positioning |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101720150A (en) * | 2008-10-09 | 2010-06-02 | 夏普株式会社 | LED drive circuit, LED illumination component, LED illumination device, and LED illumination system |
| CN104467569A (en) * | 2014-11-29 | 2015-03-25 | 成都思茂科技有限公司 | Double closed loop control direct-current speed regulation system based on linear driving |
-
2014
- 2014-11-29 CN CN201410715298.4A patent/CN104467569A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101720150A (en) * | 2008-10-09 | 2010-06-02 | 夏普株式会社 | LED drive circuit, LED illumination component, LED illumination device, and LED illumination system |
| CN104467569A (en) * | 2014-11-29 | 2015-03-25 | 成都思茂科技有限公司 | Double closed loop control direct-current speed regulation system based on linear driving |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105307362A (en) * | 2015-12-02 | 2016-02-03 | 成都思博特科技有限公司 | Sound control energy saving illumination system based on noise reduction circuit and linear driving circuit |
| CN108696212A (en) * | 2017-03-31 | 2018-10-23 | 三星电机株式会社 | Equipment for driving actuator |
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