CN104991758B - A kind of bit field cladding system and operating method - Google Patents
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Abstract
A kind of bit field cladding system of the present invention and operating method, bit field cladding system includes the first code translator, second code translator, shift unit, position selection device, adder and selector group, prospect value is obtained by shift unit, final sign bit is obtained by position selection device, background position selection signal is obtained by the first code translator, sign bit selection signal is obtained by adder and the second code translator, selector group is according to sign extended enable signal, background position selection signal and sign bit selection signal, to prospect value, value in final sign bit and background register is selected, obtain a result.Energy quick response bit field overlapping operation of the invention, and there is optional sign extended function.
Description
Technical field
The invention belongs to digital processing field, more particularly to a kind of bit field cladding system of quick optional sign extended
And operating method.
Background technology
Digital signal processor is mainly usually used in the special dimension for needing mass data quickly to handle.Communication, password now
The development of the ambits such as, image procossing, biometer mathematics all demand processors can carry out quick bit field operation.
So-called bit field operation is the operation relative to other in processor towards " word " (Word), and its operating force is ratio
It is special.Common shift instruction, "AND", "or", " non-" instruction are bit field operation, but its is simple to operate, each in " word "
It is individual all to have carried out identical operation.Now, in the harsh enterprise of some requirements and technical applications, some are towards high-end market
General processor have also been introduced some advanced bit field operational orders, such as Intel Itanium series processors.And
In Digital Signal Processing, advanced bit field instruction is then relatively common.The bit field extraction instruction of zero extension or sign extended is common
Advanced bit field operational order, and bit field covering instruction is instructed also at some numerals as the reverse operating of bit field extraction instruction
Occur in reason device.
The executive mode of bit field overlapping operation is had nothing in common with each other in current digital signal processor, and instruction is covered without bit field
Processor needs other a plurality of bit field operational orders to be used in combination and could complete；The bit field instruction of some processors uses existing
The arithmetic elements such as shift unit adder, by the realization in multiple cycles, when particularly realizing sign extended function, some processors
Realized using 32 adder so that instruction realizes that the time is longer (referring to ARM patent US7370180B2).It is so more
Processor instruction set define bit field covering instruction do not support sign extended, such as ARM Cortex-M3 instruction set；Certain
A little bit fields for supporting sign extended cover the processor of instruction, and the instruction is also required to multiple cycles realizations.
The content of the invention
(1) technical problems to be solved
The present invention for existing processor can not the quick response bit field overlapping operation with sign extended function ask
Topic, there is provided a quick bit field cladding system and operating method, and there is optional sign extended function.
(2) technical scheme
The present invention provides a kind of bit field cladding system, and for processor, the processor includes prospect register and background
Register, it is characterised in that bit field cladding system includes the first code translator, the second code translator, shift unit, position selection dress
Put, adder and selector group, wherein：
Value in prospect register is moved to left according to covering original position, obtains prospect value by shift unit；
Position selection device is selected to need the sign bit extended in prospect register, originated according to covering according to overlay length
Sign bit in position selection background register, and determine final sign bit from two sign bits of selection；
First code translator enters row decoding to covering original position, obtains background position selection signal；
Adder calculate overlay length with cover original position and, obtain and be worth；
Second code translator pair and it is worth into row decoding, obtains sign bit selection signal；
Selector group according to sign extended enable signal, background position selection signal and sign bit selection signal, to prospect value,
Value in the final sign bit and background register is selected, and is obtained a result.
The present invention also provides a kind of bit field overlapping operation method, including：
S1, according to covering original position, the value in prospect register is moved to left, obtains prospect value；
S2, while step S1 is carried out, according to overlay length, select to need the sign bit extended in prospect register,
According to the sign bit in covering original position selection background register, and final sign bit is determined from two sign bits；
S3, while step S1 is carried out, row decoding is entered to the covering original position, obtains background position selection signal；
S4, while step S1 is carried out, calculate overlay length with cover original position and, and to it is described and value progress
Decoding, obtains sign bit selection signal；
S5, according to sign extended enable signal, background position selection signal and the sign bit selection signal, to described
Value in prospect value, the final sign bit and background register is selected, and is obtained a result.
(3) beneficial effect
Bit field cladding system provided by the invention and operating method, existing shift module in processor is borrowed, reduced
The use of standard block, reduces area, reduces power consumption；Whole logical operation is highly-parallel, at data signal
Manage in device, can be finished within a cycle, this simplifies the pipeline design, improves execution efficiency；Selected using position
Device is selected, can obtain needing the sign bit extended parallel while displacement, using extension enable signal selection sign bit, than being not required to
The only more delays of one-level " selector " of the bit field overlapping operation to be extended.
Brief description of the drawings
Fig. 1 is the exemplary plot of bit field overlapping operation in the embodiment of the present invention.
Fig. 2 is the structure chart of the bit field cladding system in the embodiment of the present invention.
Embodiment
The present invention provides a kind of bit field cladding system, including the first code translator, the second code translator, shift unit, position choosing
Device, adder and selector group are selected, prospect value is obtained by shift unit, final sign bit is obtained by position selection device, is led to
Cross the first code translator and obtain background position selection signal, sign bit selection signal is obtained by adder and the second code translator,
Selector group is according to sign extended enable signal, background position selection signal and sign bit selection signal, to prospect value, final symbol
Value in position and background register is selected, and is obtained a result.
In one embodiment, the value in prospect register is moved to left, obtained according to covering original position by shift unit
To prospect value；Position selection device is selected to need the sign bit extended in prospect register, originated according to covering according to overlay length
Sign bit in position selection background register, and determine final sign bit from two sign bits of selection；First decoding dress
Put and row decoding is entered to the covering original position, obtain background position selection signal；Adder calculates the overlay length and covering
The sum of original position, obtain and be worth, the second code translator pair and be worth into row decoding, obtain sign bit selection signal.
In one embodiment, the first code translator includes the first decoder and the first phase inverter, the first decoder pair
After covering original position enters row decoding, the first phase inverter carries out reversely, obtaining background position selection signal to decoding result.
In one embodiment, position selection device includes the first digit selector, the second digit selector and sign bit selection
Device, the first digit selector select to need the sign bit that extends in prospect register according to overlay length, the second digit selector according to
The sign bit in original position selection background register is covered, symbol digit selector is according to overlay length, from two symbols of selection
Final sign bit is determined in number position.
In one embodiment, when overlay length is equal to 0, symbol digit selector selects the output of the first digit selector
Sign bit, otherwise, symbol digit selector select the sign bit of the second digit selector output.
In one embodiment, adder also exports a carry value.
In one embodiment, the second code translator include the second decoder, the second reverser and with door, wherein, the
Two decoders pair and it is worth into after row decoding, is input to an input with door, the second reverser enters to the carry value of adder
After row is reverse, another input with door is input to, with input progress and computing of the door to its input, obtains sign bit choosing
Select signal.
In one embodiment, selector group includes first selector, second selector and third selector, prospect value
And the value in background register is separately input into the input of first selector, background position selection signal is inputted to the first choosing
Select the control terminal of device；Value in final sign bit and the background register is separately input into the input of the second selector
End, an extension enable signal is inputted to the control terminal of second selector；The output end of first selector and second selector
The input of third selector is connect, sign bit selection signal is inputted to the control terminal of third selector.
The present invention also provides a kind of bit field overlapping operation method, including：
S1, according to covering original position, the value in prospect register is moved to left, obtains prospect value；
S2, while step S1 is carried out, according to overlay length, select to need the sign bit extended in prospect register,
According to the sign bit in covering original position selection background register, and final sign bit is determined from two sign bits；
S3, while step S1 is carried out, row decoding is entered to the covering original position, obtains background position selection signal；
S4, while step S1 is carried out, calculate overlay length with cover original position and, and to it is described and value progress
Decoding, obtains sign bit selection signal；
S5, according to sign extended enable signal, background position selection signal and the sign bit selection signal, to described
Value in prospect value, the final sign bit and background register is selected, and is obtained a result.
For the object, technical solutions and advantages of the present invention are more clearly understood, below in conjunction with specific embodiment, and reference
Accompanying drawing, the present invention is described in more detail.
Fig. 1 is the schematic diagram for the bit field overlapping operation that one embodiment of the invention provides.
The operand of bit field overlapping operation is defined as follows within a processor：
1st, background register Rb and prospect register Rf, register bit wide is identical with processor bit wide, is hereinafter related to
Register is processor bit wide N, generally N=32 or 64；
2nd, original position Pos, bit wide log are covered2N, span N-1 to 0；
3rd, overlay length Len, bit wide log2N+1, span N to 0；
4th, sign extended enables E.
Fig. 1 (a) figure is the bit field operation chart without sign extended.Opened in prospect register Rf from lowest order
Begin, take Len positions, cover the Len positions started in background register from Pos positions (Pos+1 positions, containing the position).When Pos be equal to 0,
Len is not 0, then the lowest order in background register Rb also will be capped.If Pos+Len ＞ 31, off-limits numerical value will
Cast out.When sign extended enables, it is necessary to be extended according to the highest order of the low Pos+Len positions of result, i.e. S=Dest [Pos
+Len-1].If Len is not equal to 0, the sign bit extended is the Len positions (i.e. Rf [Len-1]) in prospect register, as a result
As shown in Fig. 1 (b) figure；If Len is equal to 0, Pos+Len=Pos, then the Pos+Len positions of current results are background deposits
The Pos positions (i.e. Rb [Pos-1]) of device, as a result as shown in Fig. 1 (c) figure.If Len and Pos are 0, not during escape character, knot
Fruit is identical with background register, and during sign extended, result is 0.
Fig. 2 is the structure chart for the bit field cladding system that one embodiment of the invention provides, as shown in Fig. 2 bit field cladding system
Including the first code translator, the second code translator, shift unit 201, position selection device, adder 205 and selector group 206, its
In, the first code translator includes the first decoder 204 and the first phase inverter, and the second code translator includes the second decoder 207, the
Two reversers and include first selector 2061, second selector 2062 and third selector 2063 with door, selector group 206.
The operation of bit field cladding system is divided into two steps, wherein, the first step has following parallel work-flow：
Generation prospect value F
Value in prospect register Rf is moved to left according to covering original position Pos, obtains prospect value by shift unit 201
F.In the present embodiment, prospect register is moved to left into Pos positions, the position that such prospect register Rf needs to take out with background register
The position for the position for needing to cover just overlaps, as shown in table 1：
| Rb： | b | b | b | b | b | b | b | b | b | b | b | b | b | b | b | b | b | b | b | b | b | b | b | b | b | b | b | b | b | b | b | b |
| F： | f | f | f | f | f | f | f | f | f | f | f | f | f | f | f | f | f | f | f | f | f | f | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Table 1
Wherein F is exactly the value arrived that Rf is moved to left to Pos, and the position represented with underscore is the bit for needing to cover, shift unit
201 can use existing arithmetic element in current processor to realize.
Generate background position selection signal SelB
First code translator includes the first decoder 204 and the first phase inverter, and the first decoder is to covering original position Pos
After entering row decoding, the first phase inverter carries out reversely, obtaining background position selection signal SelB to decoding result.If N=32, its is true
Value table is：
| Input (Pos) | Export (SelB) |
| 00000 | 0000_0000_0000_0000_0000_0000_0000_0000 |
| 00001 | 0000_0000_0000_0000_0000_0000_0000_0001 |
| 00010 | 0000_0000_0000_0000_0000_0000_0000_0011 |
| 00011 | 0000_0000_0000_0000_0000_0000_0000_0111 |
| 00100 | 0000_0000_0000_0000_0000_0000_0000_1111 |
| … | … |
| 11110 | 0011_1111_1111_1111_1111_1111_1111_1111 |
| 11111 | 0111_1111_1111_1111_1111_1111_1111_1111 |
Table 2
The general idea of upper table be SelB since lowest order, have Pos 1 because Pos scope is 31 values 0,
SelB highest order is 0 forever.Each in SelB is using as the selection signal of an alternative selector.It is worth and is represented for 1
The position will not be covered, it is necessary to select the respective value in background register by prospect.
Generate escape character S
Performed in Fig. 2 using the first digit selector 202 and specific bit is taken out from N-bit, so the first digit selector 202
Design realization is the selector that a N selects 1.Second digit selector 203 is identical with 202 structure.Digit selector 202 exports Sb=
Rb [Pos-1], digit selector 203 export Sf=Rf [Len-1], because Pos and Len may be 0, so digit selector 202
Output and 0 when meeting that input is 0 with 203, so meet requirement above.While line position selection is entered, it can be determined that Len
Whether be zero, after Sb and Sf is obtained, using judged result select corresponding to sign bit.Generally N selects 1 selector
It is faster (unless both being realized using alternative selector) than the shift unit of N position, it is believed that the time for the sign bit S that is expanded
It is suitable with shift time.
Generate sign bit selection signal SelS
Adder calculate overlay length with cover original position and, obtain and be worth, the second code translator pair and value progress
Decoding, obtains sign bit selection signal SelS.Wherein, adder also exports a carry value, and wherein, the second code translator
Including the second decoder 207, the second reverser and with door, wherein, the second decoder pair and be worth into after row decoding, be input to and door
An input, after the second reverser is carried out reversely to the carry value of adder, be input to another input with door, with
Input progress and computing of the door to its input, obtain sign bit selection signal SelS.In the present embodiment, although Len is
Log2N+1 positions, but because its value can only be N to 0, adder 205 is a LogN positions adder.Use adder
And by with the identical decoder 207 of decoder 204 (do not have to plus phase inverter) herein, in obtained N positions, be worth that represented for 1 should
Position is in the position for needing sign extended.The carry of adder or Len highest order (not showing in diagram that) if 1,
Then represent that Len+Pos is more than or equal to N, this shows, in N positions as a result, does not need the space extended, even if then enabling symbol
Extension, last result is without selection escape character.Although 4) operation is more for operation, path is shorter, a Log2N positions
Adder, one Log of one-level2N-N atypia decoder, it is shorter than the shift unit path of N position in static CMOS.
Second step operation is carried out by the selector group 206 of bit slice, as shown in Fig. 2 selector group 206 includes the first choosing
Select device 2061, second selector 2062 and third selector 2063, the value in prospect value F and background register Rb is separately input into
The input of first selector 2061, the background position selection signal SelB are inputted to the control terminal of first selector 2061；Expand
Value in exhibition symbol S and background register Rb is separately input into the input of second selector 2062, by the enabled letter of an extension
Number E is inputted to the control terminal of second selector 2062；The output termination the 3rd of first selector 2061 and second selector 2062
The input of selector 2063, sign bit selection signal SelS are inputted to the control terminal of third selector 2063.
It is SelB and SelS example below：
| SelB | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| SelS | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Dest | S | S | S | S | S | S | S | S | S | S | S | F | F | F | F | F | F | F | F | F | F | F | b | b | b | b | b | b | b | b | b | b |
Table 3
Wherein underscore part is the position for needing prospect covering background.
Selection logic can be evident that by table 3.Being determined first according to sign extended enable signal E should in result
Extension bits sign bit S still should retain the respective value in background register Rb, and this operates with second selector 2062
Carry out, the value that is expanded ES.
When SelB intermediate values are 1, it is necessary to select the respective value of background register, prospect value F is otherwise selected, uses the first choosing
Select device 2061 to carry out, proceed to herein, except the bit field numerical value for needing to extend is not right, other values are properly, so carrying out most
Latter step, is selected using SelS, and the position in SelS for 1 is exactly the position for needing to select Bits Expanding value ES, remaining
The result that reservation selects to obtain using SelB, then obtains final result.
Above logic can also be deleted simply, not supported the hardware logic of sign extended：Without 202 Hes
203 carry out the selection of sign bit.Before final choice, by SelB and SelS phase "or", as a result in, need to select for 1 positional representation
Background register Rb value is selected, represents to need the value of selection prospect for 0 place.Compared with the logic of optional sign extended,
For in delay, one-level alternative logic more than the most logics than not supporting sign extended of logic of sign extended is supported,
For unit consumption, the former two digit selectors more than the latter.Either delay or unit consumption, can bear completely
Within the scope of.
Particular embodiments described above, the purpose of the present invention, technical scheme and beneficial effect are carried out further in detail
Describe in detail it is bright, should be understood that the foregoing is only the present invention specific embodiment, be not intended to limit the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvements done etc., it should be included in the guarantor of the present invention
Within the scope of shield.
Claims (7)
1. a kind of bit field cladding system, for processor, the processor includes prospect register and background register, its feature
Be, the bit field cladding system include the first code translator, the second code translator, shift unit, position selection device, adder and
Selector group, wherein：
Value in the prospect register is moved to left according to covering original position, obtains prospect value by the shift unit；
Institute's rheme selection device includes the first digit selector, the second digit selector and symbol digit selector, first selection
Device selects to need the sign bit extended in the prospect register according to overlay length, and second digit selector is according to covering
Sign bit in the beginning position selection background register, the symbol digit selector are true from two sign bits of the selection
Fixed final sign bit；
First code translator enters row decoding to the covering original position, obtains background position selection signal；
The adder calculate the overlay length and covering original position and, obtain and be worth；
Second code translator obtains sign bit selection signal to described and be worth into row decoding；
The selector group according to sign extended enable signal, background position selection signal and the sign bit selection signal,
Value in the prospect value, the final sign bit and background register is selected, obtained a result.
2. bit field cladding system according to claim 1, it is characterised in that first code translator includes the first decoding
Device and the first phase inverter, after first decoder enters row decoding to the covering original position, the first phase inverter paginal translation
Code result carries out reversely, obtaining background position selection signal.
3. bit field cladding system according to claim 1, it is characterised in that when the overlay length is equal to 0, the symbol
Number digit selector selects the sign bit of the first digit selector output, otherwise, the symbol digit selector selection described second
The sign bit of digit selector output.
4. bit field cladding system according to claim 1, it is characterised in that the adder also exports a carry value.
5. bit field cladding system according to claim 4, it is characterised in that second code translator includes the second decoding
Device, the second reverser and with door, wherein, second decoder is input to described with door to described and be worth into after row decoding
One input, after second reverser is carried out reversely to the carry value of the adder, it is input to described another with door
Individual input, described and input progress and computing of the door to two input, obtains the sign bit selection signal.
6. bit field cladding system according to claim 1, it is characterised in that the selector group include first selector,
Second selector and third selector, wherein：
Value in the prospect value and the background register is separately input into the input of the first selector, the background
Position selection signal is inputted to the control terminal of the first selector；
Value in the final sign bit and the background register is separately input into the input of the second selector, by one
Individual extension enable signal is inputted to the control terminal of the second selector；
The output of the first selector and the second selector terminates the input of the third selector, the sign bit
Selection signal is inputted to the control terminal of the third selector.
7. a kind of bit field overlapping operation method, for processor, the processor includes prospect register and background register, its
It is characterised by, methods described includes：
S1, according to covering original position, the value in the prospect register is moved to left, obtains prospect value；
S2, while the step S1 is carried out, according to overlay length, select to need the symbol extended in the prospect register
Position, the sign bit in the background register is selected according to covering original position, and needed from the prospect register of selection
Final sign bit is determined in sign bit in the sign bit and the background register to be extended；
S3, while the step S1 is carried out, row decoding is entered to the covering original position, obtains background position selection signal；
S4, while the step S1 is carried out, calculate the overlay length with cover original position and, and to the covering
Length with covering original position and enter row decoding, obtain sign bit selection signal；
S5, according to sign extended enable signal, background position selection signal and the sign bit selection signal, to the prospect
Value in value, the final sign bit and background register is selected, and is obtained a result.
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|---|---|---|---|---|
| CN101154153A (en) * | 2006-09-26 | 2008-04-02 | 冲电气工业株式会社 | Bit field operation circuit |
| CN103229139A (en) * | 2010-11-23 | 2013-07-31 | Arm有限公司 | Data processing apparatus having bit field manipulation instruction and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101154153A (en) * | 2006-09-26 | 2008-04-02 | 冲电气工业株式会社 | Bit field operation circuit |
| CN103229139A (en) * | 2010-11-23 | 2013-07-31 | Arm有限公司 | Data processing apparatus having bit field manipulation instruction and method |
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Effective date of registration: 20190617 Address after: 100097 Commercial A02-79, Block A, 2nd Floor, 116 Zizhuyuan Road, Haidian District, Beijing Patentee after: Beijing Zhongke Haoxin Technology Co., Ltd. Address before: 100190 Zhongguancun East Road, Haidian District, Haidian District, Beijing Patentee before: Institute of Automation, Chinese Academy of Sciences |