CN104979345A - High-voltage CMOS integrated structure and manufacture method thereof - Google Patents
High-voltage CMOS integrated structure and manufacture method thereof Download PDFInfo
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- CN104979345A CN104979345A CN201410141299.2A CN201410141299A CN104979345A CN 104979345 A CN104979345 A CN 104979345A CN 201410141299 A CN201410141299 A CN 201410141299A CN 104979345 A CN104979345 A CN 104979345A
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Abstract
The invention provides a high-voltage CMOS integrated structure and a manufacture method thereof. The high-voltage CMOS integrated structure comprises a P-type substrate, a high-voltage PMOS, a non-isolated high-voltage NMOS, an isolated high-voltage NMOS and an isolation region. The high-voltage PMOS, the non-isolated high-voltage NMOS, the isolated high-voltage NMOS and the isolation region are arranged in the P-type substrate; and the isolation region is arranged between the non-isolated high-voltage NMOS and the isolated high-voltage NMOS. The high-voltage PMOS, the non-isolated high-voltage NMOS, the isolated high-voltage NMOS and the isolation region are directly arranged in the P-type substrate without an epitaxial layer or a burial layer, thereby reducing manufacture and process cost.
Description
Technical field
The present invention relates to semiconductor technology, particularly relate to a kind of high pressure complementary metal oxide semiconductors (CMOS) (Complementary Metal Oxide Semiconductor is called for short CMOS) integrated morphology and manufacture method thereof.
Background technology
Fig. 1 is the structural representation of prior art mesohigh CMOS integrated morphology.As shown in Figure 1, the components and parts such as high voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS are integrated with in this high-voltage CMOS integrated morphology, the making of this high-voltage CMOS integrated morphology mainly adopts and make N-type buried layer in P type substrate, then epitaxial loayer is made, then among the superimposed layer structure of substrate and epitaxial loayer, make the components and parts such as high voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS, its specific implementation is: the first high pressure NMOS is non-isolation type high pressure NMOS, the second high pressure NMOS is isolated form high pressure NMOS.Wherein, the P trap of non-isolation type high pressure NMOS is directly produced among the superimposed layer structure of P type substrate and epitaxial loayer, N-type buried layer must be adopted between the P trap of isolated form high pressure NMOS and P type substrate to keep apart, high voltage PMOS adopts the 3rd P trap to bear the buffering area of high voltage operation as drain terminal, as shown in Figure 1, the effect of N-type buried layer is the 3rd P trap of high voltage PMOS drain terminal and P type substrate to keep apart, otherwise be short-circuited between drain terminal and P type substrate, and the 2nd P trap of isolated form high pressure NMOS and P type substrate are kept apart.
But owing to the integrated and isolated area of high pressure NMOS and high voltage PMOS being all produced in epitaxial loayer, and the making of epitaxial loayer needs expensive semi-conducting material, therefore result in the problem that the cost of manufacture of high-voltage CMOS integrated morphology is high.
Summary of the invention
The invention provides a kind of high-voltage CMOS integrated morphology and manufacture method thereof, by high voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area are set directly in P type substrate, do not need epitaxial loayer and buried layer, reduce making and process costs.
First aspect present invention provides a kind of high-voltage CMOS integrated morphology, comprising: P type substrate, high voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area;
Described high voltage PMOS, described non-isolation type high pressure NMOS, described isolated form high pressure NMOS and described isolated area are separately positioned in described P type substrate;
Described isolated area is arranged between described non-isolation type high pressure NMOS and described isolated form high pressure NMOS.
Second aspect present invention provides a kind of manufacture method of high-voltage CMOS integrated morphology, comprising:
Make P type substrate;
High voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area is formed in described substrate P;
Wherein, described isolated area is arranged between described non-isolation type high pressure NMOS and described isolated form high pressure NMOS.
High-voltage CMOS integrated morphology of the present invention and manufacture method thereof, by high voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area are set directly in P type substrate, epitaxial loayer is arranged on compared to prior art mesohigh PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area, the present invention, owing to not needing high voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area to be arranged in epitaxial loayer and buried layer, makes and process costs because this reducing.
Accompanying drawing explanation
Fig. 1 is the structural representation of prior art mesohigh CMOS integrated morphology;
Fig. 2 is the structural representation of high-voltage CMOS integrated morphology embodiment one of the present invention;
Fig. 3 is the structural representation of high-voltage CMOS integrated morphology embodiment two of the present invention;
Fig. 4 is the flow chart of the manufacture method embodiment one of high-voltage CMOS integrated morphology of the present invention;
Fig. 5 a to Fig. 5 c is respectively the flow chart of the manufacture method embodiment two of high-voltage CMOS integrated morphology of the present invention.
Embodiment
Fig. 2 is the structural representation of high-voltage CMOS integrated morphology embodiment one of the present invention, and as shown in Figure 2, this high-voltage CMOS integrated morphology comprises: P type substrate, high voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area.Described high voltage PMOS, described non-isolation type high pressure NMOS, described isolated form high pressure NMOS and described isolated area are separately positioned in described P type substrate, and isolated area is arranged between described non-isolation type high pressure NMOS and isolated form high pressure NMOS.
In the present embodiment, this CMOS is the combining structure that n channel metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor is called for short MOS) and P channel MOS (being called for short PMOS) are electrically connected according to certain way.High-voltage CMOS integrated morphology, at least comprises the high-pressure MOS component of three kinds of structures usually: non-isolation type high pressure NMOS, isolated form high pressure NMOS, high voltage PMOS.High pressure NMOS and high voltage PMOS adopt lightly doped N-type doped region and lightly doped P type doped region to bear the buffering area of high voltage operation as its drain terminal usually respectively, in high-voltage CMOS integrated circuit (IC) chip, also all integration section low voltage CMOS circuit (circuit that low pressure NMOS and low pressure PMOS are formed).
The high-voltage CMOS integrated morphology that the present embodiment provides, by high voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area are set directly in P type substrate, epitaxial loayer is arranged on compared to prior art mesohigh PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area, the present invention, owing to not needing high voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area to be arranged in epitaxial loayer and buried layer, makes and process costs because this reducing.
Fig. 3 is the structural representation of high-voltage CMOS integrated morphology embodiment two of the present invention, and on basis embodiment illustrated in fig. 2, as shown in Figure 3, the high-voltage CMOS integrated morphology of the present embodiment also comprises:
This high voltage PMOS comprises: source P+ doped region, P type drift region, drain terminal P+ doped region and a N trap, source P+ doped region, P type drift region and drain terminal P+ doped region are arranged in a N trap, and P type drift region is between source P+ doped region and drain terminal P+ doped region.Preferably, the degree of depth of a N trap is 2 ~ 10 times of the degree of depth of P type drift region.
In the present embodiment, P type drift region is the buffering area that high voltage PMOS drain terminal bears high voltage operation.
This isolated form high pressure NMOS comprises the 2nd N trap, the 2nd P trap, the 3rd N trap, source N+ doped region and drain terminal N+ doped region.Wherein, the 2nd N trap and the 2nd P trap are arranged in the 3rd N trap, and source N+ doped region is arranged in the 2nd P trap, and drain terminal N+ doped region is arranged in the 2nd N trap.
Preferably, the degree of depth of the 3rd N trap is 1.5 ~ 3 times of the degree of depth of the 2nd P trap.
In the present embodiment, the 2nd N trap is the buffering area that the drain terminal of isolated form high pressure NMOS bears high voltage operation.
In addition, non-isolation type high pressure NMOS is identical with prior art, comprises the 4th P trap and the 4th N trap, source N+ doped region and drain terminal N+ doped region, and the 4th N trap is the buffering area that the drain terminal of non-isolation type high pressure NMOS bears high voltage operation.
The high-voltage CMOS integrated morphology that the present embodiment provides, high voltage PMOS is by source P+ doped region, P type drift region, drain terminal P+ doped region and N trap composition, source P+ doped region, P type drift region and drain terminal P+ doped region are arranged in a N trap, and described P type drift region is between described source P+ doped region and drain terminal P+ doped region, isolated form high pressure NMOS is by the 2nd N trap, 2nd P trap, 3rd N trap, source N+ doped region and drain terminal N+ doped region composition, 2nd N trap and the 2nd P trap are arranged in described 3rd N trap, one N trap and the 3rd N trap are all arranged in P type substrate, do not need epitaxial loayer and buried layer, relative to epitaxial loayer expensive in prior art, reduce making and process costs.
Fig. 4 is the flow chart of the manufacture method embodiment one of high-voltage CMOS integrated morphology of the present invention, and as shown in Figure 4, this manufacture method comprises:
S401: make P type substrate.
S402: form high voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area in substrate P.
In the present embodiment, this high-voltage CMOS integrated morphology can be the integrated morphology of above-mentioned Fig. 2 to correspondence embodiment illustrated in fig. 3.
In addition, isolated area is arranged between non-isolation type high pressure NMOS and isolated form high pressure NMOS, and this isolated area by P trap, and can arrange the P field doped region composition higher than this P trap doping content on this P trap top layer.For the quantity of high voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area, can arrange as requested, the present invention does not limit.
The manufacture method of the high-voltage CMOS integrated morphology that the present embodiment provides, by high voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area are set directly in P type substrate, do not need epitaxial loayer and buried layer, reduce making and process costs.
Fig. 5 a to Fig. 5 c is respectively the flow chart of the manufacture method embodiment two of high-voltage CMOS integrated morphology of the present invention, on basis embodiment illustrated in fig. 4, as shown in Figure 5 a, forms high voltage PMOS in S402 in substrate P, specifically comprises:
S501, in substrate P formed a N trap.
S502, in a N trap, form source P+ doped region, P type drift region and drain terminal P+ doped region; Wherein, P type drift region is between source P+ doped region and drain terminal P+ doped region.By forming the mode of doped region, P field, form the P type drift region of this high voltage PMOS.
Preferably, as shown in Figure 5 b, in substrate P, form isolated form high pressure NMOS in S402, specifically comprise:
S503, in P type substrate make the 3rd N trap.
S504, makes the 2nd N trap and the 2nd P trap in the 3rd N trap.
S505, forms drain terminal N+ doped region in the 2nd N trap, in the 2nd P trap, form source N+ doped region.
Preferably, as shown in Figure 5 c, in substrate P, form non-isolation type high pressure NMOS in S402, specifically comprise:
S506, in P type substrate, make the 4th P trap and the 4th N trap.
S507, in the 4th N trap, form drain terminal N+ doped region, in the 4th P trap, form source N+ doped region.
In the present embodiment, preferably, the degree of depth of P type drift region is 0.25 ~ 1.8 micron, and the degree of depth of a N trap is 2-15 micron, and the degree of depth of the 3rd N trap is 4-15 micron, and the degree of depth of the 2nd N trap and the 2nd P trap is 2-8 micron.
Preferably, P type substrate to be resistivity the be P type single crystalline substrate of 5 ~ 300 ohm * centimetre.
Further, in the manufacture method embodiment three of high-voltage CMOS integrated morphology, on the basis of the embodiment shown in above-mentioned Fig. 4, Fig. 5 a-5c, field oxide is formed in the subregion on this P type substrate surface, and form gate oxide at the P type substrate surf zone do not covered by field oxide, form polysilicon gate in the subregion on gate oxide and field oxide surface, be finally made into high-voltage CMOS integrated morphology.
The manufacture method of the high-voltage CMOS integrated morphology that the present embodiment provides, high voltage PMOS is formed for forming a N trap in substrate P in substrate P, source P+ doped region, P type drift region and drain terminal P+ doped region is formed in a N trap, this P type drift region is between source P+ doped region and drain terminal P+ doped region, isolated form high pressure NMOS is formed for making the 3rd N trap in P type substrate in substrate P, the 2nd N trap and the 2nd P trap is made in the 3rd N trap, in the 2nd N trap, form drain terminal N+ doped region, in the 2nd P trap, form source N+ doped region.One N trap and the 3rd N trap are all arranged in P type substrate, do not need epitaxial loayer and buried layer, relative to epitaxial loayer expensive in prior art, reduce making and process costs.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (10)
1. a high-voltage CMOS integrated morphology, is characterized in that, comprising: P type substrate, high voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area;
Described high voltage PMOS, described non-isolation type high pressure NMOS, described isolated form high pressure NMOS and described isolated area are separately positioned in described P type substrate;
Described isolated area is arranged between described non-isolation type high pressure NMOS and described isolated form high pressure NMOS.
2. high-voltage CMOS integrated morphology according to claim 1, is characterized in that, described high voltage PMOS comprises source P+ doped region, P type drift region, drain terminal P+ doped region and a N trap;
Described source P+ doped region, described P type drift region and described drain terminal P+ doped region are arranged in a described N trap, and described P type drift region is between described source P+ doped region and described drain terminal P+ doped region.
3. high-voltage CMOS integrated morphology according to claim 1, is characterized in that, the degree of depth of a described N trap is 2 ~ 10 times of the degree of depth of described P type drift region.
4., according to the arbitrary described high-voltage CMOS integrated morphology of claims 1 to 3, it is characterized in that, described isolated form high pressure NMOS comprises the 2nd N trap, the 2nd P trap, the 3rd N trap, source N+ doped region and drain terminal N+ doped region;
Described 2nd N trap and described 2nd P trap are arranged in described 3rd N trap;
Described source N+ doped region is arranged in described 2nd P trap, and described drain terminal N+ doped region is arranged in described 2nd N trap.
5. high-voltage CMOS integrated morphology according to claim 4, is characterized in that, the degree of depth of described 3rd N trap is 1.5 ~ 3 times of the degree of depth of described 2nd P trap.
6. a manufacture method for high-voltage CMOS integrated morphology, is characterized in that, comprising:
Make P type substrate;
High voltage PMOS, non-isolation type high pressure NMOS, isolated form high pressure NMOS and isolated area is formed in described substrate P;
Wherein, described isolated area is arranged between described non-isolation type high pressure NMOS and described isolated form high pressure NMOS.
7. manufacture method according to claim 6, is characterized in that, forms described high voltage PMOS, comprising in described substrate P:
A N trap is formed in described substrate P;
Source P+ doped region, P type drift region and drain terminal P+ doped region is formed in a described N trap; Wherein, described P type drift region is between described source P+ doped region and described drain terminal P+ doped region.
8. manufacture method according to claim 6, is characterized in that, forms isolated form high pressure NMOS, comprising in described substrate P:
Described 3rd N trap is made in described P type substrate;
Described 2nd N trap and described 2nd P trap is made in described 3rd N trap;
In described 2nd N trap, form drain terminal N+ doped region, in described 2nd P trap, form source N+ doped region.
9. the manufacture method according to claim 7 or 8, is characterized in that, the degree of depth of a described N trap is 2-15 micron; The degree of depth of described 3rd N trap is 4-15 micron; The degree of depth of described 2nd N trap and described 2nd P trap is 2-8 micron.
10., according to the arbitrary described manufacture method of claim 6 ~ 9, it is characterized in that, the resistivity of described P type substrate is 5 ~ 300 ohm of * centimetre.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060220179A1 (en) * | 2005-04-01 | 2006-10-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming an improved isolation junction in high voltage LDMOS structures |
| CN102446955A (en) * | 2010-10-06 | 2012-05-09 | 旺宏电子股份有限公司 | High voltage MOS device and method for making the same |
| CN103280460A (en) * | 2013-05-22 | 2013-09-04 | 矽力杰半导体技术(杭州)有限公司 | High-voltage PMOS (p-channel metal oxide semiconductor) transistor with injection molded superimposed drift region and manufacturing method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060220179A1 (en) * | 2005-04-01 | 2006-10-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming an improved isolation junction in high voltage LDMOS structures |
| CN102446955A (en) * | 2010-10-06 | 2012-05-09 | 旺宏电子股份有限公司 | High voltage MOS device and method for making the same |
| CN103280460A (en) * | 2013-05-22 | 2013-09-04 | 矽力杰半导体技术(杭州)有限公司 | High-voltage PMOS (p-channel metal oxide semiconductor) transistor with injection molded superimposed drift region and manufacturing method thereof |
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Effective date of registration: 20220719 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District, Cheng Fu Road, No. 298, Zhongguancun Fangzheng building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |
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