CN104978448B - Bayesian model hybrid predicting circuit yield method based on Bernoulli Jacob's distribution - Google Patents
Bayesian model hybrid predicting circuit yield method based on Bernoulli Jacob's distribution Download PDFInfo
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Abstract
This method belongs to integrated circuit fields, is related to a kind of method for the Bayesian model hybrid predicting circuit yield being distributed based on Bernoulli Jacob.This method by being incorporated in the information of the different phase of IC design, accelerate to only have " by-do not pass through " the yield rate estimation procedure of the circuits of two states.This method be " by-do not pass through " output result establish Bernoulli Jacob's model, by priori yield rate be set as beta distribution, and using maximum likelihood method determine beta distribution in hyper parameter.The hyper parameter is reused, in conjunction with more a small amount of posterior information, estimates the yield rate of integrated circuit.This method estimates yield rate compared to traditional Monte Carlo Analysis, and in the case where reaching same precision, the posterior information needed has been lacked very much, can obviously save and carry out post-simulation or carry out the time newly once tested.
Description
Technical field
This method belongs to integrated circuit fields, and in particular to a kind of Bayesian model hybrid predicting based on Bernoulli Jacob's distribution
The method of circuit yield.
Technical background
The continuous diminution of studies have shown that integrated circuit dimensions results in prodigious uncertainty in manufacturing process, including ginseng
The uncertainty of the fluctuation of numberization and certain fatefulue defects, this two class may all cause serious yield loss.Cause
This, stage for testing after verification or flow either before flow, in order to improve circuit performance or reduce manufacturing cost, at
The accurate estimation of product rate is all a very important job.
Recently, the prior art proposes the design method of a series of new（Such as it is adjusted after silicon chip）It is made to solve chip
The problem of fluctuation, with the paces for maintaining current integrated circuit dimensions constantly to reduce.These novel design methods are shown through practice
It is highly effective, but in turn so that nowadays the complexity of integrated circuit is continuously increased.Such present situation is resulted in be estimated in yield rate
Timing has to collect larger numbers of Random datasets, such as：
It is verified before flow：It needs to run Butut wiring post-simulation, and is now very for the emulation of a complicated circuit
Time-consuming；
It is tested after flow：It needs to test practical silicon chip, it is real to determine that the chip is " passing through " or " not passing through "
Display is trampled, the task is also and remarkable, and the cost only tested comprehensively the silicon chip of sub-fraction is only acceptable.
In order to solve the problems, such as that this is related to data collection, there is research accurately to estimate using Bayesian model mixing method is quasi-
Count the statistical parameter of circuit（Performance profile, yield rate）.Bayesian model mixing method has borrowed prior information（As preceding emulation is believed
Breath）Accurately to estimate posterior statistical parameter.This method can efficiently reduce verified in the posteriority stage, test at
This.But traditional Bayesian model mixing method can only effectively handle continuously distributed performance parameter（Such as digital circuit
Delay, the gain etc. of analogue amplifier）.This is because traditional method assumes that actual performance profile is continuous, in many
The occasion of practical application accurately can not obtain the delay of critical path by testing a silicon chip；It can only usually know this
Whether chip meets the requirements, and is still unsatisfactory for, therefore, the still not applicable accurately estimation electricity of traditional Bayesian model mixing method
The statistical parameter on road.
The prior art related to the present invention has following bibliography：
[1]X.Li,J.LeandL.Pileggi,StatisticalPerformanceModelingandOptimizatio
n,NowPublishers,2007.
[2]SemiconductorIndustryAssociate,InternationalTechnologyRoadmapfor
Semiconductors,2011.
[3]A.Srivastava,S.Shah,K.Agarwal,D.Sylvester,D.BlaauwandS.Director,
“Accurateandefficientgate-levelparametricyieldestimationconsidering
correlatedvariationsinleakagepowerandperformance,”IEEEDAC,pp.535-540.
[4]X.Li,J.Le,P.GopalakrishnanandL.Pileggi,“Asymptoticprobabilityextra
ction fornonnormalperformancedistributions,”IEEETrans.onCAD,vol.26,no.1,
pp.16-37,Jan.2007.
[5]P.Desrumaux,Y.Dupret,J.Tingleft,S.Minehane,M.Redford,
L.LatorreandP.Nouet,“Anefficientcontrolvariatesmethodforyieldestimationofanal
og circuitsbasedonalocalmodel,”IEEEICCAD,pp.415-421,2012.
[6]S.Mitra,S.SeshiaandN.Nicolici,“Post-siliconvalidationopportunities
,challengesandrecentadvances,”IEEEDAC,pp.12-17,2010.
[7]X.Li,“Post-siliconperformancemodelingandtuningofanalog/mixed-
signal circuitsviaBayesianmodelfusion,”IEEEICCAD,pp.551-552,2012.
[8]J.Rivers,M.Gupta,J.Shin,P.KudvaandP.Bose,“Errortoleranceinserver
classprocessors,”IEEETrans.onCAD,vol.30,no.7,pp.945-959,Jul.2011.
[9]A.Tang,F.Hsiao,D.Murphy,I.Ku,J.Liu,S.Souza,N.Wang,H.Wu,Y.Wang,
M.Tang,G.Virbila,M.Pham,D.Yang,Q.Gu,Y.Wu,Y.Kuan,C.Chien,M.Chang,“Alow-
overheadself-healingembeddedsystemforensuringhighyield andlong-
termsustainabilityof60GHz4Gb/sradio-on-a-chip”,IEEEISSCC,pp.316-318,2012.
[10]B.Sadhu,M.Ferriss,A.Natarajan,S.Yaldiz,J.Plouchart,A.Rylyakov,
A.Valdes-Garcia,B.Parker,A.Babakhani,S.Reynolds,X.Li,L.Pileggi,R.Harjani,
J.TiernoandD.Friedman,“Alinearized,low-phase-noiseVCO-based25GHzPLLwithautono
micbiasing,”IEEEJSSC,vol.48,no.5,pp.1138-1150,May.2013.
[11]P.Gupta,Y.Agarwal,L.Dolecek,N.Dutt,R.Gupta,R.Kumar,S.Mitra,
A.Nicolau,T.Rosing,M.Srivastava,S.SwansonandD.Sylvester,“Underdesigned
andopportunisticcomputinginpresenceofhardwarevariability,”IEEETrans.onCAD,
vol.32,no.1,pp.8-23,Jan.2013.
[12]X.Li,W.Zhang,F.Wang,S.SunandC.Gu,“Efficientparametricyield
estimationofanalog/mixed-signalcircuitsviaBayesianmodelfusion,”IEEE ICCAD,
pp.627-634,2012.
[13]C.Gu,E.ChiproutandX.Li,“Efficientmomentestimationwithextremelysma
ll samplesizeviaBayesianinferenceforanalog/mixed-signalvalidation,”IEEE DAC,
2013.
Invention content
The purpose of the present invention is to overcome defect of the existing technology, provide a kind of Bayes being distributed based on Bernoulli Jacob
Model mixing method is used for hybrid predicting circuit yield.
This method by being incorporated in the information of the different phase of IC design, accelerate to only have " by-it is obstructed
Cross " the yield rate estimation procedure of the circuits of two states.This method be " by-do not pass through " output result establish one primary
Sharp model is exerted, priori yield rate is set as beta distributions, and the hyper parameter in beta distributions is determined using maximum likelihood method.Again
Using the hyper parameter yield rate of integrated circuit is estimated in conjunction with more a small amount of posterior information.This method compares traditional illiteracy
Spy-Carlow method estimates yield rate, and in the case where reaching same precision, the posterior information needed has been lacked very much, can obviously save
It saves and carries out post-simulation or carry out the time newly once tested.
The method of the present invention can effectively handle the emulation that conventional method cannot be handled or test generates binary output
When the case where；For only have " by-do not pass through " test cases of two kinds of output states, only need priori yield rate and after
The yield rate tested approaches in a certain range, what the present invention collected required for capable of being obviously reduced in the case where reaching same accuracy
The quantity of posteriority data point thus greatly reduces the cost of verification, test.
In order to achieve the above object, the technical scheme is that：A kind of Bayesian model based on Bernoulli Jacob's distribution is mixed
The method for closing estimation yield rate（BMF-BD）, it can be described with Fig. 1, and its step are as follows：
Step 201：The data of last stage and rear stage are read, these data are passed through advance processing, have been encoded to
The format of " 0-1 ", 0, which represents test, does not pass through, and 1, which represents test, passes through；
Step 202：Obtained data are divided into two groups：For the applicable cases emulated before flow, corresponding is placement-and-routing
Preceding emulation（Last stage）With placement-and-routing's post-simulation（Stage afterwards）, for the application tested after flow, corresponding is relatively early a batch
Test result（Last stage）With newest batch of test result（Stage afterwards）；In the step, pass through the yield rate to the last stage
Study, prior information is encoded in an appropriate form comprising step by step 21 and step by step 22：
Step by step 21：The yield rate of last stage is acquired using maximum likelihood method：
Since the test output of circuit only has two " 0-1 ", it can be considered that being one has the random of Bernoulli Jacob's distribution
Variable：
Its statistical property can be expressed as：
Wherein, β ∈ [0,1]Represent the yield rate to be estimated；
According to formula
It can obtain the yield information of last stage, wherein M is the points by test in the last stage, and N is to participate in total
The points of test；
Step by step 22：The general difference with the rear stage of the yield rate of last stage, but because of the circuit of last stage and rear stage
It,, will be to be estimated in order to characterize such uncertainty because the yield rate in hereafter stage should be similar with the last stage with similitude
Parameter beta regard as one with beta distribution stochastic variable：
Wherein, a, b are referred to as hyper parameter, they control the shape of the probability density function（As shown in Figure 2）, this
Beta functions are in some specific value βMOn get maximum, the expression formula of the particular value is：
In order to fix constraint to hyper parameter a, b, β is enabledMIt is equal with the yield rate that the last stage obtains：
Therefore, the distribution expression formula of parameter beta can also be write：
Above formula is the expression formula of prior information；
Step 203：
The value of hyper parameter a obtains it in conjunction with the data that the rear stage obtains using maximum likelihood method in above formula in order to obtain
Value：
In above formula, the rear number of stages strong point that x representatives obtain, M characterizations wherein pass through test（As a result it is " 1 "）Data point
Number, N are total data point number, and above formula integrates β from 0 to 1：
In order to enable above formula is maximum（Namely obtain the possibility maximum of observed result x）, obtained using the method for linear search
One optimal hyper parameter a meets following formula：
The size of hyper parameter is characterized firmly believes degree for prior information；
Step 204：Posteriority yield rate is obtained using maximum a posteriori, according to Bayesian formula, the Posterior distrbutionp of parameter beta is just
Than in the product of prior distribution and likelihood function：
It is obtained by normalization：
Above formula is the Posterior distrbutionp expression formula of parameter beta, it can be seen that the formula is also a beta distribution, and value obtains
The value of parameter beta when maximum is the yield rate of BMF methods estimation：
Step 205：The finished product rate score β that output estimation obtainsMAP。
The method of the present invention is directed to the circuit yield estimation with binary output, has the following advantages that：
1. combining prior information and posterior information, more traditional monte carlo method, in the feelings for reaching same accuracy
The posteriority points needed under condition are smaller, it will be apparent that reduce test and verify the costs such as required time.
2. compare the BMF methods of the prior art, this method can handle and only have " by-do not pass through " two states
Circuit has real practicability.
Description of the drawings
Fig. 1 is the flow of the method for the Bayesian model hybrid predicting circuit yield being distributed the present invention is based on Bernoulli Jacob
Figure.
Fig. 2 is the schematic diagram of beta distributions.
Fig. 3 is the simplified electrical circuit diagram of SRAM circuit in embodiment 1.
Fig. 4 is the error comparing result that SRAM circuit is obtained using different yield analysis methods.
Fig. 5 is the error comparing result that the silicon chip that two batches manufacture is completed is obtained using different yield analysis methods.
To keep the above objects, features and advantages of the present invention more obvious and easy to understand, below by several specific examples
It further illustrates.
Specific implementation mode
The representative instance of method the present invention is based on the Bayesian model hybrid predicting circuit yield of Bernoulli Jacob's distribution is
One work station comprising 4GB memories, 2.66GHz processors and hard disk drive, which, which executes, realizes that being based on uncle exerts
The method BMF-BD of the Bayesian model hybrid predicting circuit yield of profit distribution.
Embodiment 1
Use the SRAM circuit of 65nmCMOS technological designs（As shown in Figure 3）, read path and consist of the following parts：SRAM
6 pipe units, sequential logic and sense amplifier；Once wordline WL is activated, bit line BL and BL_ start to discharge, according to 6 pipe lists
The difference of numerical value storage inside member, result of the comparison is exported by sense amplifier：0 or 1, the result as reading exports,
Due to the relationship of the fluctuation in manufacture, circuit has a probability of certain error of performance, namely the result that reads and physical holding of the stock
It is not inconsistent；
In order to which method proposed by the present invention to be compared with the precision of traditional analysis method, will be used in the present embodiment
BMF-BD and two methods of Monte Carlo carried out the analysis of yield rate；
First, the circuit before placement-and-routing is run to obtain 5000 Monte Carlo simulation points using hspice, obtains this
When yield rate be β E=89.88%；In practical applications, it is believed that these information are exactly known before post-simulation, are obtained in this way
The result emulated before obtaining need not just take additional time cost again；Later, 5000 points of post-simulation point is taken, its yield rate is acquired
βEXACT=90.66%, then a small amount of point is taken in this 5000 points, it is separately operable BMF-BD methods and estimates finished product with monte carlo method
Rate, make points from 20 to 200 between change, estimate relative error：
The relationship of relative error and points variation is drawn on figure by the error that the randomness in order to eliminate sampling site is brought（Such as
Shown in Fig. 4）, it shows in figure, even if post-simulation point only has 20,
BMF-BD methods can also obtain relatively good precision, and in order to reach same precision, monte carlo method is at least
160 points are needed, since the time of operation BMF-BD methods is negligible, that is to say, that this method is than traditional
The speed that monte carlo method has obtained 8 times is promoted.
2 one silicon test examples of embodiment
Test a silicon chip（From a main semiconductor company）, former and later two test results from two batches it is different at
The number of product, the two batches finished product is respectively 2305 and 2010 test points；In the present embodiment, each chip is marked as " logical
Cross " or " not passing through ", the yield rate measured by front and back two batches be respectively βE=90.63%, βEXACT=90.25%, wherein preceding batch of
Yield rate test result is regarded as the information of last stage；
The relationship of similar embodiment 1, relative error and points variation is drawn on figure（As shown in Figure 5）, the results show that BMF-
BD methods are showing clear superiority, in order to reach the same precision, when monte carlo method needs at 200, and the side BMF-BD
Method only needs 20 points, the speed that this method has reached 10 times to be promoted.
Above-described embodiment the result shows that, in terms of existing technologies, BMF-BD methods of the invention are in precision and speed
There is very strong competitiveness on degree, be a kind of yield prediction method of highly effective.
Claims (2)
1. a kind of method of the Bayesian model hybrid predicting circuit yield based on Bernoulli Jacob's distribution, which is characterized in that it is wrapped
Include step：
Step 201：The data of last stage and rear stage are read, those data are encoded to the format of " 0-1 " through anticipating,
In, 0 represents not by test, and 1, which represents test, passes through；
Step 202：Obtained data are divided into two groups, wherein：For the applicable cases emulated before flow, corresponding is layout cloth
Emulation and placement-and-routing's post-simulation before line；For the application tested after flow, corresponding is relatively early batch of test result and most
New batch of test result；
Step 203：
In conjunction with the data that the rear stage obtains, the value of hyper parameter a is obtained using maximum likelihood method：
In above formula, βEIndicate that the known yield rate of previous stage, β indicate that the latter half needs the yield rate estimated；X representatives take
The rear number of stages strong point obtained, for M characterizations wherein by the data point number of test, the test result is " 1 ", and N is total data
Point number；
p(x,β|When a) indicating known hyper parameter a, the joint probability density of x and β；p(x|When β) indicating known β, the probability of x is close
Degree；p(β|When a) indicating known hyper parameter a, the probability density of β；Above formula integrates β from 0 to 1：
In order to enable above formula maximum is to obtain the possibility maximum of observed result x, it is optimal using the method acquisition one of linear search
Hyper parameter a meet following formula：
Wherein, the size of hyper parameter is characterized firmly believes degree for prior information；
Step 204：Posteriority yield rate is obtained using maximum a posteriori；
According to Bayesian formula, the Posterior distrbutionp of parameter beta is proportional to the product of prior distribution and likelihood function：
It is obtained by normalization：
Above formula is the Posterior distrbutionp expression formula of parameter beta, it can be seen that the formula is also a beta distribution, when value obtains maximum
Parameter beta value be Bayesian model fusion method estimation yield rate：
Step 205：The finished product rate score β that output estimation obtainsMAP。
2. method as described in claim 1, which is characterized in that pass through the yield rate to the last stage in the step 202
Study, prior information is encoded in an appropriate form, specifically as follows step by step：
Step by step 21：The yield rate of last stage is acquired using maximum likelihood method：
Since the test output of circuit only has two " 0-1 ", therefore, it is considered that being a stochastic variable for thering is Bernoulli Jacob to be distributed：
Its statistical property is expressed as：
Wherein, β ∈ [0,1]The yield rate to be estimated is represented,
According to formula：
Obtain the yield information of last stage, wherein M is the points by test in the last stage, and N is the point for participating in test in total
Number；
Step by step 22：The uncertainty for characterizing the yield rate and the yield rate in rear stage of last stage, parameter beta to be estimated is regarded as
One stochastic variable with beta distributions：
Wherein, a, b are referred to as hyper parameter, they control probability density function p (β |A, b) shape, this beta function exists
Some specific value βMOn get maximum, the expression formula of the particular value is：
Constraint is fixed to hyper parameter a, b, enables βMIt is equal with the yield rate that the last stage obtains：
The distribution expression formula writing of parameter beta as a result,：
Above formula is the expression formula of prior information.
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| CN101996266A (en) * | 2009-08-21 | 2011-03-30 | 复旦大学 | Method for establishing space correlation model of technical error in integrated circuit chip |
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| JP2008027481A (en) * | 2006-07-18 | 2008-02-07 | Toshiba Corp | Information recording medium, information recording and reproducing apparatus, inspecting method of information recording medium, and inspection apparatus of information recording medium |
| US8117568B2 (en) * | 2008-09-25 | 2012-02-14 | International Business Machines Corporation | Apparatus, method and computer program product for fast simulation of manufacturing effects during integrated circuit design |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101038602A (en) * | 2007-04-19 | 2007-09-19 | 复旦大学 | Clock deviation arrangement method driven by production yield under technique parametric variation |
| CN101996266A (en) * | 2009-08-21 | 2011-03-30 | 复旦大学 | Method for establishing space correlation model of technical error in integrated circuit chip |
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| 分层线性模型的最大后验估计;张璇;《统计与信息论坛》;20110131;第26卷(第1期);第10-16页 * |
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