CN104978448B - Bayesian model hybrid predicting circuit yield method based on Bernoulli Jacob's distribution - Google Patents

Abstract

The method belongs to the field of integrated circuits, and relates to a method for predicting circuit yield based on a Bayesian model mixed with Bernoulli distribution. The method speeds up the process of yield estimation for circuits with only "pass-fail" states by combining information at different stages of integrated circuit design. This method establishes a Bernoulli model for the output result of "pass-fail", sets the prior yield rate as beta distribution, and uses the maximum likelihood method to determine the hyperparameters in the beta distribution. Then use this hyperparameter, combined with a relatively small amount of posterior information, to estimate the yield of the integrated circuit. Compared with the traditional Monte-Carlo method for estimating the yield, this method requires much less posterior information while achieving the same accuracy, which can significantly save the time for post-simulation or a new test.

Description

Bayesian Model Hybrid Prediction Method for Circuit Yield Based on Bernoulli Distribution

technical field

The method belongs to the field of integrated circuits, and specifically relates to a method for predicting circuit yield based on a Bayesian model mixed with Bernoulli distribution.

technical background

Studies have shown that the continuous shrinking of integrated circuit dimensions has led to large uncertainties in the manufacturing process, including parametric fluctuations and certain fatal defects, both of which may cause serious yield losses . Therefore, no matter in the pre-silicon verification or post-silicon testing stage, in order to improve circuit performance or reduce manufacturing costs, accurate estimation of yield is a very important task.

Recently, a series of new design methods (such as post-silicon wafer regulation) have been proposed in the prior art to solve the problem of chip fluctuations in order to maintain the current pace of continuous shrinking of integrated circuit dimensions. These new design methods have been shown to be very effective in practice, but in turn make the complexity of today's integrated circuits continue to increase. This situation leads to the need to collect a very large number of random data samples when estimating the yield rate, such as:

Verification before tape-out: It is necessary to run post-layout simulation, and the simulation of a complex circuit is very time-consuming nowadays;

Post-silicon testing: It is necessary to test the actual silicon wafer to determine whether the chip is "passed" or "failed". Practice has shown that this task is not simple, and only a small part of the silicon wafer is fully tested. is acceptable.

In order to solve this problem related to data collection, a mixture of Bayesian models is used to accurately estimate the statistical parameters (performance distribution, yield) of the circuit. The Bayesian model mixture method borrows prior information (such as pre-simulation information) to accurately estimate posterior statistical parameters. This method can effectively reduce the cost of verification and testing in the posterior stage. However, the traditional Bayesian model hybrid method can only effectively deal with continuously distributed performance parameters (such as the delay of digital circuits, the gain of analog amplifiers, etc.). This is because the traditional method assumes that the actual performance distribution is continuous. In many practical applications, the delay of the critical path cannot be accurately obtained by testing a silicon chip; often it is only possible to know whether the chip meets the requirements or not. Satisfied, therefore, the traditional Bayesian model mixture method is still not applicable to accurately estimate the statistical parameters of the circuit.

The prior art relevant to the present invention has following references:

[1] X. Li, J. Le and L. Pileggi, Statistical Performance Modeling and Optimization, Now Publishers, 2007.

[2] Semiconductor Industry Associate, International Technology Roadmap for Semiconductors, 2011.

[3] A. Srivastava, S. Shah, K. Agarwal, D. Sylvester, D. Blaauwand and S. Director, "Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance," IEEE DAC, pp.535-540.

[4] X. Li, J. Le, P. Gopalakrishnan and L. Pileggi, "Asymptotic probability extraction for nonnormal performance distributions," IEEETrans.onCAD, vol.26, no.1, pp.16-37, Jan.2007.

[5] P. Desrumaux, Y. Dupret, J. Tingleft, S. Minehane, M. Redford, L. Latorre and P. Nouet, "An efficient control variables method for yield estimation of analog circuits based on a local model," IEEEIC CAD, pp.415-421, 2012.

[6] S. Mitra, S. Seshia and N. Nicolici, "Post-silicon validation opportunities, challenges and recent advances," IEEEDAC, pp.12-17, 2010.

[7] X.Li, "Post-silicon performance modeling and tuning of analog/mixed-signal circuits via Bayesian model fusion," IEEEIC CAD, pp.551-552, 2012.

[8] J. Rivers, M. Gupta, J. Shin, P. Kudva and P. Bose, "Error tolerance in server class processors," IEEETrans.onCAD, vol.30, no.7, pp.945-959, Jul.2011.

[9] A. Tang, F. Hsiao, D. Murphy, I. Ku, J. Liu, S. Souza, N. Wang, H. Wu, Y. Wang, M. Tang, G. Virbila, M. Pham , D.Yang, Q.Gu, Y.Wu, Y.Kuan, C.Chien, M.Chang, "Alow-overheadself-healingembeddedsystemforensuringhighieldandlong-termssustainabilityof60GHz4Gb/sradio-on-a-chip", IEEEISSCC, pp.316- 318, 2012.

[10] B. Sadhu, M. Ferriss, A. Natarajan, S. Yaldiz, J. Plouchart, A. Rylyakov, A. Valdes-Garcia, B. Parker, A. Babakhani, S. Reynolds, X. Li, L. .Pileggi, R.Harjani, J.Tierno and D.Friedman, "Alinearized, low-phase-noise VCO-based 25GHz PLL with autonomic biasing," IEEEJSSC, vol.48, no.5, pp.1138-1150, May.2013.

[11] P. Gupta, Y. Agarwal, L. Dolecek, N. Dutt, R. Gupta, R. Kumar, S. Mitra, A. Nicolau, T. Rosing, M. Srivastava, S. Swanson and D. Sylvester," Underdesigned and opportunisticcomputinginpresenceofhardwarevariability,"IEEETrans.onCAD,vol.32,no.1,pp.8-23,Jan.2013.

[12]X.Li, W.Zhang, F.Wang, S.Sun and C.Gu, "Efficient parametric ield estimation of analog/mixed-signal circuits via Bayesian model fusion," IEEE ICCAD, pp.627-634, 2012.

[13] C. Gu, E. Chiprout and X. Li, “Efficient moment estimation with extremely small samplesize via Bayesian inference for analog/mixed-signal validation,” IEEE DAC, 2013.

Contents of the invention

The purpose of the present invention is to overcome the defects in the prior art, and provide a Bayesian model mixing method based on Bernoulli distribution, which is used for mixing prediction circuit yield.

The method speeds up the process of yield estimation for circuits with only "go-no-go" states by combining information from different stages of integrated circuit design. This method establishes a Bernoulli model for the output result of "pass-fail", sets the prior yield rate as beta distribution, and uses the maximum likelihood method to determine the hyperparameters in the beta distribution. Then use this hyperparameter, combined with a relatively small amount of posterior information, to estimate the yield of the integrated circuit. Compared with the traditional Monte-Carlo method for estimating the yield, this method requires much less posterior information while achieving the same accuracy, which can significantly save the time for post-simulation or a new test.

The method of the present invention can effectively handle the situation when the simulation or test that the traditional method cannot handle produces a binary output; for the test situation with only two output states of "pass-fail", only the prior yield and The posterior yield is close within a certain range, and the present invention can significantly reduce the number of posterior data points to be collected while achieving the same accuracy, thereby greatly reducing the cost of verification and testing.

In order to achieve the above object, the technical solution of the present invention is: a method (BMF-BD) for estimating the yield rate based on the Bayesian model of Bernoulli distribution, which can be described in Figure 1, and its steps are as follows:

Step 201: Read the data of the previous stage and the latter stage. These data have been pre-processed and encoded into the format of "0-1", 0 means the test failed, and 1 means the test passed;

Step 202: The obtained data are divided into two groups: for the application of pre-silicon simulation, corresponding to the pre-layout simulation (pre-stage) and post-layout simulation (post-stage), for the application of post-silicon test, corresponding to The test results of the earlier batch (pre-stage) and the latest batch of test results (post-stage); in this step, through the learning of the yield rate of the previous stage, the prior information is encoded in a suitable form, and its Including sub-step 21 and sub-step 22:

Sub-step 21: Use the maximum likelihood method to obtain the yield of the previous stage:

Since the test output of the circuit has only two bits "0-1", it can be considered as a random variable with Bernoulli distribution:

Its statistical properties can be expressed as:

Among them, β∈[0,1] represents the estimated yield;

According to the formula

You can get the yield information of the previous stage, where M is the number of points that passed the test in the previous stage, and N is the total number of points that participated in the test;

Sub-step 22: The yield rate of the former stage is generally different from that of the latter stage, but because the circuits of the former stage and the latter stage are similar, the yield rate of the latter stage should be similar to that of the former stage. In order to represent such uncertainties, we will The parameter β to be estimated is regarded as a random variable with a beta distribution:

Among them, a and b are called hyperparameters, and they control the shape of the probability density function (as shown in Figure 2). This beta function is maximized at a specific value β _M , and the expression of the specific value for:

In order to set constraints on the hyperparameters a and b, let β _M be equal to the yield obtained in the previous stage:

Therefore, the distribution expression for the parameter β can also be written as:

The above formula is the expression of prior information;

Step 203:

In order to obtain the value of the hyperparameter a in the above formula, combined with the data obtained in the later stage, the maximum likelihood method is used to obtain its value:

In the above formula, x represents the data points obtained in the later stage, M represents the number of data points that passed the test (the result is "1"), N is the total number of data points, and the above formula is integrated from 0 to 1 for β :

In order to maximize the above formula (that is, to obtain the maximum possible observation result x), use the linear search method to obtain an optimal hyperparameter a that satisfies the following formula:

The size of the hyperparameters characterizes the degree of confidence in the prior information;

Step 204: Use the maximum a posteriori method to obtain the posterior yield. According to the Bayesian formula, the posterior distribution of the parameter β is proportional to the product of the prior distribution and the likelihood function:

After normalization, we get:

The above formula is the posterior distribution expression of the parameter β. It can be seen that this formula is also a beta distribution, and the value of the parameter β when its value is maximized is the yield rate estimated by the BMF method:

Step 205: Output the estimated yield value β _MAP .

The method of the present invention has the following advantages for the circuit yield estimation with binary output:

1. Combining prior information and posterior information, compared with the traditional Monte Carlo method, the number of posterior points required to achieve the same accuracy is relatively small, which significantly reduces the time and other costs required for test verification.

2. Compared with the BMF method in the prior art, this method can deal with circuits with only two states of "pass-fail", which is practical and practical.

Description of drawings

FIG. 1 is a flowchart of a method for predicting circuit yield based on a Bernoulli distribution-based Bayesian model of the present invention.

Figure 2 is a schematic diagram of the beta distribution.

FIG. 3 is a simplified circuit diagram of the SRAM circuit in Embodiment 1. FIG.

Figure 4 shows the error comparison results obtained by using different yield analysis methods for SRAM circuits.

Fig. 5 is the error comparison result obtained by using different yield analysis methods for two batches of manufactured silicon wafers.

In order to make the above objects, features and advantages of the present invention more obvious and understandable, several specific examples are used to further illustrate below.

Detailed ways

A typical example of the method for predicting circuit yield based on the Bayesian model of Bernoulli distribution in the present invention is a workstation that includes 4GB memory, a 2.66GHz processor and a hard disk drive. Yassian Model Hybrid Method for Predicting Circuit Yield BMF-BD.

Example 1

The SRAM circuit designed using 65nm CMOS process (as shown in Figure 3), its read path consists of the following parts: SRAM 6-tube unit, sequential logic and sensitive amplifier; once the word line WL is activated, the bit lines BL and BL_ start to discharge , according to the difference of the stored value inside the 6-tube unit, the comparison result is output by the sensitive amplifier: 0 or 1, which is output as the read result. Due to the fluctuation in the manufacturing process, the circuit has a certain probability of working error, and also That is, the read result does not match the actual stored one;

In order to compare the accuracy of the method proposed by the present invention with the traditional analysis method, the BMF-BD and Monte Carlo methods to be used in this embodiment have carried out the analysis of the yield;

First, use hspice to run the circuit before layout and routing to get 5000 Monte Carlo simulation points, and the yield rate at this time is βE=89.88%. In practical applications, it is considered that this information is known before post-simulation, so There is no need to spend extra time to obtain the results of the pre-simulation; after that, take 5000 points of the post-simulation point to obtain its yield β _EXACT = 90.66%, and then take a small number of points from these 5000 points and run BMF-BD respectively Method and Monte Carlo method to estimate the yield, make the number of points change from 20 to 200, and estimate the relative error:

In order to eliminate the error caused by the randomness of the sampling points, the relationship between the relative error and the change of the number of points is drawn in the figure (as shown in Figure 4). The figure shows that even if there are only 20 post-simulation points,

The BMF-BD method can also obtain relatively good accuracy. In order to achieve the same accuracy, the Monte Carlo method needs at least 160 points. Since the time for running the BMF-BD method is negligible, that is to say, this method is faster than the traditional method. The Monte Carlo method got an 8x speedup.

Example 2 of a silicon wafer test

Test a silicon chip (from a major semiconductor company), the two test results come from two different batches of finished products, the numbers of the two batches of finished products are 2305 and 2010 test points respectively; in this embodiment, each chip is marked It is "Pass" or "Fail", and the yield rate measured by the two batches before and after is β _E =90.63%, β _EXACT =90.25%, among them, the yield test result of the previous batch is regarded as the information of the previous stage ;

Similar to Example 1, the relationship between the relative error and the number of points is plotted in the figure (as shown in Figure 5). The results show that the BMF-BD method shows obvious advantages. In order to achieve the same accuracy, the Monte Carlo method needs 200 points When , the BMF-BD method only needs 20 points, and this method achieves a 10-fold speedup.

The results of the above examples show that, compared with the prior art, the BMF-BD method of the present invention is highly competitive in accuracy and speed, and is an efficient and practical yield prediction method.

Claims (2)

1. a kind of method of the Bayesian model hybrid predicting circuit yield based on Bernoulli Jacob's distribution, which is characterized in that it is wrapped Include step：

Step 201：The data of last stage and rear stage are read, those data are encoded to the format of " 0-1 " through anticipating, In, 0 represents not by test, and 1, which represents test, passes through；

Step 202：Obtained data are divided into two groups, wherein：For the applicable cases emulated before flow, corresponding is layout cloth Emulation and placement-and-routing's post-simulation before line；For the application tested after flow, corresponding is relatively early batch of test result and most New batch of test result；

Step 203：

In conjunction with the data that the rear stage obtains, the value of hyper parameter a is obtained using maximum likelihood method：

In above formula, β_EIndicate that the known yield rate of previous stage, β indicate that the latter half needs the yield rate estimated；X representatives take The rear number of stages strong point obtained, for M characterizations wherein by the data point number of test, the test result is " 1 ", and N is total data Point number；

p(x,β|When a) indicating known hyper parameter a, the joint probability density of x and β；p(x|When β) indicating known β, the probability of x is close Degree；p(β|When a) indicating known hyper parameter a, the probability density of β；Above formula integrates β from 0 to 1：

In order to enable above formula maximum is to obtain the possibility maximum of observed result x, it is optimal using the method acquisition one of linear search Hyper parameter a meet following formula：

Wherein, the size of hyper parameter is characterized firmly believes degree for prior information；

Step 204：Posteriority yield rate is obtained using maximum a posteriori；

According to Bayesian formula, the Posterior distrbutionp of parameter beta is proportional to the product of prior distribution and likelihood function：

It is obtained by normalization：

Above formula is the Posterior distrbutionp expression formula of parameter beta, it can be seen that the formula is also a beta distribution, when value obtains maximum Parameter beta value be Bayesian model fusion method estimation yield rate：

Step 205：The finished product rate score β that output estimation obtains_MAP。

2. method as described in claim 1, which is characterized in that pass through the yield rate to the last stage in the step 202 Study, prior information is encoded in an appropriate form, specifically as follows step by step：

Step by step 21：The yield rate of last stage is acquired using maximum likelihood method：

Since the test output of circuit only has two " 0-1 ", therefore, it is considered that being a stochastic variable for thering is Bernoulli Jacob to be distributed：

Its statistical property is expressed as：

Wherein, β ∈ [0,1]The yield rate to be estimated is represented,

According to formula：

Obtain the yield information of last stage, wherein M is the points by test in the last stage, and N is the point for participating in test in total Number；

Step by step 22：The uncertainty for characterizing the yield rate and the yield rate in rear stage of last stage, parameter beta to be estimated is regarded as One stochastic variable with beta distributions：

Wherein, a, b are referred to as hyper parameter, they control probability density function p (β |A, b) shape, this beta function exists Some specific value β_MOn get maximum, the expression formula of the particular value is：

Constraint is fixed to hyper parameter a, b, enables β_MIt is equal with the yield rate that the last stage obtains：

The distribution expression formula writing of parameter beta as a result,：

Above formula is the expression formula of prior information.