CN104967579A - Switch MAC address synchronization method and system - Google Patents
Switch MAC address synchronization method and system Download PDFInfo
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- CN104967579A CN104967579A CN201510373555.5A CN201510373555A CN104967579A CN 104967579 A CN104967579 A CN 104967579A CN 201510373555 A CN201510373555 A CN 201510373555A CN 104967579 A CN104967579 A CN 104967579A
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- mac address
- exchange chip
- spatial cache
- variation message
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
Abstract
The invention provides a synchronous and asynchronous combined switch MAC address synchronization method and system. When a few of change messages which need to be synchronized are sent by an exchange chip, a synchronous processing approach is used. When a lot of change messages which need to be synchronized are sent by the exchange chip, an asynchronous processing approach is used. The method and the system have synchronous and asynchronous advantages, and can effectively overcome disadvantages caused by a synchronous approach used alone.
Description
Technical field
The present invention relates to a kind of synchronous method, particularly relate to the switch mac address synchronous method in a kind of switch being applied to many exchange chips and system.
Background technology
Present switch generally all comprises a master cpu and polylith exchange chip is formed.Every block exchange chip has oneself mac address table, is safeguarded by exchange chip hardware itself, meanwhile, there is one the is carried out software maintenance overall software register comprising all exchange chip MAC Address within the scope of whole switch system by master cpu in switch.When the mac address table of certain block exchange chip changes, this block exchange chip hardware will produce message informing master cpu, master cpu is by the MAC Address message of resolving exchange chip hardware and reporting and make respective handling in conjunction with overall software register, upgrade overall software register and be synchronized in the mac address table of all exchange chips, whole like this switch system two layers forwards could be normal.If the message that incorrect processing and exchanging chip address changes, the mac address table of each exchange chip of whole switch system will be caused inconsistent, and two layers of forwarding capability of switch just there will be exception.
And software synchronization exchange chip mac address table has two kinds of modes: synchronous and asynchronous.When synchronously referring to that CPU receives exchange chip MAC Address change message, process immediately; When the asynchronous CPU of referring to receives exchange chip MAC Address change message, first keep in message queue, wait the lighter time delay reprocessing of cpu load.The method of synchronization is suitable for MAC Address, and to change message less, and advantage is that real-time is good, and it is low that shortcoming is that MAC Address changes message cpu busy percentage of many time; It is more that asynchronous system is suitable for MAC Address change message, and advantage is that cpu busy percentage is high, and shortcoming is that synchronous real-time is slightly poor.
Therefore, the present invention proposes switch mac address synchronous method that a kind of synchronous and asynchronous combines and system, effectively to overcome the simple drawback using a kind of method of synchronization to bring.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of switch mac address synchronous method and system, for solving in prior art the simple problem using synchronous or asynchronous a kind of like this method of synchronization to bring.
For achieving the above object and other relevant objects, the invention provides a kind of switch mac address synchronous method, it is applied to one and comprises in the switch system of master cpu and multiple exchange chip, when the mac address table of one of them exchange chip changes, this exchange chip hardware will produce a variation message, and be sent in this master cpu, it is characterized in that, this switch mac address synchronous method comprises: 1) make this master cpu by temporary for sent a variation message spatial cache; 2) this master cpu is made to be temporary in the quantity of the variation message in this spatial cache every a scheduled time statistics; 3) whether the quantity of adding up is not more than a predetermined number value, if so, then proceeds to step 4 to make this master cpu judge), if not, then proceed to step 5); 4) process of the employing method of synchronization is temporary in all variation message in this spatial cache; And 5) adopt asynchronous system process to be temporary in all variation message in this spatial cache.Wherein, this master cpu also prestores an overall software register comprising the MAC Address of all exchange chips.And in one embodiment, this spatial cache is first-in first-out (First Input FirstOutput; FIFO) message queue, but not as limit.
Preferably, above-mentioned steps 4) comprise further: 4-1) make this master cpu resolve all variation message be temporary in this spatial cache, and obtain the change entry that should change message number for a pair, and remove all variation message of executed dissection process in this spatial cache; This master cpu 4-2) is made to be synchronized in the overall software register be stored in this master cpu by obtained all change entries; And 4-3) make this master cpu according to obtained all change entries, whether the mac address table searched one by one in each exchange chip has stored above-mentioned change entry, if, then simultaneous operation is not carried out to the exchange chip storing above-mentioned change entry, if not, then above-mentioned change entry is updated in the mac address table of the exchange chip not storing above-mentioned change entry.Above-mentioned steps 5) comprise further: 5-1) make this master cpu judge current load whether excess load, if not, then proceed to step 5-2), if so, then repeat above-mentioned determining step; 5-2) make this master cpu resolve all variation message be temporary in this spatial cache, and obtain a change entry, and remove all variation message of executed dissection process in this spatial cache; This master cpu 5-3) is made to be synchronized in this overall software register by obtained change entry; And 5-4) make this master cpu according to obtained change entry, whether the mac address table searched one by one in each exchange chip has stored above-mentioned change entry, if, then simultaneous operation is not carried out to the exchange chip storing above-mentioned change entry, if not, then above-mentioned change entry is updated in the mac address table of the exchange chip not storing above-mentioned change entry.
In addition, the present invention also provides a kind of switch mac address synchro system, being applied to one comprises in the switch system of master cpu and multiple exchange chip, when the mac address table of one of them exchange chip changes, this exchange chip hardware will produce a variation message, and is sent in this master cpu, it is characterized in that, this switch mac address synchro system comprises: memory module, and the variation message in order to be sent by this exchange chip is kept in in a spatial cache; Statistical module, in order to add up the quantity of the variation message of keeping in this spatial cache every a scheduled time; And processing module, in order to judge whether the quantity that this statistical module is added up is not more than a predetermined number value, if so, then the process of the employing method of synchronization is temporary in all variation message in this spatial cache, if not, then the process of employing asynchronous system is temporary in all variation message in this spatial cache.Wherein, this memory module also prestores an overall software register comprising the MAC Address of all exchange chips.And this spatial cache can be such as first-in first-out message queue, but not as limit.
Specifically, the step of all variation message that the process of the above-mentioned employing method of synchronization is temporary in this spatial cache comprises further: this processing module resolves all variation message be temporary in this spatial cache, and obtain the change entry that should change message number for a pair, and remove all variation message of executed dissection process in this spatial cache, then, obtained all change entries are synchronized in this overall software register, again according to obtained all change entries, whether the mac address table searched one by one in each exchange chip has stored above-mentioned change entry, if, then simultaneous operation is not carried out to the exchange chip storing above-mentioned change entry, if not, then above-mentioned change entry is updated in the mac address table of the exchange chip not storing above-mentioned change entry.
And all variation message that the process of above-mentioned employing asynchronous system is temporary in this spatial cache comprise further: this processing module judges the current load of this master cpu whether excess load, if, then repeat above-mentioned determining step, if not, then resolve all variation message be temporary in this spatial cache, and obtain the change entry that should change message number for a pair, and remove all variation message of executed dissection process in this spatial cache, then, obtained all change entries are synchronized in this overall software register, again according to obtained all change entries, whether the mac address table searched one by one in each exchange chip has stored above-mentioned change entry, if, then simultaneous operation is not carried out to the exchange chip storing above-mentioned change entry, if not, then above-mentioned change entry is updated in the mac address table of the exchange chip not storing above-mentioned change entry.
Preferably, above-mentioned memory module, statistical module and processing module are all realized by this master cpu.
As mentioned above, the present invention proposes switch mac address synchronous method that a kind of synchronous and asynchronous combines and system, when exchange chip synchronization message is less, adopt synchronous processing mode, when exchange chip synchronization message is more, adopt asynchronous processing mode, there is the advantage of synchronous and asynchronous so simultaneously, can effectively overcome its shortcoming again.
Accompanying drawing explanation
Fig. 1 is shown as the block schematic diagram of switch mac address synchro system of the present invention.
The operational flowchart of Fig. 2 display application switch mac address synchronous method of the present invention.
Element numbers explanation
1 switch
10 master cpus
100 switch mac address synchro systems
101 memory modules
1011 spatial caches
102 statistical modules
103 processing modules
11 ~ 14 exchange chips
S100 ~ S162 step
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.It should be noted that, when not conflicting, the feature in following examples and embodiment can combine mutually.
It should be noted that, the diagram provided in following examples only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
Refer to Fig. 1, the invention provides a kind of switch mac address synchro system, it is applied to one and comprises master cpu 10 and multiple exchange chip (illustrates 4 exchange chips herein, be respectively exchange chip 11,12,13,14, but not as limit) switch system in, as shown in Figure 1, switch mac address synchro system 100 of the present invention comprises memory module 101, statistical module 102 and processing module 103.In the present embodiment, above-mentioned memory module 101, statistical module 102 and processing module 103 are all realized by master cpu 10, wherein, when the mac address table of one of them exchange chip changes, this exchange chip hardware will produce a variation message, and be sent in this master cpu 10, namely switch mac address synchro system of the present invention is described in detail below.
As shown in Figure 1, this memory module 101 is that the variation message in order to be sent by this exchange chip is kept in in a spatial cache 1011, and in addition, this memory module 101 also prestores an overall software register comprising the MAC Address of all exchange chips.Wherein, this spatial cache 1011 is first-in first-out message queue, but not as limit.
This statistical module 102 is the quantity in order to add up the variation message of keeping in this spatial cache 1011 every a scheduled time.
This processing module 103 judges whether the quantity that this statistical module 102 is added up is not more than a predetermined number value, if, then the process of the employing method of synchronization is temporary in all variation message in this spatial cache 1011, if not, then the process of employing asynchronous system is temporary in all variation message in this spatial cache 1011.
Specifically, when needing to adopt method of synchronization process to be temporary in all variation message in this spatial cache 1011, namely this processing module 103 resolves all variation message be temporary in this spatial cache 1011, and obtain the change entry that should change message number for a pair, and remove all variation message of executed dissection process in this spatial cache 1011, then, obtained all change entries are synchronized in this overall software register, again according to obtained all change entries, whether the mac address table searched one by one in each exchange chip has stored above-mentioned change entry, if, then simultaneous operation is not carried out to the exchange chip storing above-mentioned change entry, if not, then above-mentioned change entry is updated in the mac address table of the exchange chip not storing above-mentioned change entry.So, when the MAC Address variation of exchange chip is less (when being not more than above-mentioned predetermined number value), the method for synchronization can be adopted to process the synchronous event of MAC Address immediately, and synchronous real-time is good.
And when needing to adopt asynchronous system process to be temporary in all variation message in this spatial cache 1011, first namely this processing module 103 judge the current load of this master cpu 10 whether excess load, if, then repeat above-mentioned determining step, if not, then resolve all variation message be temporary in this spatial cache 1011, and obtain the change entry that should change message number for a pair, and remove all variation message of executed dissection process in this spatial cache 1011, then, obtained all change entries are synchronized in this overall software register, again according to obtained all change entries, whether the mac address table searched one by one in each exchange chip has stored above-mentioned change entry, if, then simultaneous operation is not carried out to the exchange chip storing above-mentioned change entry, if not, then above-mentioned change entry is updated in the mac address table of the exchange chip not storing above-mentioned change entry.So, when the MAC Address variation of exchange chip is more (when being greater than above-mentioned predetermined number value), asynchronous system (when the load that master cpu 10 is current is lighter) can be adopted to process the synchronous event of MAC Address, and the utilance of CPU is high.
Refer to Fig. 2, be the above-mentioned switch mac address synchro system of display application, perform the operating process schematic diagram of switch mac address synchronous method of the present invention.Namely below composition graphs 1 to add up the quantity of the variation message obtained to switch mac address synchronous method of the present invention and the operating procedure that performs is described in detail for single predetermined period of time.
As shown in Figure 1, first, step S100 is performed, in the temporary spatial cache of the variation message making this master cpu be sent by exchange chip.Then, step S110 is carried out.
In step s 110, this master cpu is made to add up the quantity of the variation message be temporary within a scheduled time in this spatial cache.Then, step S120 is carried out.
In the step s 120, whether the quantity of adding up is not more than a predetermined number value, if so, then proceeds to step S131, if not, then proceeds to step S132 to make this master cpu judge.
In step S131, make this master cpu resolve all variation message be temporary in this spatial cache, and obtain the change entry that should change message number for a pair, and remove all variation message of executed dissection process in this spatial cache.Then, step S140 is carried out.
In step S132, make this master cpu judge current load whether excess load, if not, then proceed to step S131, if so, then repeat the judgement operation of this step.
In step S140, this master cpu is made obtained all change entries to be synchronized in the overall software register be stored in this master cpu.Then, step S150 is carried out.
In step S150, make this master cpu according to obtained each change entry, whether the mac address table searched one by one in each exchange chip has stored above-mentioned change entry, if so, then proceeds to step S161, if not, then proceeds to step S162.
In step S161, simultaneous operation is not carried out to the exchange chip storing above-mentioned change entry.
In step S162, above-mentioned change entry is updated in the mac address table of the exchange chip not storing above-mentioned change entry.
Above-mentioned steps S131 → S140 → S150 → S161 or S162 is all variation message that the synchronous mode process of employing is temporary in this spatial cache, and above-mentioned steps S132 → S131 → S140 → S150 → S161 or S162 is all variation message that the asynchronous mode process of employing is temporary in this spatial cache.
What need to be explained is herein, above-described embodiment only lists the simultaneous operation process that application switch mac address synchronous method of the present invention performs for the quantity being temporary in the variation message of spatial cache come out in the scheduled time, in actual application, above-mentioned master cpu is the quantity statistics work of the variation message namely performing spatial cache at interval of this scheduled time, once obtain the quantitative value of adding up, namely follow-up simultaneous operation (synchronous or asynchronous) is performed, during continuous after execution simultaneous operation can by added up quantity so that the follow-up variation message performing dissection process remove, not affect the simultaneous operation performed for the quantitative value come out in the next scheduled time.
For more detailed understanding application network file cloud synchronous method of the present invention, how to judge whether to need to upgrade the mac address table in exchange chip according to obtained change entry, below coordinate Fig. 1, and have 5 (wherein to be temporarily stored in the quantity changing message in this spatial cache 1011, article 3, be the variation message that the hardware of exchange chip 11 sends, other 2 variation message being the hardware of exchange chip 13 and sending) be described for example, so, the quantity of then resolving the change entry obtained also has 5, obviously, to 3 variation message and resolving sending of the hardware of exchange chip 11 3 of obtaining changing entries (for ease of describing, these 3 are changed entry and are defined as change entry L1 respectively, L2, L3) exist already in exchange chip 11, and to other 2 variation message and resolving of sending of the hardware of exchange chip 13 2 of obtaining changing entries (for ease of describing, these 2 are changed entry and are defined as change entry L4 respectively, L5) also exist already in exchange chip 13, therefore, when this master cpu 10 is according to obtained change entry, when whether the mac address table searched one by one in each exchange chip 11 ~ 14 has stored above-mentioned change entry, then can find that the mac address table in exchange chip 11 stores change entry (L1, L2 and L3), mac address table in exchange chip 12 and 14 does not store any change entry (L1 ~ L5), and the mac address table in exchange chip 13 stores change entry (L4, L5), now, namely this master cpu 10 does not carry out change entry (L1 to this exchange chip 11, L2 and L3) simultaneous operation, change entry (L4 is not carried out to this exchange chip 13, L5) simultaneous operation, and entry (L4 will be changed, L5) be updated in the mac address table of this exchange chip 11, and entry (L1 ~ L5) will be changed be updated in the mac address table of this exchange chip 12 and 14 respectively, and entry (L1 will be changed, L2 and L3) be updated in the mac address table of this exchange chip 13.So far, the simultaneous operation of the mac address table to each exchange chip is namely completed.
In sum, the invention provides a kind of switch mac address synchronous method and system, synchronous and asynchronous well combines by it, in less with the variation message that the need sent at exchange chip are synchronous, adopt synchronous processing mode, and when the variation message that the need of exchange chip transmission are synchronous is more, adopt asynchronous processing mode, there is the advantage of synchronous and asynchronous so simultaneously, effectively can overcome again and select separately a kind of method of synchronization and the shortcoming brought.So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (11)
1. a switch mac address synchronous method, being applied to one comprises in the switch system of master cpu and multiple exchange chip, when the mac address table of one of them exchange chip changes, described exchange chip hardware will produce a variation message, and be sent in described master cpu, it is characterized in that, described switch mac address synchronous method comprises:
1) make described master cpu by temporary for sent a variation message spatial cache;
2) described master cpu is made to be temporary in the quantity of the variation message in described spatial cache every a scheduled time statistics;
3) whether the quantity of adding up is not more than a predetermined number value, if so, then proceeds to step 4 to make described master cpu judge), if not, then proceed to step 5);
4) process of the employing method of synchronization is temporary in all variation message in described spatial cache; And
5) process of employing asynchronous system is temporary in all variation message in described spatial cache.
2. switch mac address synchronous method according to claim 1, is characterized in that: described master cpu also prestores an overall software register comprising the MAC Address of all exchange chips.
3. switch mac address synchronous method according to claim 2, is characterized in that: described step 4) comprise further:
4-1) make described master cpu resolve all variation message be temporary in described spatial cache, and obtain the change entry of a corresponding described variation message number, and remove all variation message of executed dissection process in described spatial cache;
4-2) making described master cpu obtained all change entries be synchronized to is stored in described overall software register; And
4-3) make described master cpu according to obtained all change entries, whether the mac address table searched one by one in each exchange chip has stored above-mentioned change entry, if, then simultaneous operation is not carried out to the exchange chip storing above-mentioned change entry, if not, then above-mentioned change entry is updated in the mac address table of the exchange chip not storing above-mentioned change entry.
4. switch mac address synchronous method according to claim 2, is characterized in that: described step 5) comprise further:
5-1) make described master cpu judge current load whether excess load, if not, then proceed to step 5-2), if so, then repeat above-mentioned determining step;
5-2) make described master cpu resolve all variation message be temporary in described spatial cache, and obtain the change entry of a corresponding described variation message number, and remove all variation message of executed dissection process in described spatial cache;
Described master cpu 5-3) is made to be synchronized in described overall software register by obtained change entry; And
5-4) make described master cpu according to obtained change entry, whether the mac address table searched one by one in each exchange chip has stored above-mentioned change entry, if, then simultaneous operation is not carried out to the exchange chip storing above-mentioned change entry, if not, then above-mentioned change entry is updated in the mac address table of the exchange chip not storing above-mentioned change entry.
5. the switch mac address synchronous method according to claim 1,3 or 4, is characterized in that: described spatial cache is first-in first-out message queue.
6. a switch mac address synchro system, being applied to one comprises in the switch system of master cpu and multiple exchange chip, when the mac address table of one of them exchange chip changes, described exchange chip hardware will produce a variation message, and be sent in described master cpu, it is characterized in that, described switch mac address synchro system comprises:
Memory module, the variation message in order to be sent by described exchange chip is kept in in a spatial cache;
Statistical module, in order to add up the quantity of the variation message of keeping in described spatial cache every a scheduled time; And
Processing module, in order to judge whether the quantity that described statistical module is added up is not more than a predetermined number value, if, then the process of the employing method of synchronization is temporary in all variation message in described spatial cache, if not, then the process of employing asynchronous system is temporary in all variation message in described spatial cache.
7. a kind of switch mac address synchro system according to claim 6, is characterized in that: described memory module also prestores an overall software register comprising the MAC Address of all exchange chips.
8. a kind of switch mac address synchro system according to claim 7, it is characterized in that: the step of all variation message that the process of the described employing method of synchronization is temporary in described spatial cache comprises further: described processing module resolves all variation message be temporary in described spatial cache, and obtain the change entry of a corresponding described variation message number, and remove all variation message of executed dissection process in described spatial cache, then, obtained all change entries are synchronized in described overall software register, again according to obtained all change entries, whether the mac address table searched one by one in each exchange chip has stored above-mentioned change entry, if, then simultaneous operation is not carried out to the exchange chip storing above-mentioned change entry, if not, then above-mentioned change entry is updated in the mac address table of the exchange chip not storing above-mentioned change entry.
9. a kind of switch mac address synchro system according to claim 7, it is characterized in that: all variation message that the process of described employing asynchronous system is temporary in described spatial cache comprise further: described processing module judges the current load of described master cpu whether excess load, if, then repeat above-mentioned determining step, if not, then resolve all variation message be temporary in described spatial cache, and obtain the change entry of a corresponding described variation message number, and remove all variation message of executed dissection process in described spatial cache, then, obtained all change entries are synchronized in described overall software register, again according to obtained all change entries, whether the mac address table searched one by one in each exchange chip has stored above-mentioned change entry, if, then simultaneous operation is not carried out to the exchange chip storing above-mentioned change entry, if not, then above-mentioned change entry is updated in the mac address table of the exchange chip not storing above-mentioned change entry.
10. a kind of switch mac address synchro system according to claim 6,8 or 9, is characterized in that: described spatial cache is first-in first-out message queue.
11. a kind of switch mac address synchro systems according to claim 6,8 or 9, is characterized in that: described memory module, statistical module and processing module are all realized by master cpu.
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| CN201510373555.5A CN104967579B (en) | 2015-06-30 | 2015-06-30 | Interchanger MAC address synchronizations method and system |
| PCT/CN2015/093002 WO2017000448A1 (en) | 2015-06-30 | 2015-10-28 | Method and system for synchronizing mac address of switch |
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| CN111464447A (en) * | 2020-04-08 | 2020-07-28 | 盛科网络（苏州）有限公司 | Method and device for synchronizing forwarding tables of ultra-bandwidth multi-core Ethernet switching chips |
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| CN115174676A (en) * | 2022-07-04 | 2022-10-11 | 深圳星云智联科技有限公司 | Convergence and shunt method and related equipment thereof |
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| CN111464447A (en) * | 2020-04-08 | 2020-07-28 | 盛科网络（苏州）有限公司 | Method and device for synchronizing forwarding tables of ultra-bandwidth multi-core Ethernet switching chips |
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