CN104966673A - Interface passivation method for improving the interface characteristic and electric leakage characteristic of AI203/InP MOS capacitor - Google Patents
Interface passivation method for improving the interface characteristic and electric leakage characteristic of AI203/InP MOS capacitor Download PDFInfo
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- CN104966673A CN104966673A CN201510393302.4A CN201510393302A CN104966673A CN 104966673 A CN104966673 A CN 104966673A CN 201510393302 A CN201510393302 A CN 201510393302A CN 104966673 A CN104966673 A CN 104966673A
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000002161 passivation Methods 0.000 title claims abstract description 23
- 239000003990 capacitor Substances 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 238000000231 atomic layer deposition Methods 0.000 claims abstract description 24
- 238000000151 deposition Methods 0.000 claims abstract description 24
- 230000008021 deposition Effects 0.000 claims abstract description 23
- 238000009832 plasma treatment Methods 0.000 claims description 30
- 239000012159 carrier gas Substances 0.000 claims description 14
- 238000004140 cleaning Methods 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 230000004907 flux Effects 0.000 claims description 7
- 230000008020 evaporation Effects 0.000 claims description 6
- 238000001704 evaporation Methods 0.000 claims description 6
- 230000007547 defect Effects 0.000 abstract description 22
- 238000000137 annealing Methods 0.000 description 11
- 230000000052 comparative effect Effects 0.000 description 10
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 8
- 238000005406 washing Methods 0.000 description 8
- 239000008367 deionised water Substances 0.000 description 7
- 229910021641 deionized water Inorganic materials 0.000 description 7
- 238000001259 photo etching Methods 0.000 description 7
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 7
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 6
- 238000011161 development Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000002791 soaking Methods 0.000 description 6
- 238000012546 transfer Methods 0.000 description 6
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- 239000006185 dispersion Substances 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 3
- 238000005566 electron beam evaporation Methods 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 239000003513 alkali Substances 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005527 interface trap Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000005554 pickling Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 239000002585 base Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
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- 239000002075 main ingredient Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000002207 thermal evaporation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Ceramic Engineering (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The invention discloses an interface passivation method for improving the interface characteristic and electric leakage characteristic of an AI203/InP MOS capacitor. The method includes a step of N2 plasma processing on the surface of a substrate and a gate medium deposition step, and the step of N2 plasma processing on the surface of the substrate and the gate medium deposition step are carried out in a TFS 200 atomic layer deposition system. The step of N2 plasma processing on the surface of the substrate is that the substrate is arranged in the cavity of the TFS 200 atomic layer deposition system and a plasma generator of the TFS 200 atomic layer deposition system generates N2 plasma to perform N2 plasma processing on the surface of the substrate, and the gate medium deposition step is that the substrate after being subjected to N2 plasma processing deposits gate mediums at the original position. According to the method, the boundary defects and the interface defects of an AI203/InP interface can be effectively passivated, and grid leakage current can be reduced.
Description
Technical field
The present invention relates to one and improve Al
2o
3the interface passivation method of/InP mos capacitance interfacial characteristics and leakage current characteristic, belongs to semiconductor material device field.
Background technology
Along with constantly reducing of CMOS (Complementary Metal Oxide Semiconductor) (CMOS) device feature size, the development of SiMOS device is close to its physics limit.Group III-V compound semiconductor material is considered to be one of substituting of silicon base CMOS channel material, and international many research institutions all start with Group III-V semiconductor the research of the MOSFET element being channel material.But, obtaining stable metal-oxide semiconductor (MOS) (MOS) interface is currently realize one of the severeest problem that iii-v MOSFET faces, this is because the instability at Group III-V semiconductor and gate medium interface can form iii-v natural oxide, iii-v natural oxide can worsen MOS interfacial characteristics, a series of problem can be caused, such as: fermi level pinning, C-V hysteresis, C-V frequency dispersion etc.Therefore, the MOS interface of an acquisition stable high-quality amount is needed.
InP, as one of the most promising Group III-V compound semiconductor, has high electron mobility (~ 5400cm
2/ Vs), but poor High-K/InP interface remains the one of the main reasons affecting InP MOSFET performance.In order to improve High-K/InP interface quality, InP surface passivation technique causes to be paid close attention to widely, and it can reduce dangling bonds and the natural oxide on InP substrate surface effectively, reduces interface state density, thus obtains high-quality interfacial characteristics.Such as, Hyoung-Sub Kim etc. have reported at HfO
2/ InP interface is the interface passivation layer (IPL) of an insertion Ge, and obtain good C-V characteristic, frequency dispersion is less, and obtains the equivalent capacity thickness (CET) of 1.4nm.Noriyuki Taoka etc. has reported with (NH
4)
2s solution passivation InP surface, can reduce boundary defect (interface traps) and the slow defect (slow traps) of interface, obtain the interface of good quality.F.Gao etc. have reported and have used N
2plasma directly processes GaAs surface, can suppress the formation of the oxide of As, significantly improves the C-V characteristic of GaAs mos capacitance.Takuya Hoshii etc. has reported and has used N
2plasma directly processes InGaAs surface, one deck nitrogen oxide can be formed on surface, due to As-N key in nitrogen oxide and In-N key instability, therefore oxynitride layer mainly Ga-N key, significantly reduce boundary defect (interface traps) and slow defect (slow traps), obtain lower than 3 × 10
11cm
-2.ev
-1interface state density.About N
2this method that plasma directly processes semiconductor surface also had relevant report on InP material, and e.g., the people such as A.Talbi have reported at InP surface directly N
2plasma treatment, can form In-N key and P-N key (Materials Science and Engineering A, 2006,437 (2006): 254-258) on surface.The people such as T.Haimoto have reported and have adopted ECR (electron cyclotron resonace) plasma generator to produce N after with acetone and ammoniacal liquor cleaning
2plasma directly processes InP surface, then electron beam evaporation gate medium SiO
2with thermal evaporation grid metal A l, result shows form one deck nitrogen oxide on InP surface, reduce the slow defect in the natural oxide of InP surface, obtain C-V hysteresis (relevant with boundary defect) (the AppliedPhysics Letters being less than 10mv, 2010,96 (1): 012107-1-012107-3).But, all after first carrying out plasma treatment in other plasma generator in prior art, again sample is transferred in atomic layer deposition system and carry out gate medium deposition, and sample exposure can form the natural oxide affecting interfacial characteristics in atmosphere in the process of transfer, also greatly can increase the probability that substrate surface is polluted simultaneously, cause the interface defect density (Dit) of final gained sample and boundary defect density (Δ Nbt) all to have increase to a certain degree.
Summary of the invention
The technical problem to be solved in the present invention is to provide one and improves Al
2o
3the interface passivation method of/InP mos capacitance interfacial characteristics and leakage current characteristic.Adopt the method can effectively passivation boundary defect and Al
2o
3the boundary defect at/InP interface, can also reduce gate leak current, thus reaches raising Al
2o
3the object of/InP mos capacitance electric property.
Of the present inventionly improve Al
2o
3the interface passivation method of/InP mos capacitance interfacial characteristics and leakage current characteristic, comprises and carries out N to substrate surface
2plasma treatment step and gate medium deposition step, describedly carry out N to substrate
2plasma treatment step and gate medium deposition step all carry out in TFS 200 atomic layer deposition system, wherein:
N is carried out to substrate surface
2plasma treatment step is cavity substrate being placed in TFS 200 atomic layer deposition system, and the plasma generator utilizing TFS 200 atomic layer deposition system to carry produces N
2plasma carries out N to substrate surface
2plasma treatment;
Gate medium deposition step is by N
2substrate after plasma treatment deposits gate medium in position.
In technical scheme of the present invention, described TFS 200 atomic layer deposition system is Beneq Corp. of Finland (Beneq) TFS 200 atomic layer deposition system.The present invention adopts InP substrate.
The present invention adopts TFS 200 atomic layer deposition system carrying plasma generator to carry out N to substrate
2plasma treatment and gate medium deposition, at N
2do not need moving substrate to make it on original position, directly carry out gate medium deposition after plasma treatment, avoid substrate because of transfer contaminated and again be oxidized may, thus can more effectively passivation boundary defect and Al
2o
3the boundary defect at/InP interface; In addition, adopt the method for the invention effectively can also reduce gate leak current, improve interface and mass of medium, significantly improve Al
2o
3the electric property of/InP mos capacitance.
In technique scheme, N is being carried out to substrate surface
2in plasma treatment step, N
2the condition of plasma treatment is preferably: the N producing plasma
2flow is 200 ~ 400sccm, uses N
2as carrier gas, carrier gas flux is 30 ~ 100sccm, and radio-frequency power is 50 ~ 100W, and nitridation time is 5 ~ 10min, and the temperature in cavity is 180 ~ 250 DEG C.Be more preferably: the N producing plasma
2flow is 300 ~ 400sccm, uses N
2as carrier gas, carrier gas flux is 50 ~ 100sccm, and radio-frequency power is 80 ~ 100W, and nitridation time is 8 ~ 10min, and the temperature in cavity is 180 ~ 220 DEG C.
In technique scheme, in gate medium deposition step, described gate medium is Al
2o
3, preferably controlling growth temperature is 180 ~ 250 DEG C, and growth thickness is 3 ~ 10nm; Being more preferably and controlling growth temperature is 180 ~ 220 DEG C, and growth thickness is 3 ~ 5nm.
Interface passivation method of the present invention, except comprising above-mentioned steps, is carrying out N to substrate surface
2before plasma treatment step, also comprise the step that substrate is cleaned; After gate medium deposition step, also comprise the step of evaporation grid metal.Further, after evaporation grid metal step, conventional photoetching, development and annealing steps is also comprised to prepare mos capacitance.Wherein:
Described comprises organic cleaning step and inorganic cleaning step to the step that substrate cleans.Wherein, carrying out organic washing to remove the organic pollution of substrate surface to substrate slice surface, can be specifically use each soaking and washing 3 ~ 5min of acetone, ethanol successively, then clean with deionized water rinsing, then uses dry N
2dry up.Carrying out inorganic cleaning to remove the natural oxide of substrate surface to substrate slice surface, can be specifically pickling and alkali cleaning.Wherein pickling is the hydrochloric acid solution soaking and washing 1 ~ 2min of employing 5 ~ 10% (w/w), then clean with deionized water rinsing, uses dry N
2dry up.Alkali cleaning is the ammonia spirit soaking and washing 3 ~ 5min with 15 ~ 25% (w/w), then clean with deionized water rinsing, uses dry N
2dry up.
In described evaporation grid metal step, described grid metal is Al, and equipment and the operation of this employing are same as the prior art.Preferably, grid metal thickness is 100 ~ 200nm, and evaporation of metal adopts EVA450 electron beam evaporation platform (French Alliance).
Described photoetching, development and annealing steps are same as the prior art.Preferably, photoresist adopts 9920 positive glue, and glue evenning table rotating speed is 3500 ~ 4000r/min, and the time is 60 ~ 70sec, and photoetching preferably adopts SUSSMA6/BA6 double face photoetching machine, and the time for exposure is 15 ~ 18sec.Development adopts developer for positive photoresist, and developing time is 8 ~ 10min.Annealing preferably adopts AG610 annealing furnace, at N
2anneal under condition, annealing temperature is 250 ~ 350 DEG C, and annealing time is 30 ~ 60sec.
Compared with prior art, the plasma generator that the present invention is carried by use TFS 200 atomic layer deposition system produces N
2plasma processes InP surface, and then makes substrate in situ go up depositing Al
2o
3after effectively avoiding completing plasma treatment in prior art in other plasma generator, sample is transferred in atomic layer deposition system again and carry out substrate surface that gate medium deposition brings and be again oxidized and pollution to substrate surface, thus can more effectively passivation boundary defect and Al
2o
3the boundary defect at/InP interface; In addition, adopt the method for the invention effectively can also reduce gate leak current, improve interface and mass of medium, significantly improve Al
2o
3the electric property of/InP mos capacitance.
Accompanying drawing explanation
Fig. 1 is the process chart of the embodiment of the present invention 1;
Fig. 2 is multifrequency (1KHz ~ 1MHz) capacitance-voltage (C-V) curve and high frequency (1MHz) hysteresis loop of the embodiment of the present invention 1 gained sample;
Fig. 3 is multifrequency (1KHz ~ 1MHz) capacitance-voltage (C-V) curve and high frequency (1MHz) hysteresis loop of comparative example gained sample;
Fig. 4 is the energy profile of the interface defect density Dit of the embodiment of the present invention 1 gained sample and comparative example gained sample, wherein ▲ represent embodiment 1 gained sample,
represent comparative example gained sample;
Fig. 5 is the distribution map of the boundary defect density Δ Nbt of the embodiment of the present invention 1 gained sample and comparative example gained sample, wherein
represent embodiment 1 gained sample,
represent comparative example gained sample;
Fig. 6 is the gate leak current curve of the embodiment of the present invention 1 gained sample and comparative example gained sample, and wherein represents embodiment 1 gained sample, and ■ represents comparative example gained sample.
Embodiment
Below in conjunction with specific embodiment, the present invention is described in further detail, and to understand content of the present invention better, but the present invention is not limited to following examples.
Embodiment 1
1) organic washing is carried out to InP substrate surface, first use acetone soaking and washing 5min, then clean with deionized water rinsing, use dry N
2dry up; Clean 5min by alcohol immersion again, taking-up is clean with deionized water rinsing, uses dry N
2dry up, to remove the organic pollution of substrate surface.
2) inorganic cleaning is carried out to substrate surface, first use the hydrochloric acid solution soaking and washing 1min of 10% (w/w), then clean with deionized water rinsing, use dry N
2dry up; Use the ammonia spirit soaking and washing 5min of 25% (w/w) again, then clean with deionized water rinsing, use dry N
2dry up, to remove the natural oxide of substrate surface.
3) by substrate-transfer in TFS 200 atomic layer deposition system (Beneq company) cavity, the plasma generator that utilizes it to carry produces N
2plasma carries out N to substrate surface
2plasma treatment; N
2the condition of plasma treatment is: the N producing plasma
2flow is 400sccm, uses N
2as carrier gas, carrier gas flux is 100sccm, and radio-frequency power is 100W, and nitridation time is 10min, and cavity temperature is 200 DEG C.
4) carry out gate medium deposition at the cavity situ of TFS 200 atomic layer deposition system, wherein gate medium is Al
2o
3, the growth temperature of gate medium is 200 DEG C, and growth thickness is 3nm.
5) substrate completing gate medium deposition is placed in EVA450 electron beam evaporation platform (French Alliance) and evaporates grid metal, wherein grid metal is Al, and its evaporation thickness is 200nm.
6) technique completes the techniques such as follow-up photoetching, development, annealing to prepare mos capacitance routinely, and particularly, photoresist adopts 9920 positive glue, and glue evenning table rotating speed is 4000r/min, and the time is 60sec; Photoetching adopts SUSS MA6/BA6 double face photoetching machine, and the time for exposure is 18sec; Development adopts developer for positive photoresist, developing time is that (this developing time comprises the etching time of Al to 10min, because the Main Ingredients and Appearance Tetramethylammonium hydroxide (TMAH) in developer for positive photoresist has strong basicity, to Al, there is corrosiveness, and unexposed photoresist is not affected, in developing process, therefore directly can complete the etching process of Al); Annealing adopts AG610 annealing furnace, at N
2anneal under condition, annealing temperature is 350 DEG C, and annealing time is 30sec.The process chart of the present embodiment as shown in Figure 1.
Comparative example
Repeat embodiment 1, as different from Example 1, the substrate in this comparative example does not carry out N at TFS 200 atomic layer deposition system cavity
2plasma treatment (namely not carrying out the step 3 in embodiment 1)).
The sample (being called for short sample 1) of embodiment 1 gained and the sample (being called for short sample 2) of comparative example gained are carried out to the test of multifrequency (1KHz ~ 1MHz) capacitance-voltage (C-V) characteristic and high frequency (1MHz) hysteretic characteristic, wherein as shown in Figure 2, multifrequency (1KHz ~ 1MHz) capacitance-voltage (C-V) curve of sample 2 and high frequency (1MHz) hysteresis loop are as shown in Figure 3 for multifrequency (1KHz ~ 1MHz) capacitance-voltage (C-V) curve of sample 1 and high frequency (1MHz) hysteresis loop.Compare in Fig. 3 without N
2the curve of the sample 2 of plasma passivation process, through N
2the sample 1 accumulation area frequency dispersion of plasma passivation process and hysteresis have had great reduction, and accumulation area frequency dispersion is reduced to 3.5% by 7.8%, and hysteresis is decreased to 60mv by 130mv.
By calculating, wherein interface defect density is by 5 × 10
12/ cm
2eV is reduced to 2 × 10
12/ cm
2eV, as shown in Figure 4; Boundary defect density is by 9 × 10
11v
-1cm
-2be reduced to 5.85 × 10
11v
-1cm
-2, as shown in Figure 5; Gate leak current is by 9 × 10
-5a/cm
2be reduced to 2.5 × 10
-7a/cm
2(in order to the fairness compared, compare the gate leak current that flat band voltage adds 1V voltage place, wherein the flat band voltage of sample 1 is 0V, and the flat band voltage of sample 2 is 0.5V), as shown in Figure 6.
As can be seen here, utilize the present invention can effectively passivation boundary defect and Al
2o
3the boundary defect at/InP interface, suppresses the formation of InP surface natural oxide, reduces gate leak current, improve interface and mass of medium, significantly improve Al
2o
3the electric property of/InP mos capacitance.
Embodiment 2
Repeat embodiment 1, unlike: step 3) and step 4) undertaken by following restriction:
3) by substrate-transfer in TFS 200 atomic layer deposition system (Beneq company) cavity, the plasma generator that utilizes it to carry produces N
2plasma carries out N to substrate surface
2plasma treatment; N
2the condition of plasma treatment is: the N producing plasma
2flow is 300sccm, uses N
2as carrier gas, carrier gas flux is 30sccm, and radio-frequency power is 50W, and nitridation time is 8min, and cavity temperature is 250 DEG C.
4) carry out gate medium deposition at the cavity situ of TFS 200 atomic layer deposition system, wherein gate medium is Al
2o
3, the growth temperature of gate medium is 250 DEG C, and growth thickness is 10nm.
Embodiment 3
Repeat embodiment 1, unlike: step 3) and step 4) undertaken by following restriction:
3) by substrate-transfer in TFS 200 atomic layer deposition system (Beneq company) cavity, the plasma generator that utilizes it to carry produces N
2plasma carries out N to substrate surface
2plasma treatment; N
2the condition of plasma treatment is: the N producing plasma
2flow is 200sccm, uses N
2as carrier gas, carrier gas flux is 50sccm, and radio-frequency power is 75W, and nitridation time is 5min, and cavity temperature is 220 DEG C.
4) carry out gate medium deposition at the cavity situ of TFS 200 atomic layer deposition system, wherein gate medium is Al
2o
3, the growth temperature of gate medium is 220 DEG C, and growth thickness is 5nm.
Embodiment 4
Repeat embodiment 1, unlike: step 3) and step 4) undertaken by following restriction:
3) by substrate-transfer in TFS 200 atomic layer deposition system (Beneq company) cavity, the plasma generator that utilizes it to carry produces N
2plasma carries out N to substrate surface
2plasma treatment; N
2the condition of plasma treatment is: the N producing plasma
2flow is 350sccm, uses N
2as carrier gas, carrier gas flux is 80sccm, and radio-frequency power is 80W, and nitridation time is 6min, and cavity temperature is 200 DEG C.
4) carry out gate medium deposition at the cavity situ of TFS 200 atomic layer deposition system, wherein gate medium is Al
2o
3, the growth temperature of gate medium is 200 DEG C, and growth thickness is 4nm.
Claims (7)
1. one kind is improved Al
2o
3the interface passivation method of/InP mos capacitance interfacial characteristics and leakage current characteristic, comprises and carries out N to substrate surface
2plasma treatment step and gate medium deposition step, is characterized in that: describedly carry out N to substrate
2plasma treatment step and gate medium deposition step all carry out in TFS200 atomic layer deposition system, wherein:
N is carried out to substrate surface
2plasma treatment step is cavity substrate being placed in TFS 200 atomic layer deposition system, and the plasma generator utilizing TFS 200 atomic layer deposition system to carry produces N
2plasma carries out N to substrate surface
2plasma treatment;
Gate medium deposition step is by N
2substrate after plasma treatment deposits gate medium in position.
2. interface passivation method according to claim 1, is characterized in that: carrying out N to substrate surface
2in plasma treatment step, N
2the condition of plasma treatment is: the N producing plasma
2flow is 200 ~ 400sccm, uses N
2as carrier gas, carrier gas flux is 30 ~ 100sccm, and radio-frequency power is 50 ~ 100W, and nitridation time is 5 ~ 10min, and the temperature in cavity is 180 ~ 250 DEG C.
3. interface passivation method according to claim 1, is characterized in that: in gate medium deposition step, and described gate medium is Al
2o
3.
4. interface passivation method according to claim 1, is characterized in that: in gate medium deposition step, and controlling growth temperature is 180 ~ 250 DEG C, and growth thickness is 3 ~ 10nm.
5. the interface passivation method according to any one of Claims 1 to 4, is characterized in that: carrying out N to substrate surface
2before plasma treatment step, also comprise the step that substrate is cleaned.
6. interface passivation method according to claim 5, is characterized in that: described step of cleaning substrate comprises organic cleaning step and inorganic cleaning step.
7. the interface passivation method according to any one of Claims 1 to 4, is characterized in that: after gate medium deposition step, also comprises the step of evaporation grid metal.
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|---|---|---|---|
| CN201510393302.4A CN104966673A (en) | 2015-07-07 | 2015-07-07 | Interface passivation method for improving the interface characteristic and electric leakage characteristic of AI203/InP MOS capacitor |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298780A (en) * | 2016-09-27 | 2017-01-04 | 中国科学院微电子研究所 | InP substrate MOSCAP structure and preparation method thereof |
| CN108666216A (en) * | 2018-05-15 | 2018-10-16 | 西安电子科技大学 | HEMT device and preparation method thereof based on overlayer passivation structure |
| CN111697113A (en) * | 2020-06-15 | 2020-09-22 | 南方科技大学 | Preparation method of Micro-LED device and Micro-LED device |
-
2015
- 2015-07-07 CN CN201510393302.4A patent/CN104966673A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298780A (en) * | 2016-09-27 | 2017-01-04 | 中国科学院微电子研究所 | InP substrate MOSCAP structure and preparation method thereof |
| CN108666216A (en) * | 2018-05-15 | 2018-10-16 | 西安电子科技大学 | HEMT device and preparation method thereof based on overlayer passivation structure |
| CN108666216B (en) * | 2018-05-15 | 2021-05-07 | 西安电子科技大学 | HEMT device based on laminated passivation structure and preparation method thereof |
| CN111697113A (en) * | 2020-06-15 | 2020-09-22 | 南方科技大学 | Preparation method of Micro-LED device and Micro-LED device |
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