CN1049580A

CN1049580A - improved digital signal data and forward error control coding technology

Info

Publication number: CN1049580A
Application number: CN90104810A
Authority: CN
Inventors: 唐纳德·H·麦克马汉; 阿伦·J·柯比; 布鲁斯·A·斯科菲尔德; 肯特·斯普林杰
Original assignee: Digital Equipment Corp
Current assignee: Digital Equipment Corp
Priority date: 1989-07-17
Filing date: 1990-07-17
Publication date: 1991-02-27
Anticipated expiration: 2005-07-17
Also published as: AU5870890A; ATE163823T1; AU1092892A; AU618680B2; EP0414368A3; CN1020364C; DE69032076T2; JPH03171826A; CA2021072A1; EP0414368B1; IE902591A1; KR910003957A; DE69032076D1; EP0414368A2

Abstract

With a plurality of digital signal bit sequences coding or have an encoder of data code word of the accumulative total direct current offset of maximum string length that improved signal characteristic promptly limits and qualification.Then, this encoder is encoded to the data code word with forward error control (" FEC ") code, so that constitute the FEC code block by a plurality of data code words.Preferably construct the FEC code block, then general-FEC position and complement code thereof and each data code word and put so that FEC position and benefit participation thereof are inserted between each successive generations code word by producing verification or the FEC position that data code word in its number and the piece equates.In addition, can be with complementary FEC to being used for receiver so that before decoding, obtain the FEC code block of suitable framing.

Description

Improved digital signal data and forward error control coding technology

The present invention relates to digital communication system, more precisely, the present invention relates to help accurately to receive the improved coding techniques of transmission of digital signals.

Usually the digital communication signal that sends by the communication channel such as coaxial cable or optical fiber link is encoded, even so that because the noise in the communication channel and when occurring possible signal errors during the transmission, also receiving accurately at terminal point.According to application requirements, can adopt to be used to improve the digital coding of code characteristic or the coding that employing prevents mistake.

Digital coding needs the bit stream translation of information or data-signal or is transformed into " code word ", and this code word has the maximum string length of restriction, the characteristic features such as direct current offset that add up of restriction, and helps other signal characteristic of receiving.Specifically, digital coding is made up of the process that the data word (or N position block) with the N position is transformed to M position code word (or M position block), and wherein M is greater than N.Used " expense " of encoding scheme is M-N, and its available percentage 100 * (M-N)/N% expresses.The efficient of encoding scheme is N/M.For the bit pattern of data is transformed to the bit pattern that can receive more reliably when noise appears in communication path, encoding scheme was added to extra " expense " position on the data before sending data.Add up direct current offset or both that signal behind the coding may, for example have the fixed string length of restriction, a qualification have concurrently.

The encoding scheme that the N bit data word is transformed to M position code word often is called the Nb/Mb encoding scheme.For example, the 8b/10b encoding scheme is transformed to 10 code words with 8 bit data word.This scheme has 2 or 25% expense, and has 80% efficient.

Some encoding scheme can be encoded to two types code word, promptly to data word and command word coding.Do like this owing to a kind of like this fact produces, can be with the Nb/Mb encoding scheme as 2 ^NPlant the set and 2 of possible data word ^MOnly use wherein 2 in the possible code word ^NMan-to-man map between the subclass of different code word.These are remaining 2 years old ^M-2 ^NCode word no longer is used.Yet, in some coding, 2 ^M-2 ^NSub-fraction in the individual code word has and represents 2 of data ^NThe transmission feature that meets the requirements (for example, string length and accumulative total direct current offset) that individual code word is same.This sub-fraction can be used to represent the another kind of code word that is called command word.For encoding scheme, preferably allow a large amount of command words with the transmission characteristic that meets the requirements equally with coded data word is encoded.

To the restriction of the maximum string length of data code word, for example carrying out in the clock recovery during the decoding of destination is of great use.Maximum string length is exactly to have the maximum number that identical numerical value is the phase ortho position of logical zero or logical one.Limit maximum string length, in order to reduce to have the bit string length of same numerical value, this is crucial for finish accurate clock recovery in the destination, because clock recovery circuitry detects basic data clock frequency according to the transition between logical one and 0 data value.The free of data transition if pass through a lot of bit intervals, clock recovery circuitry will lose usually synchronously so.So the encoding scheme that selection has low maximum string length is desirable.

The accumulative total direct current offset also can be described as direct current disequilibrium or the numeral and the deviation of accumulative total, is often expressed as the number that bit sequence obtains the position of required its value of change of balance.For example, if there is one to be necessary for logical one and to make this sequence balance, but the value of this position is a logical zero, and adding up direct current offset so is a position.The another kind statement is to the position weighting-1 of each logical zero, to weighting+1, position of each logical one, then the power of all in the serial flow to be sued for peace, with resulting single counting as the accumulative total direct current offset.Explain like this, go up the position of 2 extra in routine sequence logical zeros, can obtain the accumulative total direct current offset is-2.With its accumulative total direct current offset is that 0 bit sequence is called " balance ", and with its accumulative total direct current offset be 1 or the bit sequence of more position be called " imbalance ".

The bit stream that sends to the destination is made up of the sequence of logical zero and logical one numerical value.The acceptor circuit of destination receives two kinds of two kinds of logical values such as the polarity opposite voltage usually, and the signal voltage of acceptor circuit has and the proportional component of voltage near direct current (that is low frequency) of bit stream accumulative total direct current offset.Since acceptor circuit only be applicable to qualification direct voltage swing and can not transship, therefore,, preferably adopt the code of the accumulative total direct current offset of restricted code data for avoiding receiver overload.

In addition, preferably adopt a kind of encoding scheme of property performance period dc balance, the ending place accumulative total direct current offset that described periodicity dc balance is defined as in each K hyte is 0 just, and wherein K is the number of fixing position.(for example, K can be one or two times of length M of coded word or block).Has periodically dc balance as encoding scheme, then its bit stream just spectrum component has been limited to the proportional preset frequency of 1/K under, thereby all spectrum components that this encoding scheme allows acceptor circuit to adopt high pass filter to stop is lower than this frequency improve the signal to noise ratio of receivers.

Propose many kinds of digital coding and be used for commercial digital communication system to some extent.For example, known Manchester (Manchester) code realizes that its maximum string length is 2 easily, and is the cycle dc balance with 2.Yet 100% coding expense of this code it has been generally acknowledged that and goes a bit too far.Another kind of known code, Sperry 4b/5b code, its maximum string length is 4,25% coding expense only, but its accumulative total direct current offset unrestrictedly increases in time.

Other has a kind of known codes is IBM 8b/10b code, is being published in " IBM J.Res.Develop. " Vol.27, and No.5 is entitled as on September nineteen eighty-three number in the paper of " 8b-10b transmission code dc balance, the subregion block " and describes this code.IBM 8b/10b code can be decomposed into 3b/4b and 5b/6b coding.The maximum string length of this code is 5, and it is quite easy to realize with hardware, also have 25% coding expense, and the accumulative total direct current offset in the bit stream is restricted to ± 3, and will add up direct current offset to the end of any 10 code words and be restricted to+/-1.But, for many application, the command code word that IBM 8b/10b code is allowed very little, and its maximum string length is 5 also excessive.In addition, it is defined and is failed the accumulative total direct current offset of cyclical equilibrium and can be brought difficulty when receiver filtering.

As mentioned above, can utilize coding to be provided for sending the error detection occurs and the error correction mechanism of signal selectively.The error correction coding is represented with its initial letter " ECC " usually.The general approach of using ECC that the mistake in the signal of communication that receives is detected and corrects is forward error control, is commonly referred to as " FEC " with its initial combination.In forward error control; the word of each transmission; block or frame comprise preamble bit and (are sometimes referred to as " ECC ", " redundancy "; " protection " or " verification " symbol), use these symbols, receiver can detect mistake; and; in some FEC scheme, can find bit-error locations, promptly detect or locate the mistake that exists in the received signal bit stream.Lend bit position if identify,, for example, change logical one into logical zero just can simply the error bit negate that identifies should be finished correction, perhaps opposite.In this way, can obtain to send duplicating accurately of signal and need not to transmit again.

Using the FEC code to produce redundant symbol, to carry out the optimised form of error protection coding be not only as linear code but also be systematic code.In linear code, any two encoded radios arbitrarily and can produce another encoded radio.In systematic code, each code word comprises and the identical part of coded data not.So the FEC code of generation is by coded data is not formed with combining of the redundant symbol that is produced by the FEC sign indicating number.

An example of this FEC sign indicating number is that Hamming (Hamming) distance (being the minimum number of the different positions of any two valid code blocks) is 4 Hsiao code.Use this invention distance, this FEC code can be corrected the single mistake in the transmission bit sequence and detect double bit error.This code needs 8 FEC redundant digits to come to add up to 64 to 127 position in the protected data input, and 7 redundant digits can be protected 32 to 65, can protect the 16-31 position for 6, can protect 8 to 15 for 5.

Existing FEC encoding scheme is only considered the problem of error detection occurs/correction usually and is not planned to improve the transmission characteristic of data (for example, string length and accumulative total direct current offset) as discussed earlier.Thereby, there are needs to the improved encoding scheme that error detection occurs or correction and improved string length and accumulative total direct current offset characteristic can be provided simultaneously.

According to one aspect of the present invention; input value is carried out digital coding (for example to improve characteristics of signals; the maximum string length that limits and the accumulative total direct current offset of qualification) thus form " data code word "; then; plurality of data code word (stack up is called block) is carried out the error protection coding; preferably use forward error control (" FEC ") code of conventional linearity and system, to produce the FEC code block.Preferably, form the FEC code block by producing some check digit, perhaps data code word number equates in FEC code bit and this piece, then with a FEC position and the complement of two's two's complement and each data code word and put, makes a FEC position and complement code thereof be inserted between each continuous code word.

An advantage of the invention is, allow in error detection occurs/correction, string length and accumulative total direct current offset are limited.Because each FEC position and its quilt sign indicating number occur in pairs, any accumulative total direct current offset of himself can not introduced in this FEC position, and the feasible FEC code block that produces has the accumulative total direct current offset that is limited equally with the data code word.Preferably, use a kind of by the defined on the other hand data coding scheme of the present invention, this encoding scheme can reach 0 or 1 accumulative total direct current offset in ending place of each code word, therefore, also has 0 or be not more than 1 accumulative total direct current offset according to FEC encoding block of the present invention.

And, FEC position and its complement code placed between each continuous code word by any continuous bit string that prevents from the to have identical value place, end that surpasses a code word of extending enter the place that begins of code word of future generation, help to realize the qualification of the string length of bit stream.For example, if be scheduled to a kind of encoding scheme is used for preventing that appearance is more than the string of 3 continuous positions in the code word, concerning a code word, still might end at so 3 logical ones the position and code word of future generation start from 3 logical ones the position, just produced 6 continuous logical ones the position the combination string.The present invention overcomes this problem by the position of inserting a pair of complementation between two code words, and the string length of generation only is 4 rather than 6.

According to another aspect of the present invention, if string comprises first or last position of code word, then limiting string length is 3, and the string length in the code word is defined as 4, and the present invention can be more advantageously be used in combination with 10 or 20 s' data coding scheme so.When FEC encoding scheme of the present invention combines with 10 codes of the present invention or 20 codes of the present invention, its maximum string length of FEC coded word block code that is produced is 4, and the largest cumulative direct current offset is 1.

For example, in a most preferred embodiment, available 8 10 bit data code words (forming), 8 FEC positions by the 8b/10b data encoder and with 8 FEC code blocks that form 96 of this FEC position complementation.Can use the conventional FEC algorithm of all FEC of Hsiao as previously mentioned schemes, derive 8 FEC positions from 80 data bit (8 10 bit data word).These FEC positions are arranged between every pair of data code word, and FEC complementary pair (that is 1 bit complement of 1 FEC symbol and it) is placed after the last data code word.96 whole piece can be protected in these 8 FEC positions.Like this, use this encoding scheme, the expense that relates to the error protection coding is 25%, (identical with 8b/10b digital coding expense).Another advantage of 96 block encoding schemes be it be applicable to a plurality of 8 or 16 bit data code words and with existing hardware and program compatibility towards 8.

In another most preferred embodiment, it is right that each 16 input data values is encoded to 20 bit data code words, and this 20 bit data code word is to being made of 9 code words and 11 code words.Best 16b/20b encoding scheme is defined as 4 and reach dc balance in each 20 ending place that code word is right with string length.(best hardware implements to comprise precoder and each 8b/9b and the 10b/11b sub-encoders that 16b/20b encodes carried out in stack up) produces 8 FEC from 4 20 code words to 80 pieces forming then.A FEC position and the complement of two's two's complement (as prefix or suffix) thereof are juxtaposed on each 9 and the 11 bit data code words, and form 96 FEC pieces.

When execution is used for producing 9-, the 10-of FEC version noted earlier or 11 bit data code words, preferably by selecting 3/4/3 maximum string length code word in the look-up table that is stored in the memory or producing with logic device.Concerning each bit string or bit sequence of last (" end string length ") of first (" beginning string length ") comprising code word or code word, the string length of these code words is not more than 3, and to each intermediate sequence (promptly, do not comprise first and the string of last position), the string length of these code words is not more than 4.

By selecting 3/4/3 such code word, and with the FEC mutual-complementing code to placing side by side between the data code word, can be with internal code word string length, yes, and the maximum string length of internal code word is defined as 4.The reason of restricted internal code word is, finish single FEC position (if the identical logical values that string length 3 adds the back, just as the stop bits of this code word), producing the longest strings that are made of the close position of 4 values, is that same processing can be done in 3 initial string and the FEC position that is inverted formerly to length.If be inserted in the FEC complementary pair does not have between the data code word, so, internal code word string length is 3+3=6.Like this, by using interpolation FEC right, can obtain the short maximum string length of digital signal bit stream.

And, can be by to the suitable selection of data code word with and put the accumulative total direct current offset minimum that makes crossfire.For example, when 8b/10b encodes, with each input value be encoded to have accumulative total direct current offset be 0(promptly, the balanced code word) or for 1(be uneven code word) the data code word.Then, when another input value is encoded to next uneven code word, select its disequilibrium to compensate the imbalance of last uneven code word.In other words, select the data code word and average out, that is, within the bounds of possibility, select the data code word to make it to match mutually with association code word with opposite accumulative total direct current offset.Therefore, just can make this FEC code block balance, and, 1 the minimum accumulative total direct current offset of possibility can be arranged just whenever containing odd number unbalanced data code word whenever containing even number unbalanced data code word.So the accumulative total direct current offset of any code word ending place is not more than 1.

Similarly, in above-mentioned 16b/20b encoding scheme, has the opposite accumulative total direct current offset that cancels each other out from paired 9 and 11 s' of encoder section.Therefore, contain many FEC pieces and obtain dc balance this class section.

According to another aspect of the present invention, receiver uses complementary FEC position to obtaining the suitable frame indication of FEC code block between decoding.In the signal that the framer circuit inspection receives everybody and by detect the FEC complement code to the data code word in the mistake and the frame boundaries that slides come the identification block border until mistake is minimum.Then, the FEC code block is deciphered, at first whole FEC code block execution FEC is deciphered and recover FEC position, their complement code and data code word, detected mistake in the data code of correcting a mistake the then word is carried out data decoding at last and is recovered essential information.

Obviously, the above-mentioned technology that is used for producing the data code word of the accumulative total direct current offset with qualification can be used for the application scenario without the error protection coding.For example, 2/4/2 code can be used in conjunction with present technique, be 4 and the accumulative total direct current offset that limits with the maximum string length that obtains the digital signal bit stream.Another selection is, pseudo-complementary pair can be placed code between.

The present invention comprises various above mentioned new coding techniquess, and the technology of other embodiment illustrated that will propose hereinafter, and claims are pointed out in the scope of the present invention.

For understanding essence of the present invention and purpose more comprehensively, should consult the detailed description of following illustrative embodiment in conjunction with the accompanying drawings, in the accompanying drawing:

Fig. 1 comprises the block diagram that comprises the coding circuit of 16b/20b data encoder and FEC encoder according to the first embodiment of the present invention;

Fig. 2 is the block diagram single, direct 8b/10b data encoder according to second embodiment of the invention;

Fig. 3 is the block diagram according to the direct 8b/10b data encoder of another embodiment of the present invention;

Fig. 4 be according to third embodiment of the invention to counting the circuit block diagram that code word is carried out parallel encoding based on a plurality of 8 systems;

Fig. 5 is according to the fourth embodiment of the present invention, uses the block diagram towards the 16b/20b coding circuit of 16 words of 8b/9b and 10b/11b sub-encoders;

Fig. 6 according to the fifth embodiment of the present invention, use 8b/9b and 10b/11b sub-encoders, be used for the 16b/20b coding circuit of 8 carry system code words;

Fig. 7 is to use the block diagram of the communication system of Fig. 6 coding circuit;

Fig. 8 is the framing of Fig. 7 and the block diagram of data recovery circuit.

1. data and FEC coding circuit

Fig. 1 shows and is used for 2 32 DATA(data) signal carries out the circuit diagram that data and FEC are encoded to 96 FEC code blocks.Each DATA signal comprises 2 16 section DATA0, DATA1, each segment table example such as data or command information, and with 22 CMD(order) one of signal CMD0, CMD1 be associated.Each cmd signal has a numerical value, and this numerical value can be used for discerning this dependent segment, and whether to comprise command information promptly be command signal, or comprise data message, that is, be data-signal.

With each section DATA0, DATA1 and its cmd signal that is associated together, be added to 16b/20b data encoder 14a, 16b.This data encoder 14a, 14b are converted to corresponding 20 data code word with section DATA0, DATA1, are stored in then among corresponding registers 16a, the 16b.Then, two 20 bit data code words that are stored among register 16a, the 16b are supplied with 1: 2 demultiplexer 18, with described 20 bit data code words with preceding or 2 that are afterwards produced by data encoder 14a, 14b other 20 data code word mutually and put.

Then 4 20 data code word is added to register 20 as one 80 piece.Preferably, each data code self is a dc balance in this piece of 80.If these 80 pieces comprise and fail the data code word of dc balance, so, its data code word within the possible range, the compensation disequilibrium makes 80 whole blocks have minimum accumulative total direct current offset or reaches dc balance.Its realization technology is described below.

Then 80 data code word is added to FEC symbol generator 22 and register 24.This FEC symbol generator 22 produces one 8 FEC symbol according to this data code word, promptly is used for the ECC symbol of forward error control.These FEC positions promptly are added to 8 inverters 26 directly are added to register 24 again.The place value negate of 26 pairs of FEC symbols of inverter, thus anti-phase or complementary FEC position produced, and FEC symbol and complement code thereof are delivered to register 24.

Register 24 is with interlace mode and put the FEC position of data code word, FEC position and negate.Specifically, meet in 8 FEC positions and its paratope one after each of 8 20 bit data code words.In other words, Hu Bu FEC is in the FEC code block that is dispersed in coded data.This has not only limited the string length of internal code word effectively, and dc balance complementary FEC right, and therefore do not change the accumulative total direct current offset of 80 pieces.

96 FEC code blocks are added to 6: 1 multiplexers 26 to produce 16 DATA-OUTPUT(data output) and be stored in the register 28, prepare to carry out the transmission of 16 Bits Serial.

Although the DATA that coding circuit 10 usefulness 2 parallel 16b/20b data encoder 14a, 14b handle 16 input, yet, also can replace 2 parallel 16b/20b data encoders by suitably revising 4 parallel 8b/10b encoders of circuit 10 usefulness, these are obvious to those skilled in the art.The various embodiment of 16b/20b and 8b/10b coding are discussed in more detail below.

The most preferred embodiment of each data encoder 14a, 14b uses precoding and 8b/9b and 10b/11b coding.This just produces 9 and 11 s' data code word.20B block structured 9b/11b partition helps coding and decoding, and allows to limit maximum string length and accumulative total direct current offset.By suitable selection data code word, the dc balance in each 9 and each 11 section can be defined as logical one or logical zero value, and this has just reached the disequilibrium of the possible minimum of odd length section.To having 9 and 11 section of opposite disequilibrium, can make that 20 bit sequences that are combined into are balances.Moreover, following illustrated, use 9 and the subclass of 11 bit data codes conforming to 3/4/3 maximum string length standard, maximum string length can be restricted to 4.

Use such digital coding, be preferably in when producing the FEC code block, single FEC and anti-phase FEC position are placed between 9 and 11 sections, to reduce maximum string length in couples.

This FEC code block comprises FEC position that adds up to 16 and 80 the coded data that is 4 20 seat piece forms like this.Each sub-piece is a dc balance.The 16B/20B subblock coding of module balance has been simplified total sheet design, and allows the word of the data/command bit length of use 8/5,16/14,32/30 and 64/62.

In other words, code block is to be made of 4 structural similarities, each sub-piece of 24.Each 24 seat piece comprises 20 coded data, and these 20 coded datas can further be subdivided into 9 and 11 s' section.Between each section is a FEC and its complement code.Ending place 11 sections has an additional FEC position and a complementing bits thereof.Because each 24 seat piece comprises 2 FEC positions and 4 sub-pieces are arranged, so whole just contains 8 FEC positions.Therefore, block structure is as follows:

Piece=

[24 seat piece] [24 seat piece]+

[24 seat piece] [24 seat piece]

Sub-piece=

[9 coded datas] [FEC position] [FEC position of negate]+

[11 coded datas] [FEC position] [FEC position of negate]

(top symbol "+" is represented and is put, that is, on last two adjacent lines of this page represented data actual be a continuous bit stream)

FEC symbol generator 22 preferably uses feasible single mistake can examine two wrong inventions apart from the Hsiao block encoding process that is 4.For compatible mutually with demultiplexer and other common interface with existing multiplexer, code length should be 8 multiple.Use 8 forward error control character, might protect the piece (comprising the FEC position) that contains 64 to 127.The data code word length is 80, and (that is, 20 of 4 codings words or 8 10 words) are owing to having reduced the FEC expense and increased link efficiency to have superiority.

Like this, the invention provides is used forward error correction ability of for example optical fiber transmission medium and good signal characteristic (for example, the accumulative total direct current disequilibrium or the cycle balance of Duan maximum string length and minimum).25% expense that is attributable to the data encoder part is that simple and feasible block encoding process is finished when adopting realization with 25% expense that is attributable to the FEC coded portion.

2. string length introduction

The available maximum string length characteristic that comprises the coded word separately of bit stream is determined the peak signal string length of this bit stream.The string length characteristic that available initial string length, middle maximum string length and end string length are come the analysis of encoding word.A kind of code limits its initial string length and is not more than i, and inter-burst length is not more than j, and the ending string length is not more than k, can be referred to as the maximum string length coding of i/j/k, and wherein, " i ", " j " and " K " are integer.For example, the continuous sequence of the 2/5/3/ code serial flow that can to produce its maximum string length be i+k=j=2+3=5.Equally, it is i+k=6(because to 3/4/3 code word that the continuous sequence of 3/4/3 code word will produce maximum string length, the serial flow of j＜i+k).But, as select one group of position to divide 3/4/3 code word sequence, and make its starting and ending string length be " C " (C is a positive integer), be the maximum number among " C+i ", " j " or " K+C " just can draw the maximum string length of this bit stream, concerning 3/4/3 code word, be C+i=k+C.Wherein, 3/4/3 code word is divided (for example " 1 "/" 0 " or " 0 "/" 1 " FEC position) by the position of paired complementation, C=1, and the maximum string length of generation bit stream is 1+i=k+1=4.

The code number that meets given initial/centre/end string length standard can require all code words of figure place by listing and leave out the code word that does not meet the string length standard and calculate.This process can be finished fast by computer processor, below is the table of the code number that meets various string length standards of computer generation, to do further reference.

Table 1: code word mark sheet

The string length standard satisfies string length in the codeword length code word

The code word number of the number of " 1 " position

94 or 5 2/,4/2 89

94 or 5 3/,4/3 113

94 or 5 2/,5/3 102

94 or 5 3/,6/3 116

10 5 2/4/2 180

10 5 3/4/3 228

10 4 or 6 2/,4/2 124

10 4 or 6 3/,4/3 165

11 5 or 6 2/,4/2 303

11 5 or 6 3/,4/3 391

11 5 or 6 2/,5/3 359

11 5 or 6 3/,6/3 412

3. use the 8b/10b digital coding of FEC complementary pair separator

As mentioned above, can help realizing digital coding with the 8b/10b coding.According to the present invention, a kind of new, use that complementary FEC position is that string length to each end of 10b code word is limited to coming, directly the 8b/10b coding method allows to produce 2 ⁸Individual data code and 2 ⁷Individual command code.The maximum string length of this code is 4, and the largest cumulative direct current offset is 0 or 1 in the code word, and the largest cumulative direct current offset of each code word end is 1.

Use this 8b/10b code, can not have the code balance periodically balance of each code word end (promptly) consistently; Satisfy 10 code words having only 228 balances of 3/4/3 string length standard, these code words are not enough to 256 possible 8 each in the coded data word not distributed in 10 balanced code word independently.The best result that can accomplish is that the accumulative total direct current offset with each code word end is defined as single " 1 " or " 0 " position.According to the present invention, this may be mapped on 10 codes of balance and will remain in 8 bit data word each and be mapped to the complementation of step-by-step each other and only have in 1 unbalanced two optional 10 code words one and realize by will be many as far as possible 8 bit data word of (nearly 228).As long as to 8 bit data word codings, it is mapped in unbalanced 10 code word one, this encoder is just selected one from two candidate's code words, make data word recover the accumulative total balance.

In other words, if this accumulative total disequilibrium comprises too much " 1 ", then select next uneven code word to have the disequilibrium of contrary sign, promptly too much " 0 ".This can be by selecting finishing on the contrary of second its disequilibrium of uneven code word and first.By like this selection of uneven code word being compensated the imbalance of the nearest uneven code word in front, will be not more than single " 1 " or " 0 " position at the clean accumulative total direct current offset of any code word block end place (and complete message end).So,, but still the accumulative total direct current offset can be limited within the limit of explication although bit stream can not guarantee cyclical equilibrium.

Can calculate the number of share code word that satisfies aforementioned string length and accumulative total direct current offset standard.Ading up to of 10 words of balance got 5 number of combinations at every turn in 10, promptly 10! / (5! * 5! )=252.So, represent 2 with 10 code words of balance ⁸=256 data values are impossible.And, shown in the table of Fig. 2, have only 3/4/3 code of 228 balances, and 3/4/3 code is best, be 4 bit stream because these codes can utilize complementary FEC position to producing maximum string length.Yet, also can be shown in Figure 2, also there is the code word of some additional disequilibriums with single " 1 " position (i.e. 6 " 1 " and 4 " 0 "), wherein 165 are satisfied 3/4/3 standard.Equally, have the code that " 0 " position is arranged too much of same number.So available balanced code word table shows 228 input values, and in two code words of the available uneven degree minimum of the input value of additional number (nearly 165) any represents that each in the code word is the complement code by turn of another code word.In this way, always total 228+165=393 3/4/3 code can use.In these 393 10 codes, need 256 8 bit data word of encoding wherein, and remaining 137 10 code words can be used for encoding to reaching 137 different command words (that is, 128 7 possible order of the bit words of coding are more than sufficient).Like this, use this encoding scheme, 10 code words can be represented one 8 bit data word or one 7 order of the bit word.Separate 3/4/3 code with complementary FEC, guaranteed that maximum string length is 4.

4. the illustrative embodiment of single direct 8b/10b data encoder

Fig. 2 has described single direct 8b/10b data encoder 40.This encoder 40 comprises: uneven detector 42, toggle flip-flop circuit 44 and memory 46.Encoder 40 is distinguished its corresponding 10 code words in 8 input words be that corresponding 10 code words with it of balance are unbalanced.Its corresponding 10 code words to the complementary pair that is mapped to uneven code word are unbalanced input value, and this encoder is selected a uneven code word of considering front crossfire history, and produce the code flow of a minimum disequilibrium of performance.Like this, no matter when, the logical one of code word is during more than logical zero, and the next unbalanced code word of being selected by encoder 40 will have opposite disequilibrium, and promptly logical zero is more than logical one.

Whether uneven detector 42 these codes of test balance, just, discern whether imbalance of a code word.When a code word was imbalance, uneven detector 42 just produced the UNBALANCE(imbalance of its value for logical one) signal.When this code word was balance, then the UNBALANCE signal value was a logical zero.

Uneven detector 42 has an AND gate 50, and three highest orders (MSB) of input signal are delivered to described AND gate as independently importing A5-A7.(, in uneven detector 42, not having to use the lowest order (LSB) of being appointed as A0-A6) because of following described reason.The output of AND gate 50 is added on the OR-gate 52 together as first input and other cmd signal of pointing out whether input signal comprises command information.The output of OR-gate 52 is UNBALANCE " signal.

The operation of uneven detector 42 can be understood with reference to the corresponding truth table that following table 2 provides.

The truth table of the uneven detector of table 2: Fig. 2

Input and output

CMD A7 A6 A5 UNBAL

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0

0 1 1 0 0

0 1 1 1 1

1 X X X 1

But for understanding this table, do following consideration: have as seen from Table 1 228 its maximum string length be 3/4/5 10b balanced code word (promptly, 10b code word with 5 logical ones) and exist uneven number be 1(promptly, have the code word of 4 or 6 logical ones) and 165 10b code words of 3/4/3 maximum string length.These numbers of code word are transformed to binary number, just have

228（dec）＝11100100（bin）

165（dec）＝10100101（bin）

Can handle above-mentioned several round downs and obtain 224(dec)=11100000(bin) balanced code word, and 160(dec)=10100000(bin) uneven code word, can satisfy the standard of described 3/4/3 maximum string length.Like this less than 224(11100000 ₂) the available balanced code word table of input data signal value show that and 224 to 255 input data values can be represented with uneven code word, the input command of (sum 128) can be represented with uneven code word between 256 to 383.Use this scheme, the standard of discerning uneven code word is that (A5, A6 are 1 A7) to 3 highest orders.

Now, by the essential information that has provided, just be readily appreciated that the form of Fig. 3 A.In this table, " 1 " points out logical one, and " 0 " points out logical zero, and " X " or point out logical one or logical zero.By only using three highest orders of data input signal and command signal, simplified uneven detector circuit 42.

This is by as seen, and when three incoming line A7-A5 of AND gate 50 were not " 1 " entirely, it was output as logical zero, points out that input signal values is lower than 224 and be equivalent to the balanced code word.When the incoming line of AND gate 50 all predicates " 1 ", this AND gate 50 is output as logical one, points out that input signal values is equal to or greater than 224 and be equivalent to uneven houses.When AND gate 50 is output as logical one or concludes that it is that the cmd signal value is a logical one that cmd signal is arranged, its value of OR-gate 52 generations is the UNBALANCE signal of logical one so, any situation no matter, all point out a uneven code word, on the other hand, when the arbitrary position of input signal is logical zero, OR-gate 52 produces its values and is the UNBLANCE signal of logical zero, points out that input signal values is less than 224 and do not conclude that cmd signal is arranged.This situation is equivalent to uneven houses.

The current state that toggle flip-flop circuit 44 is used for preserving the UNBALANCE signal is up to producing next uneven code word, and this circuit uses partial sum gate 44a and stores a last UNBALANCE signal such as the memory device of D flip-flop or register 44b.When code word of future generation to be sent was uneven, this trigger just made its state counter-rotating.The output of toggle flip-flop circuit 44 is added to storage on 46 so that select the suitable code balance of next uneven code.

Memory 46 is preferably realized by read-only memory (" ROM ") or programmable logic array (" PLA "), and is preferably realized the 10b/10b coding by means of the code word look-up table that uses storage.This look-up table provides 10 code words to each 10 input.These 10 inputs are made up of the UNBALANCE output of the single position of toggle flip-flop circuit 44 and command signal CMD and data bit A7-A0, CMD and A7-A0 add to storage after (in the delay device 47, for example a register bank) postpones on 46 to arrive according to the clock cycle identical with circuit 44 corresponding outputs.Memory 46 is carried out the code word specified scheme of summarizing above, to those data inputs that the uneven code word of complementation is represented by 2, UNBALANCE output according to toggle flip-flop circuit 44 is selected between two code words, so that compensate the disequilibrium of the front of coded data formerly.Finishing the required code word of this process specifies the output of using from toggle flip-flop circuit 44 so that determine the imbalance of this code word according to the imbalance of a last input.

Fig. 3 has drawn alternative encoder.Generally speaking encoder ROM 46C is identical with the ROM46 of Fig. 3 B, and difference is in and additionally in, each unit comprises the 11st, i.e. whether UNBALANCE signal constitutes the code word of a balance with the position beyond pointing out 10.This is added on the toggle flip-flop circuit 47 identical with the circuit 44 of Fig. 3 A, to produce the similar input of decoder ROM 46C.

Following table 3 explanation is stored in the look-up table among the encoder ROM 46C.

Table 3: the conversion lookup table of Fig. 3 encoder

Uneven 3/4/3 code word of balance CMD data

Input and output

A 00 0-223 0 equilibrium criterion type code word

B 00 224-255 1 contain the lack of equilibrium of superfluous " 1 "

The data type code word

C 01 0-127 1 contain the lack of equilibrium of superfluous " 1 "

Contain and make the type code word

The command type code word of D 01 128-255 1 the same " C "

0-127

The equilibrium criterion type generation of E 10 0-223 1 the same " A "

Code word

The lack of equilibrium data type of F 10 224-255 0 above-mentioned " B "

The complement code of code word, but contained

" 0 " that remains

The lack of equilibrium command type of G 11 0-127 0 above-mentioned " C "

The complement code of code word, but contained

" 0 " that remains

The command type code word of H 11 128-255 0 the same " G "

Complement code

The first three columns of this table is represented the input of ROM 46C, (that is, the ROM address), and the 11st or unbalanced signal of output shown in the 4th tabulation, and 10 code word outputs are shown in the 5th tabulation.

Look-up table is supplied with toggle flip-flop circuit 44a with the UNBALANCE signal, on the 46a that adds to storage then, as described in conjunction with Fig. 2.

5. multiple eight hyte digital coding circuit

Fig. 4 illustrates a kind of combined encoder 60 of multiple (for example 4) eight hyte words being carried out the parallel block coding with parallel mode.This circuit 60 comprises 4 parallel uneven detector 62a-62d, 4 10b/10b component coder 66a-66d, each usually as shown in Figure 3A, in addition, circuit 60 also comprises memory 74.

To 48 hyte word parallel processings the time, uneven minimum for making, can appear at the difficulty of not run in the unblocking coding.Specifically, in combined encoder 60,10 input words of each of each component coder 66a-66d or comprise data or comprise command information, can point out whether this output code word is uneven, as above described in conjunction with Fig. 3 A, but make the uneven minimum correct selection of piece depend on the performance of all component coders, and component coder is interrelated and must depend on the information (outside each component coder self circuit) that the outside provides thus the imbalance of crossfire that makes generation for minimum.

Provide a kind of method of external information to be, serially from the one-component encoder to another encoder, and turn back to first encoder ground from last component coder and supply with a feed forward signal, make accumulative total direct current offset minimum with the selection that acts on follow-up code word.Yet, because the pulsation required time is usually oversize so that can not finish in the single clock cycle from the encoder to the encoder, so can not make in this way in some applications.

A kind of faster and best method as shown in Figure 4, this method need be used and select the unbalanced signal generator, this generator comprises 4 uneven detector 62a-62d, a read-only memory 74 and a latch 76.Detector 62a-62d with they separately UNBALANCE signal U1-U4 give memory 74 as address signal, this memory also receives the PRIOR BALANCE(forward horizontal stand as the part of its address input) signal.Memory 74 can be single 5 inputs/5 output ROM or PLA.SELECT UNBALANCE look-up table of memory 74 storages.The output of this look-up table offers combined encoder 66a-66d as the SELECT UNBALANCE signal to 4 signal line S1-S4.This SELECT UNBALANCE signal is pointed out the suitable direct current non-equilibrium state by each this code word to be selected among 4 combined encoder 66a-66d.A NEXT BALANCE(next one balance with memory 74) carry-out bit is supplied with its latch 76 that is output as PRIOR BALANCE signal, and described NEXT BALANCE signal points out to be used to produce the imbalance of next SELECT UNBALANCE signal.Latch 76 keeps NEXT BALANCE signal, and gives memory 74 with it in the clock cycle, and in the described time cycle, four signal UNBALANCE signal U1-U4 of next group are provided by uneven detector 42a-42d.Like this, this NEXT BALANCE signal is a feedback signal, and this signal cycle is to produce the unbalanced history of front.

Latch 78 on the circuit incoming line receives CMD and A7-A0 input and delivers to uneven detector 62a-62d and encoder 66a-66d with the same clock cycle as buffer.Latch 76,78 preferably starts clock with the same moment.

This SELECT UNBALANCE table that is stored in the memory 74 is as shown in table 4.

Table 4: the look-up table of Fig. 4 memory

PRIOR U1 U2 U3 U4 NEXT S1 S2 S3 S4

BALANCE BALANCE

0/1 0 0 0 0 0/1 X X X X

0/1 0 0 0 1 1/0 X X X 1/0

0/1 0 0 1 0 1/0 X X 1/0 X

0/1 0 0 1 1 0/1 X X 1/0 0/1

0/1 0 1 0 0 1/0 X 1/0 X X

0/1 0 1 0 1 0/1 X 1/0 X 0/1

0/1 0 1 1 0 0/1 X 1/0 0/1 X

0/1 0 1 1 1 1/0 X 1/0 0/1 1/0

0/1 1 0 0 0 1/0 1/0 X X X

0/1 1 0 0 1 0/1 1/0 X X 0/1

0/1 1 0 1 0 0/1 1/0 X 0/1 X

0/1 1 0 1 1 1/0 1/0 X 0/1 1/0

0/1 1 1 0 0 0/1 1/0 0/1 X X

0/1 1 1 0 1 1/0 1/0 0/1 X 1/0

0/1 1 1 1 0 1/0 1/0 0/1 1/0 X

0/1 1 1 1 1 0/1 1/0 0/1 1/0 0/1

Wherein, the accumulative total direct current offset that PRIOR BALANCE points out the front for " 0 " for-1(promptly, 6 " 0 " and 4 " 1 "), and PRIOR BALANCE is " 1 ", points out that then the accumulative total direct current offset of front is+1, (that is, 6 " 1 " and 4 " 0 ").

Similarly, NEXT BALANCE for " 1 " point out next accumulative total direct current offset for+1(promptly, 6 " 1 " and 4 " 0 "), the accumulative total direct current offset that NEXT BALANCE then points out next uneven code word for " 0 " for-1(promptly, 6 " 0 " and 4 " 1 ").

According to pointing out the unbalanced input signal of which code word, BALANCE-TO-SELECT(selects balance) form is chosen as the employed non-equilibrium state of encoder 66a-66d." 0 " in the row in the SELECT UNBALANCE table in the input row (U1-U4) points out that selected code word is a balance, and " 1 " points out that selected code word is unbalanced.If " 0 " of selected code word more than " 1 ", the output of SELECT UNBALANCE form so, be that SELECT UNBALANCE signal is " 0 ", more than " 0 ", then be output as " 1 " as " 1 " of selected code word.Input illustrates SELECT UNBALANCE signal value " X " (for " 1 " or be " 0 ") to this SELECT UNBALANCE table to balance, in this case, and the code word that encoder 16a-16b preferably exports and uneven selection wire is irrelevant.

Whenever the value of PRIOR BALANCE signal is " 1 ", all carry-out bit S1-S4 of this look-up table are the complement of two's two's complement of their value at PRIOR BALANCE signal value during for " 0 ".Shown in Fig. 4 A, for saving space on the page, SELECT UNBALANCE table to be divided half-and-half, two values of complementary inlet are divided by slash as shown in FIG..Lvalue is used for PRIOR BALANCE=" 0 " and r value is used for PRIOR BALANCE=" 1 ".(optional method of realizing this purpose is to use one group of parallel partial sum gate at memory 74 outputs, among the output signal S1-S4 of look-up table each is delivered on different in each partial sum gate doors as first input, then be added on each partial sum gate as the second public input from the PRIOR BALANCE signal of latch 76.

6. use the 16b/20b coding of 8b/9b and 10b/11b coding

The 8b/10b code need use some uneven code words.Although the input word length also doubles to reach 16.Yet, by being put, the code word size is twice 20, can obtain the code that all code words are balance.

For this reason, 10 of 20 pieces must have same logical value.So having length is 20 C(20/10)=20! / 10! * 10!=184,756 kinds of balanced code words that have nothing in common with each other.Therefore, to 2 ¹⁶=65536 input values, all the representing of 20 code words of available ready-made balance.(on the other hand, the 16b/19b code produces some uneven code words, and the code word of any kind that the 16b/18b code forms all seldom).16b/20b digital coding process also provides such advantage, and is promptly the same with the 8b/10b code, and using input value is 8 multiple, thus can with the hardware and the program compatibility of 8 hytes.

Be made in ROM on the CMOS chip or PLA carries out the 16b/20b coding in order to use by prior art, the 16b/20b cataloged procedure is preferably divided size approximately equalised 2 or a plurality of cataloged procedure so that chip area is kept to minimum.

The 16b/20b coding is divided into 2 8b/10b codings, and the result has only C(10/5)=252 balanced code words, promptly be not enough to represent each 8 input value desired 2 ⁸=256 input values.On the other hand, if enlarge the available codes collection, can obtain enough code words certainly, but introduce the direct current imbalance certainly with unbalanced 10 code words.

Yet,, 20 bit combination code words of enough available balance are so just arranged as the 16b/20b coding being divided into two unequal part: 8b/9b and 10b/11b coding.And 9 still 11 code word all can not balance, the odd length code word can not balance, 9 and 11 code words can only be restricted to uneven minimum and opposite imbalance is arranged, and makes that with code word and when putting, result's piece is a balance.

In 9 codes, always total C(9/4)=126 code word and 126 code words with a surplus " 0 " position with a surplus " 1 " position.252 such code words can separately be used, and promptly in this scheme, represent different input values with 9 code words and complement code thereof, and they can not be as the optional method of the same input value of expression.In 11 codes, always total C(11/5)=462 have the code word of single surplus " 1 " position and the code word that has single surplus " 0 " position of same number.Yet, different with 9 code words, must be with 11 code words alternately representing of complementation as same input; During in using effective 252 9b code words one, the imbalance of 11 code word must and this 9 code words uneven complementary, to produce the overall balance of 20 pieces completely.So 252 * 462=116 is arranged, 424 code words, expression 2 ¹⁶Individual numerical value is more than sufficient.

Yet, use 116,424 all code words very loose to the restriction of the maximum string length of coding stream.For example, use 000011111 and 11111000000 and put when forming 20 blocks, can produce maximum string length is 10.Yet, use the forward error correction code bit to allow maximum string length is limited, promptly use 96 blocks, each block is protected by 8 FEC positions and 8 complementary FEC positions, and complementary FEC position is opposite between each of 4 9b and 11b section.In this case, using the maximum string length of above-mentioned word is 7.

Can see as the form from Fig. 2, what have single surplus " 0 " position always has 391 11 code words and 113 9 code words, meets 3/4/3 maximum string length standard.Also have 113 9 code words that have single surplus " 0 " position.If to being used between each 9 of this limited code word collection and 11 code words, can reach maximum string length so is 4 with complementary FEC.Have 4 bit strings, 20 code words long, balance of 391 * 2 * 113=88366 such expression data, expression 2 ¹⁶=65536 input values are more than sufficient, therefore, have 22830 code words to can be used as other purposes.

In these 22830 additional codewords, for example can be with 2 ¹⁴=16,384 code words as the expression command information, i.e. " command code word ".Preferably come the marking command code word with this quadrat method, promptly by one " order circuit " is set, this order circuit is for inputing or outputing circuit, and this order circuit can input or output circuit separately with 16 data.In other words, the order circuit is set code word is identified as the information that expression is ordered, and 16 orders that line description is specific in addition.Yet, because the ascii character code collection does not allow 2 ¹⁶Individual bid value is so when the order circuit was effective, two highest orders were insignificant.In this case, keep 2 ¹⁴=16,368 values are used for representing command code.However, also surplus 6446(＞4096=2 ¹²) code word is in order to represent extra data type or kind, they can be described as " free time " code word.The 16b/20b code word preferably not only can represent 2 ¹⁶Individual data word and 2 ¹⁴Individual command word, and can represent 2 of the 3rd class ¹²Individual free word.

Free word can be used for various purposes.For example, these free word can be sent link and be used for initialization, perhaps, when the link input does not have valid data, send free word to keep desired maximum crossfire characteristic (idle link).2 ¹²Individual available 12 code words (in this embodiment as free word) also can strengthen the ability of 8 hyte data of 16b/20b coded representation and order, and are as described below.

Though it is 20 bit data code words of 4 balance that 88,366 maximum string length are arranged, and realizes such code and do not exceed effective consistent ascii character code collection to be not categorical with 8b/9b with the 10b/11b encoder.Specifically, if the encoder incoming line is exactly the circuit that has 16 inputs simply, just so without limits to input value.Therefore, arrive the number (2 of the possible input word of 8b/9b encoder ⁸=256) can exceed and 9 numbers (226) that code word is consistent, arrive the number (2 of the possible input word of 10b/11b encoder ¹⁰=1024) can be above meeting 11 numbers (391) that code word is right.This short wooden stake just needs logical transition.

Although " random logic circuit " of available AND gate or OR-gate realized, the best is embodied as ROM or PLA look-up table.The ROM or the PLA that carry out necessary conversion in the digital coding process are called " precoder " logic, are called " precoder " simply.

Precoder preferably produces some precoder code words, when these precoder code words are added to 8b/9b and 10b/11b encoder as input, the restriction that can not exceed the code set of 8b/9b and 10b/11b encoder, and the major part of this encoder sign indicating number collection is used in permission.In addition, the bar number of the data circuit by the precoder sub-fraction in 16 input data lines altogether preferably.Otherwise when increasing order circuit and idle line, the circuit sum can make precoder ROM or PLA chip area excessive.On the contrary, make that I haven't seen you for ages causes sending to the loss of quantitative aspects of the numerical value of 9b and 11b encoder by the circuit number of precoder conversion.

As noted before, having 226 9 bit value and 391 11 bit value is 20 balanced codes of 4 in order to maximum string length to be provided.Can draw with these data of binary representation:

226（dec）＝11100010（bin）

391（dec）＝110000111（bin）

It is evident that, if the numerical value that is equal to or greater than 11100000=112 is not sent to the 8b/9b encoder, also the numerical value that is equal to or greater than 110000000=384 is not delivered to the 10b/11b encoder, which this input provide the capacity of the encoder of code word can " not overflow " to so.In fact, 8b/9b encoder not input is just necessary with all three highest order set, and when the 10b/11b encoder is not imported, just should be with 2 highest order set.

7. use the 16b/20b encoder towards 16 words of 8b/6b and 10b/11b sub-encoders

Fig. 5 shows a kind of encoder 80 towards the 16b/20b of 16 words of combination.Encoder 80 comprises precoder 82,8b/

9b component coder

84 and 10b/11b component coder 86.For the purpose of conceptual purpose, this figure has also drawn inverter 88.The input of encoder 80 is a highest order by 16 bit data D15-D0(D15), order circuit input CMD and idle line input IDLE(free time) form.Data In-Line road D11-D5 walks around precoder 82 and is directly coupled to the input A7-A1 of 10b/11b encoder 86.Data circuit D4-D1 also walks around precoder 82 and is coupled to the input B4-B1 of 8b/9b encoder 84.Incoming line D0 is connected with the B0 input of 8b/9b encoder 84 and judges the imbalance that this encoder is exported.Include inverter 88 uneven opposite with the imbalance of pointing out the output of this encoder and the output of 8b/9b encoder, certainly, although owing to the look-up table of 10b/11b encoder 86 can be arranged to directly realize this function, so this inverter is not that to obtain this result necessary.

If the not set of D0 line, encoder 84 provides the output with single surplus " 0 ", and encoder 86 provides the output with single surplus " 1 ".When the set of D0 line, two encoders are output as the complement code that the D0 line is not exported during set.Signal on the look-up table response D0 line of encoder 84,86 is to produce desired code word.Another program is certainly, can produce complementary data by the linear array that uses anticoincidence circuit.

Being stored in encoder 84 and 86 9 and 11 code words respectively is 1 from its accumulative total direct current offset that is produced by computer preferably, selects in the code word table of its maximum string length 3/4/3.Be entitled as described in the 2nd joint of " string length introduction " as the front, this table can be produced by programming, that is, computer is listed each possible 9 and 11 code words with ordering and each word is tested those code words that satisfy 1 accumulative total direct current offset standard and 3/4/3 maximum string length standard to find out.Be stored in respectively in encoder ROM84 and 86 satisfying 9 of above-mentioned two standards and 11 words value as code word.

Represented by the available following table 5 of conversion that precoder 82 is carried out.

Table 5: the conversion lookup table of Fig. 5 precoder

The incoming line outlet line

C2 C1 D15 D14 D13 D12 A9 A8 B7 B6 B5

DATA 0 0 0 0 0 0 0 0 0 0 0

DATA 0 0 0 0 0 1 0 0 0 0 1

DATA 0 0 0 0 1 0 0 0 0 1 0

DATA 0 0 0 0 1 1 0 0 0 1 1

DATA 0 0 0 1 0 0 0 0 1 0 0

DATA 0 0 0 1 0 1 0 0 1 0 1

DATA 0 0 0 1 1 0 0 0 1 1 0

DATA 0 0 0 1 1 1 0 1 0 0 0

DATA 0 0 1 0 0 0 0 1 0 0 1

DATA 0 0 1 0 0 1 0 1 0 1 0

DATA 0 0 1 0 1 0 0 1 0 1 1

DATA 0 0 1 0 1 1 0 1 1 0 0

DATA 0 0 1 1 0 0 0 1 1 0 1

DATA 0 0 1 1 0 1 0 1 1 1 0

DATA 0 0 1 1 1 0 1 0 0 0 0

DATA 0 0 1 1 1 1 1 0 0 0 1

DATA 0 1 X X 0 0 1 0 0 1 0

DATA 0 1 X X 0 1 1 0 0 1 1

DATA 0 1 X X 1 0 1 0 1 0 0

DATA 0 1 X X 1 1 1 0 1 0 1

DATA 1 0 X X X X 1 0 1 1 0

From the right of this table as seen, A9 and A8 are " 1 " never simultaneously, and B8, B7 and three of B6 can not be " 1 " simultaneously.So, avoided use can exceed the input value of the 8b/9b and the 10b/11b encoder of consistent code sign indicating number collection.Notice, be used for order and free time for work " X " value of D14 and D15, in addition, D12 and D13 are used for the free time as X, output is identical to ROM with PLA, and no matter point out the numerical value of these circuits in the state.Also note that,, always have 2 because the circuit that has is walked around precoder 82 ¹⁶Individual data, 2 ¹⁴Individual order and 2 ¹²Individual free word can be encoded.

8.8 the 16b/20b encoder of position hyte data

In 16b/20b described above, the input of encoder 80 or comprise data or comprise command information rather than comprise both 16 words.16b/20b encodes also applicable to the input value based on 8 hytes, i.e. 28 words.Each 8 input word can be represented 8 bit data or 5 command information.Like this, 16 input values can be data-data sequence (promptly, each 8 hyte comprises data), order-command sequence (promptly, each 8 hyte comprises command information), data-command sequence (be first 8 hytes comprise data and second 8 figure place comprises command information), or order-data sequence (be that first 8 figure places comprise command information, and second comprising data).

Except that 16 data wires, also have two additional order circuits of pointing out other 16 circuit contents (whether being data-data, order-data etc. promptly) together.In data-data sequence, all 16 lines all have data, and 2 possible input words are so just arranged, and each possible input word is specified an individual code.

This system's regulation has only 32(=2 ⁵) individual different possible command word, 3 highest orders that comprise in data-command sequence 8 hytes of an order are expected to be 0, and use all 8 of 8 hytes of data.So, must be with 2 to data-command sequence ⁵* 2 ⁸=2 ¹³Individual different possible input word is appointed as code word, and with other 2 ¹³Individual order one data sequence of being appointed as always has 2 ¹⁴Individual code word is used for data-order and order-data sequence.Order-the command sequence that allows is needed other 2 ⁵* 2 ⁵=2 ¹⁰Individual code word.

In the coding circuit of Fig. 5, do not increase and be used for two 8 hyte input words are transformed to the logic of 16 input word, and another more straightforward procedure is arranged, promptly provide suitable precoder conversion lookup table to finish desired task.

Fig. 6 illustrates the 16b/20b coding circuit 90 that makes in this way this method of two 8 hyte input values codings.In Fig. 6, represent 28 inputs with data wire A1-A8 and B0-B7 respectively.A 1 order of the bit/data circuit A-CMD points out that 8 input word A1-A8 represent command word or data word.Another 1 bit line B-CMD points out that input word B0-B7 represents command word or data word.Precoder 92 take orders signal A-CMD, B-CMD and input value, for example, data or command information A8-A6, B7-B5.Output A9 '-A6 ' from precoder 92 is added to 10b/11b encoder 94, and this encoder 94 also receives input value A5-A1.The encoder 86 of 10b/11b encoder 94 and Fig. 5 is identical.Other output B7 '-B5 ' of precoder 92 is offered 8b/9b encoder 96, and this encoder is received signal B4-B1 and BALANCE signal B0 also.The encoder 84 of 8b/9b encoder 96 and Fig. 5 is identical.By inverter 98 with BALANCE order B0 anti-phase and as another the input A0 be added on the encoder 94.

Following table 6 illustrates the truth table of being realized by precoder 92.

The conversion lookup table of the precoder of table 6: Fig. 6

CA?CB?A8?A7?A6?B7?B6?B5?A9'?A8'?B7'?B6'?B5'?A7'?A6'

Data 00 D D D D D D D D D D D D D

B-CMD 0 1 0 0 0 X X X 1 0 0 1 0 0 0

B-CMD 0 1 0 0 1 X X X 1 0 0 1 0 0 1

B-CMD 0 1 0 1 0 X X X 1 0 0 1 0 1 0

B-CMD 0 1 0 1 1 X X X 1 0 0 1 0 1 1

B-CMD 0 1 1 0 0 X X X 1 0 0 1 1 0 0

B-CMD 0 1 1 0 1 X X X 1 0 0 1 1 1 0

B-CMD 0 1 1 1 1 X X X 1 0 0 1 1 1 1

A-CMD 1 0 X X X 0 0 0 1 0 1 0 0 0 0

A-CMD 1 0 X X X 0 0 1 1 0 1 0 0 0 1

A-CMD 1 0 X X X 0 1 0 1 0 1 0 0 1 0

A-CMD 1 0 X X X 0 1 1 1 0 1 0 0 1 1

A-CMD 1 0 X X X 1 0 0 1 0 1 0 1 0 0

A-CMD 1 0 X X X 1 0 1 1 0 1 0 1 0 1

A-CMD 1 0 X X X 1 1 0 1 0 1 0 1 1 0

A-CMD 1 0 X X X 1 1 1 1 0 1 0 1 1 1

AB-CMDS 1 1 X X X X X X 1 0 1 1 0 0 0

IDLE 1 1 X X 0 X X 1 1 0 1 1 0 0 1

IDLE 1 1 X X 1 X X 0 1 0 1 1 0 1 0

IDLE 1 1 X X 1 X X 1 1 0 1 1 0 1 1

In this table, the first row group represents incoming line (for example, the ROM address road), secondary series group (going up the marker tape apostrophe) expression outlet line (for example, be stored among the ROM value).For shortening the printing scale of truth table in the table 6, in the figure, represent preceding 64 row of truth table with single row.In this table, " X " points out that its value does not influence the signal of output." D " points out that corresponding inlet can be " 0 " or " 1 "." X " difference, " D " of input side points out that the different value of these input signals can produce the different value of the output signal of being represented by D.

When CA=CB=0, input word A1-A8 and B0-B7 represent data word rather than command word.In this case, precoder 92 carry out 6 precoder data inputs (A8-A6, B7-B5) and 7 precoder data output (B7 '-B5 ', A9 '-A6 ') between man-to-man mapping.Can use any man-to-man mapping, as long as this mapping is not violated preventing necessary two restrictions of overflowing of 8b/9b encoder and 10b/11b encoder.These two restrictions are, at least one must be set at the value logical zero among three-line B7 '-B5 ', and at least one must be set at the value logical zero among two circuit A8 ' and the A9 '.In table 6, represent the input data of two 8 hytes with 10b/11b encoder input A9-A0 and 8b/9b encoder input B7-B0.External data is added on 8 A1-A8 and the B0-B7 circuit.The B0-B4 input is walked around precoder and is directly entered the 8b/8b encoder.B0 determines the non-equilibrium state of 8b/9b encoder output, with B0 anti-phase and deliver to the 10b/11b encoder the A0 input so that its output balance compensate mutually with the balance that the 8b/9b encoder is exported.The A1-A5 circuit is also walked around precoder and is directly entered the 10b/11b encoder.Incoming line A6-A8 and B5-B7 enter order wire A-CMD and B-CMD enters precoder (8 incoming line) and precoder has 7 outlet line A9 '-A6 ', B7 '-B5 '.

9. forward error correction is encoded

The type of the forward error correction sign indicating number that uses can be, for example, and single error correction, two wrong correction, specifically, such as being that 4 code is (with reference to by Shu Lin ﹠amp by the improved Hamming distance of Hsiao; Daniel J.Costello, the book that Jr. showed " error control coding ", PRENTICE-HALL nineteen eighty-three is published the 498th to the 502nd page).This code is linear, is because any two coding numerical value sums derive another coding numerical value.These codes also can be systems, that is, coded data partly is not that coded data variation never obtains.So, by and large, the FEC position be added to make the combination of FEC position and data code word provide distance 4 codings on the data code word.The method that can obtain the FEC sign matrix of 1 * P by FEC matrix multiple with the matrix data word of 1 * B and B * P produce FEC everybody, data code word total bit in " B " expression piece wherein, and the figure place of " P " expression FEC.This piece total bit is L=B+P.

Under present condition, the piece (i.e. 4 20 data code word) that the protection of available 8 FEC positions is 80.Therefore, B=80 and P=8.Produce 80 row of FEC matrix, use 8 vector sequence, each vector comprises odd number " 1 " position, and this odd number is at least 3.Because have 3 " 1 " position have only 8! / 3!=56 vector sequences, and have 80 will protect, so also must use 8 bit vector sequences of the complementary type that comprises 5 " 1 " values.Owing to also there are 56 complement code sequences; derivation adds up to 112(and also exists another group to contain 8 vector sequences of 7 " 1 " values; these vector sequences need not use) and have only 80 to have to be protectedly, so select which 80 from 112 vectors to use be arbitrarily.Make " 1 " figure place in the vector minimum make coding and decipher the required number that activates door be kept to minimum.

It (that is is not by the rotatable sequence unit sequence of conversion mutually usually, that the best approach that produces the FEC position is to use circulation independent code sequence.From containing the angle of sequence of 3 " 1 " position, below 7 irrelevant variations of circulation be easy to enumerate:

[00000111]，[00001011]，[00010011]，

[00100011]，[01000011]，[00010101]，

[00100101]

Rotation with above-mentioned these sequences are carried out through whole 8 kinds of possible circulation change can produce and add up to 56 FEC code.In addition, the complementary series that comprises 5 " 1 " can produce by all the anti-phase methods in the code that will obtain under 3 " 1 " situations.

10. illustrative communication system

Fig. 7 illustrates according to communication system 100 of the present invention.System 100 is point-to-point optical fiber data links.Illustrated element can adopt two CMOS chips for example carrying out digital coding, decoding and framing to realize in the system 100.

System 100 comprises transmitter part 100a and receiver part 100b.In transmitter part 100a, the input data are received by encoder 102 as one 32 parallel-by-bit stream, and encode and add the forward error correction position, so that form the ECC code word by the above mode.Encoder 102 is preferably realized as shown in Figure 1.In encoder 102, this data multiplex is transferred to nearly 16 parallel word, deliver to 16: 1 multiplexers (" MUX ") 104 then, connect laser transmitting set 106 behind this multiplexer 104, this serialized data is the input that the laser that drives link or channel 108 send device 106.

In receiver part 100b, be transformed to the signal of telecommunication by link 108 received optical signals optical receiver/converters 110 and also amplified, deliver to clock recovery module 112 then.By these module 112 recovered clock and data and be added to conventional 1: 16 demultiplexer 114 when resetting.This demultiplexer 114 is added to framing and data recovery circuit 120 with 16 electrical signal sequence.Framing and data recovery circuit 120 carries out that further multiple signals separate, framing to be determining 96 FEC code block boundaries, and error correction and data decoding flow to obtain data recovered.This data recovered stream is that 32 parallel-by-bits are streamed, comprises 32 DATA and 2 CMD, the form of the source data of similar above-mentioned supply transmitter part 100a.

During coding and decoding, control and state information by the register access in encoder 102 and the decoder 120 by each microprocessor 122,124.

11.FEC the framing of code block and data decoding

When the initial receiving communication signal of receiver 110b, the bit stream of arrival lacks the border of any sign FEC code block starting and ending.Therefore, framing and decoding circuit 120 must identify these borders,, the FEC code block are divided into frame that is, so that can proofread and correct and data decoding by execution error.This carries out before reception real data normally between the receiver 100b starting period.

Fig. 8 has provided framing and decoding circuit 120.16 bit sequences from 1: 16 demultiplexer 114 are added on the register 200 one at a time.Then, register 200 is with its content, and promptly 16 bit sequences are added on 1: 6 demultiplexer 202 that produces 96 outputs.This 96 bit sequence is supplied with register 204.Register 204 offers framer circuit 205 with its 96 contents, and this framer circuit comprises the generator 206 of makeing mistakes, FEC verification 208 and error counter 210.This framer circuit 205 is used as the FEC code block to each 96 bit sequence and is handled and calculate contained mistake number in this piece like that, and wherein contained mistake is to be pointed out by the position of this sequence of the position, position that occupies the FEC symbol.

Specifically, if this sequence assembling is correct, just be added to the generator 206 of makeing mistakes to 80 in 96 bit sequences that comprise the data code word with 8 that can be the FEC position.Mistake during this generator 206 of makeing mistakes detects these 88, and produce one 8 ERROR(mistake) signal, this ERROR signal contains " 0 " entirely when not detecting mistake, and when makeing mistakes generator 206 unit of detecting mistakes, contain odd number " 1 ", and when the generator 206 of makeing mistakes detects double error, contain even number " 1 ".The generator of makeing mistakes like this is easy to make the ready-made part of single integrated circuit chip form.

When the generator 206 of makeing mistakes receives 88 pieces of 96 bit sequences, register 204 will be delivered to FEC verification 208 from same 96 bit sequences, 8 FEC positions of correspondence and 16 of their 8 bit complements.Whether the position that 208 pairs of this FEC verifications receive compares, check each FEC position with its complement code and put.As there not being complementary pair, the FEC-ERROR(FEC mistake has been asserted in this FEC verification 208).

Error count circuit 210 receives from 8 ERROR signals of the generator 206 of makeing mistakes with from the FEC-ERROR signal of FEC verification 208.To each mistake of pointing out by the generator 206 of makeing mistakes, promptly to each unit mistake or dibit mistake, these error count circuit 210 count-up counters.If to 90 any pieces, make mistakes generator 206 and FEC verification 208 all do not detect mistake, are 0 with this counter reset.

If this counter reaches pre-selected threshold, 8 mistakes for example, error count circuit 210 is delivered to a BIT SLIP signal SLIP or the SKIP input of 1: 16 demultiplexer 114 so.This signal makes demultiplexer 114 skip of serial data stream of input, as mentioned above, so that change of the 96 bit sequence frames alignment that offers register 204.(demultiplexer with this " slip-stream " (" Slip ") or " skipping " (" Skip ") function is easy to find ready-made commodity) checks 96 bit sequences that this is new once more by framer circuit 205 then.

This process proceeds to 96 bit sequences (for example, the 10) zero defect of finding predetermined number.At this moment, suitably start receiver 100b, then can carry out error recovery and data decoding.

Any detected mistake in the data code word of 96 FEC code blocks of conventional H siao error correction circuit 212 recoverable neotectonics frames, and the data code word offered register 218, this register is supplied with 2: 1 multiplexers 220 with described data code word.This multiplexer 220 provides first pair data code word, is about to preceding 40 data code word and offers data decoder 222.222 pairs of data code words that received of this data decoder are deciphered, to recover to comprise data and command information wherein.The output of this data decoder 222 is stored in the register 224 with 32 DATA-OUT and 2 CMD-OUT value.Provide remaining 2 data code words by 2: 1 multiplexers 220 then, be about to 40 last supply decoders 222, produce one 32 DATA-OUT signal and one 2 CMD-OUT signal once more by this decoder.

The illustrative embodiment of decoder 222 is described now.This decoder is deciphered the data code word that is for example formed by encoder.This data decoder 222 has two same, parallel decoding branches, and each is used to decipher a code word.In each branch, 20 of receiving the data code word are delivered to 11b/10b and 9b/8b decoder.Like this, to deliver to the back decoder from three highest orders of 9b/8b decoder with from 2 highest orders of 11b/10b decoder, this back decoder is carried out the operation opposite with Fig. 5 precoder 42, just, shown in this Fig. 5 A, carry out searching from right to left to the table among Fig. 5 A (being included in pre-decode device and the precoder 42).The output of this decoding circuit can be reproduced whole 18 line signals of the input of Fig. 5 coding circuit 40 exactly.

Yet, between decoding circuit and coding circuit 40, have some difference at least, at the output of decoding circuit not corresponding to the effective word of order and idle line set.At the output of decoding circuit, preferably will order and idle line on the appearance of " 1 " be used to refer to the reception of invalid code.

Using system 100 is optimized so that transmit by optical fiber link 108 character of serial data stream of coding.According to various aspects of the present invention, keep short maximum string length and help clock recovery and make low frequency energy be kept to minimum, and dc balance allows the receiver of the AC coupled by using high-gain to carry out reliable code to restore.Maximum string length is preferably 4, that is, when error-free, do not have more than 4 in succession logical one or logical zero appear in the serial data stream.Preferably will add up direct current offset to be restricted in each code word+4, and be defined as 0 in each 24 seat block end place.For these numerical value, the gross efficiency of the link 108 of system 100 is 2/3.

12. other data encoding technique

Coding techniques as described above all uses coding twice, i.e. digital coding before this, and the most handy 3/4/3 code is the FEC coding of the piece (for example, 96 pieces) that comprises a plurality of (for example 4) data code word then.By everybody is dispersed between the data code word with FEC, making the last bit stream of signal of communication reach maximum string length is 4.

Also the new technology of many error protection codings can be used for difference effectively uses in conjunction with the described data-encoding scheme of illustrative embodiment of the present invention.For example the use of the distribution of paratope or 96 FEC pieces can be above mentioned IBM 8b/10b code and uses.And described herein error protection coding techniques can be used for even not adopting the occasion of digital coding, promptly only wishes coding sequence is not protected the occasion of coding.

On the other hand, only needing the application scenario of digital coding also can obtain many advantages of the present invention.Yet, although the requirement of application is depended in the selection of code,, preferably using 2/4/2 code for keeping short string length, 1/4/3 code or 3/4/1 code replace above-mentioned 3/4/3 code.Although use different codes, the encoder circuit shown in Fig. 3,4 and 5 also is applicable to the code word that the input value digital coding is limited the accumulative total direct current offset for band.

For example, the uneven standard of the uneven detector circuit 42 of Fig. 3 can be by used code appropriate change.For example, 10 code words to 2/4/2, this standard can change into: from 0 to 123 input value is expressed as the unbalanced data code word, from 124 to 255 input value is expressed as the data code word of balance, and the value between 256 to 303 can be represented the command code word (48 command code words altogether) of balance.In other words, to 2/4/2 code, the standard of uneven code word of expression data is any input values less than 124, with binary representation, is exactly that its 5 highest orders are not any input value of the data of logical one.

The description of front is confined to the specific embodiment of the invention always.Yet, it is evident that and can be used for various modifications and modification, and can obtain part or all of advantage of the present invention the present invention.Therefore, the purpose of appending claims is to cover improvement and the modification of all these, and these improve and modification is included within scope of the present invention and the connotation.This specification is defined as to be write without limitation with illustrative.

Claims

1, a kind of encoder includes:

Each that is used for a plurality of digital signal bit sequences is encoded into the sequential coding device of a plurality of first generation code words, and each first generation code word has maximum string length and is lower than pre-selected limits and adds up the feature that direct current offset is lower than pre-selected limits, and

The protection code device that is coupled and is used for therefrom receiving first generation code word and produces a plurality of error protection symbols by this first generation code word with described sequential coding device.

2, encoder according to claim 1 is characterized in that each first generation code word is a dc balance.

3, encoder according to claim 1 is characterized in that also comprising and described sequential coding device and described protection code device are coupled, are used to form the device of the piece that comprises a plurality of first generation code words and a plurality of error protection symbols.

4, encoder according to claim 3 is characterized in that, piece forms device at least one error protection symbol is placed between the first generation code word of piece.

5, encoder according to claim 4 is characterized in that, also comprises with institute protection code device the device of the complement of two's two's complement that is coupled, is used to construct the error protection symbol.

6, encoder according to claim 5; it is characterized in that: described forms device and is coupled with described complement code formation device and is used for therefrom receiving complement code, forms a plurality of complementary pairs; and at least one complementary pair placed between first and second of described a plurality of first generation code words in this piece, each complementary pair comprises an error protection symbol and its complement code.

7, encoder according to claim 6 is characterized in that, each piece comprises 96.

8, encoder according to claim 7 is characterized in that, each piece comprises 4 20 first generation code words, 8 error protection symbol, and the complement code of 8 described error protection symbol.

9, encoder according to claim 8 is characterized in that, each first generation code word has 3/4/3 maximum string length, and described maximum string length is 4.

10, encoder according to claim 9 is characterized in that, each sequence comprises 16, and described sequential coding device is one 20 first generation code word with each sequential coding.

11, encoder according to claim 10 is characterized in that, described sequential coding device is encoded to 10 second generation code word and 10 third generation code word with each 16 bit sequence, and they constitute the first generation code word of this sequence jointly.

12, encoder according to claim 10 is characterized in that, described forms device and form each piece by 4 second generation code words and 4 third generation code words, and with a complementary pair place each second and third generation code word between and place, an end of this piece.

13, encoder according to claim 10 is characterized in that, described sequential coding device is encoded into 9 second generation code word and 11 third generation code word with each 16 bit sequence, and these two codes constitute the first generation code word of this sequence jointly.

14, encoder according to claim 13 is characterized in that, described forms device and form each piece by 4 second generation code words and 4 third generation code words, and with a complementary pair place each second and third generation code word between and place, an end of this piece.

15, a kind of encoder includes:

Be used for a sequential coding device that is encoded into a plurality of first generation code words with a plurality of digital signal bit sequences, each first generation code word has maximum string length and is lower than pre-selected limits and adds up the feature that direct current offset is lower than the pre-selected limits value,

Be coupled, be used for therefrom to receive first generation code word and produce the protection code device of a plurality of error protection symbols with described sequential coding device by this first generation code word, and

Be coupled, be used to form the device of the complement of two's two's complement of error protection symbol with described protection code device.

16, encoder according to claim 15 is characterized in that: also comprise with described sequential coding device, described protection code device and described complement code and form the device device coupling, that be used to form the piece of the error protection symbol that comprises time a plurality of first generation code words, produced by a plurality of first generation code words of this time and complement code thereof.

17, encoder according to claim 16 is characterized in that, described forms device at least one error protection symbol is placed between the piece first generation code word.

18, encoder according to claim 17; it is characterized in that; described forms device and forms a plurality of complementary pairs, and at least one complementary pair is placed between first and second of a plurality of first generation code words in the piece, and each complementary pair comprises an error protection symbol and its complement code.

19, encoder according to claim 18 is characterized in that, described forms device one in the complementary pair is placed between per 2 first generation code words.

20, encoder according to claim 19, it is characterized in that, the sequential coding device becomes common second and the third generation code word that constitutes first generation code word with each sequential coding, and described form device with one in the complementary pair place each second and third generation code word between.

21, a kind of encoder includes:

Be used to receive a plurality of digital signal bit sequences and produce the protection code device of a plurality of error protection symbols from this bit sequence, and

22, encoder according to claim 21; it is characterized in that also comprising with described protection code device and described complement code and form the device that device is coupled, is used to form the piece of the error protection symbol that comprises time a plurality of bit sequences and produced by a plurality of bit sequences of this time and complement code thereof.

23, encoder according to claim 22 is characterized in that, described forms device at least one error protection symbol is placed between the piece bit sequence.

24, encoder according to claim 23; it is characterized in that; described forms device and forms a plurality of complementary pairs, and at least one complementary pair is placed between first and second of bit sequence in the piece, and each complementary pair comprises an error protection symbol and its complement code.

25, encoder according to claim 24 is characterized in that, described forms device one in the complementary pair is placed between per 2 bit sequences.

26, a kind of encoder to digital signal encoding is characterized in that comprising:

Be used to separate the signal into a plurality of and each block encoding become the data coding device of data code word,

With the coupling of described data coding device, be used for therefrom receiving a plurality of data code words, with a plurality of data code words each and be changed to second and produce a plurality of protection symbols to each second; each protection symbol is produced the protection code device of its complement code, and

Be used at least one protection symbol and complement code thereof are placed between the data code word that forms this piece so that form the device of protection code word.

27, a kind of combined encoder that is used to receive the combined encoder input signal of representing the input bit sequence row, in the described combined encoder input signal each comprises a plurality of position and a plurality of precoder input positions that comprise a plurality of component coder inputs position, described a plurality of precoder inputs position comprises at least one public precoder input position, and described combined encoder comprises:

Precoder, this precoder responds the combined encoder input signal, 1) according to the precoder code, a plurality of precoder output words are determined in precoder input position according to its each sequence, each precoder output word comprises at least one precoder carry-out bit, and according to the precoder code, a plurality of precoder output words are correlated with on a public precoder carry-out bit at least, 2) produce the precoder output signal of representing each precoder output word, and

The component coder related with each precoder output signal, each component coder is reacted to its related precoder output signal and at least one component coder input position, 1) according to the component coder code, determine code word, 2 according at least one component coder input position with by the represented precoder output word of the precoder output signal that is associated) produce the output signal of the component coder of the determined code word of representative.

28, a kind of combined encoder is characterized in that comprising:

A plurality of be used to receiving separately unbalanced signal and representing the separately encoder of the separately encoder input signal of encoder input word; So that 1) according to a kind of code; Determine separately code word according to received signal; Make the complementary pair of the code word with opposite disequilibrium and at least some input word be associated; Each encoder according to its separately the value of unbalanced signal between the complementary pair code word, select; 2) produce representative separately the separately encoder output of definite code word

The unbalanced signal generator, be used to monitor that the combined encoder input signal is to monitor the disequilibrium that encoder output adds up all the time and to discern the unbalanced encoder of its output signal, so that determine the uneven symbol of each encoder so that add up uneven minimum, so that produce each unbalanced signal of the uneven symbol of definite like this expression and be added to encoder according to accumulative total imbalance and its identification of exporting unbalanced encoder.