CN104952707A - TiN composite hard mask, mask for forming interconnection layer structure and manufacturing method of interconnection layer - Google Patents
TiN composite hard mask, mask for forming interconnection layer structure and manufacturing method of interconnection layer Download PDFInfo
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Abstract
The present application discloses a TiN composite hard mask, a mask for forming an interconnection layer structure and a manufacturing method of an interconnection layer. The TiN composite hard mask comprises at least one group of mask components, and each of the mask components comprises a first mask layer close to the surface of a device to be etched and a second mask layer arranged at one side of the first mask layer far from the device to be etched, and the hardness of the first hard mask layer is lower than the hardness of the second hard mask layer. Through arranging a titanium nitride layer on the upper side, the hardness of the TiN composite hard mask is raised, thus the protection of a semiconductor device in the etching process is facilitated, at the same time the layer thickness of TiN is reduced, the quantity of TiN debris in polishing is reduced, and thus TiN residues are reduced.
Description
Technical field
The application relates to semiconductor integrated circuit manufacture technology field, in particular to the hard mask of a kind of TiN compound, for the formation of the mask of interconnect layer structure and the manufacture method of interconnection layer.
Background technology
In the manufacturing process of semiconductor device, usually can form patterned hard mask on a semiconductor substrate, the pattern etching semiconductor substrate then along hard mask forms required semiconductor functional areas, such as groove or through hole etc., finally removes hard mask.At present, the most frequently used hard mask material is TiN.TiN, because having compact structure, hardness advantages of higher, makes in etching process, etch ion and can not pass TiN, and then can effectively protect semiconductor device, avoid semiconductor device to be damaged.
At present, the technique removing the hard mask of TiN mainly adopts chemico-mechanical polishing.So-called chemico-mechanical polishing is on the basis of mechanical polishing, adds chemical addition agent to reach the effect strengthening polishing at wanted polished surface.When carrying out CMP (Chemical Mechanical Polishing) process process to the hard mask of TiN, because TiN hardness is higher, making its processing characteristics poor, easily on burnishing surface, producing space.Meanwhile, when carrying out CMP (Chemical Mechanical Polishing) process process to the hard mask of TiN, the TiN chip produced can be filled in the space on burnishing surface and cannot wash away by polished solution, makes to produce TiN residue on the semiconductor device formed, and then affects the stability of semiconductor device.
In the manufacturing process of interconnection layer, TiN residue can be produced on interconnection layer equally.The making step of interconnection layer comprises: on connected medium layer, form oxide mask and the hard mask of TiN as mask, then etching runs through dielectric layer and mask formation through hole, form metal preparation layers in through-holes again, finally adopt the mask on chemico-mechanical polishing removal dielectric layer and metal preparation layers to form metal level.Carrying out in the process of chemico-mechanical polishing to mask and metal preparation layers, part TiN can remain on formed interconnection layer, as shown in Figure 1, figure 1 illustrates a kind of SEM photo of the existing interconnection layer using the hard mask of TiN as mask fabrication, obviously can find out the TiN residue (as shown in fig. ia) produced on the burnishing surface of interconnection layer in the drawings, the existence of these TiN residues can affect the stability of interconnection layer.
Summary of the invention
The application aims to provide the hard mask of a kind of TiN compound, for the formation of the mask of interconnect layer structure and the manufacture method of interconnection layer, to solve the problem that easily there is TiN residue in semiconductor device.
To achieve these goals, this application provides the hard mask of a kind of TiN compound, the hard mask of this TiN compound comprises at least one group of mask assembly, and wherein mask assembly comprises: the first mask layer, arranges near device surface to be etched; Second mask layer, is arranged on the side of the first mask layer away from device to be etched; Second mask layer is titanium nitride layer, and the hardness of the first mask layer is lower than the hardness of the second hard mask layer.
Further, in the above-mentioned hard mask of TiN compound, the hard mask of this TiN compound comprises 2 ~ 4 groups of mask assemblies.
Further, in the above-mentioned hard mask of TiN compound, in each mask assembly, the aspect ratio of the first mask layer and the second mask layer is 1:0.5 ~ 2.
Further, in the above-mentioned hard mask of TiN compound, in different group mask assembly, the material of the first mask layer is identical or not identical.
Further, in the above-mentioned hard mask of TiN compound, each first mask layer is for containing silicon dielectric layer.
Further, in the above-mentioned hard mask of TiN compound, each first mask layer is selected from SiO
2, SiOC, SiON or SiCN.
Present invention also provides a kind of mask for the formation of interconnect layer structure, this mask comprises the hard mask of TiN compound being set in turn in oxide mask on connected medium layer and the application and providing.
Further, in above-mentioned mask, oxide mask is selected from black diamond, SiOC and SiO
2in any one or more.
Further, in above-mentioned mask, oxide mask comprises towards away from the black diamond that connected medium layer direction sets gradually and SiO
2.
Further, in above-mentioned mask, mask also comprises and is arranged on the protective layer of the hard mask of TiN compound away from connected medium layer side, and preferred protective layer is SiO
2.
Present invention also provides a kind of manufacture method of interconnection layer, be included on semiconductor substrate and form connected medium layer and mask successively, etching runs through mask and connected medium layer forms through hole, fill in through hole and form metal preparation layers, and remove the mask and metal preparation layers formation metal level that are positioned on connected medium layer, the mask forming the application and provide wherein is provided in the step of mask.
The technical scheme that theres is provided of application the application, employs titanium nitride layer and the hardness another kind of material layer lower than titanium nitride layer simultaneously.By titanium nitride layer being arranged on top, to improve the hardness of the hard mask of TiN compound, and then be conducive in etching process for semiconductor device provides protection, simultaneously by reducing the thickness of TiN, the quantity of TiN fragment during minimizing polishing, and then reduce TiN residue.Simultaneously, by adopting on the surface of device to be etched the material layer that hardness is lower, improve the processing characteristics of the hard mask of TiN compound, and then when polishing, decrease quantity and the area in space on burnishing surface left after the hard mask of polishing TiN compound, and then decrease on semiconductor device and produce TiN residue, improve the stability of semiconductor device.
Accompanying drawing explanation
The Figure of description forming a application's part is used to provide further understanding of the present application, and the schematic description and description of the application, for explaining the application, does not form the improper restriction to the application.In the accompanying drawings:
Fig. 1 shows the SEM photo of existing interconnection layer;
Fig. 2 shows the cross-sectional view of the hard mask that the application's execution mode provides;
Fig. 3 shows the cross-sectional view of a kind of mask for the formation of interconnect layer structure that the application's execution mode provides; And
Fig. 4 shows another kind that the application's execution mode the provides cross-sectional view for the formation of the mask of interconnect layer structure.
Embodiment
It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.The application is described in detail below in conjunction with embodiment.
It should be noted that used term is only to describe embodiment here, and be not intended to the illustrative embodiments of restricted root according to the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to comprise plural form, in addition, it is to be further understood that, when use belongs to " comprising " and/or " comprising " in this manual, it indicates existing characteristics, step, operation, device, assembly and/or their combination.
For convenience of description, here can usage space relative terms, as " ... on ", " in ... top ", " at ... upper surface ", " above " etc., be used for the spatial relation described as a device shown in the figure or feature and other devices or feature.Should be understood that, space relative terms is intended to comprise the different azimuth in use or operation except the described in the drawings orientation of device.Such as, " in other devices or structure below " or " under other devices or structure " will be positioned as after if the device in accompanying drawing is squeezed, being then described as the device of " above other devices or structure " or " on other devices or structure ".Thus, exemplary term " in ... top " can comprise " in ... top " and " in ... below " two kinds of orientation.This device also can other different modes location (90-degree rotation or be in other orientation), and relatively describe space used here and make respective explanations.
As what introduce in background technology, there is the problem of hard mask residue in the semiconductor device.Present inventor studies for the problems referred to above, provides the hard mask of a kind of TiN compound.As shown in Figure 2, the hard mask 100 of this TiN compound comprises at least one group of mask assembly 110, and mask assembly 110 comprises: the first mask layer 111 and the second mask layer 112.First mask layer 111 is arranged near device surface to be etched; Second mask layer 112 is arranged on the side away from device to be etched of the first mask layer 111, and the second mask layer 112 is titanium nitride layer, and the hardness of the first mask layer 111 is lower than the hardness of the second hard mask layer 112.
In the hard mask of this TiN compound that the application provides, employ titanium nitride layer and the hardness another kind of material layer lower than titanium nitride layer simultaneously.By titanium nitride layer being arranged on top, to improve the hardness of the hard mask of TiN compound, and then be conducive in etching process for semiconductor device provides protection; simultaneously by reducing the thickness of TiN; and then when reducing polishing, the quantity of TiN fragment, and then reduce TiN residue.Simultaneously, by adopting on the surface of device to be etched the material layer that hardness is lower, improve the processing characteristics of the hard mask of TiN compound, and then when polishing, decrease quantity and the area in space on burnishing surface left after the hard mask of polishing TiN compound, and then decrease on semiconductor device and produce TiN residue, improve the stability of semiconductor device.
In the hard mask 100 of above-mentioned TiN compound, the quantity of mask assembly 110 can be one or more groups, and those skilled in the art can according to the quantity of actual process requirements set mask assembly 110.In a preferred embodiment, the hard mask 100 of this TiN compound comprises 2 ~ 4 groups of mask assemblies 110.When the hard mask 100 of TiN compound comprises 2 ~ 4 groups of mask assemblies 110, the TiN layer arranged by layering, be ensure that the hardness of the hard mask 100 of TiN compound, and then is conducive to for semiconductor device provides protection.Simultaneously, when the height of the hard mask of TiN compound 100 is identical, the group number of mask assembly 110 is more, and the height of every layer of TiN is thinner, in this case, TiN layer is more easily removed, and when removing TiN layer, the TiN fragment produced more disperses, be easy to remove, and then be conducive to reducing the TiN residue produced on the semiconductor device, improve the stability of semiconductor device.But along with the increase of the group number of mask assembly 110, preparation technology also can relative complex, in order to simplify preparation technology, preferred 2 ~ 4 groups of mask assemblies 110 in this application.
In each mask assembly 110, those skilled in the art equally can according to the aspect ratio of actual process requirements set first mask layer 111 and the second mask layer 112.In a preferred embodiment, the aspect ratio of the first mask layer 111 and the second mask layer 112 is 1:0.5 ~ 2.Adopt the mask assembly 110 of above-mentioned aspect ratio to be conducive to making the hardness of the hard mask 100 of TiN compound and processing characteristics reach one to balance; and then while being conducive to providing protection to semiconductor device; the TiN residue after reducing polishing, semiconductor device produced, improves the stability of semiconductor device.Above-mentioned first mask layer 111 can be siliceous dielectric material common in this area.Preferably, the first mask layer 111 is SiO
2, SiOC, SiON or SiCN.It should be noted that, in difference group mask assembly 110, the material of the first mask layer 111 can be identical, also can not be identical.
Present invention also provides a kind of firmly covering for the formation of interconnect layer structure.As shown in Figure 3, this mask comprises and is set in turn in oxide mask 200 on connected medium layer and the hard mask 100 of TiN compound, wherein the hard mask 100 of TiN compound that provides for the application of the hard mask of TiN compound 100.The interconnection layer adopting this mask to be formed can not produce TiN residue, and then improve the stability of interconnection layer.
Above-mentioned oxide mask 200 can be the common oxide mask material in this area.Preferably, oxide mask 200 is selected from black diamond, SiOC and SiO
2in any one or more.Oxide mask 200 can be one or more layers, and when oxide mask 200 is multilayer, in a kind of preferred implementation, oxide mask 200 is included in black diamond away from connected medium layer direction sets gradually and SiO
2.It should be noted that as shown in Figure 4, this mask can also comprise the protective layer 300 away from connected medium layer side being arranged on the hard mask 100 of TiN compound, and this protective layer 300 is preferably SiO
2.
Simultaneously, present invention also provides a kind of manufacture method of interconnection layer, be included on semiconductor substrate and form connected medium layer and mask successively, etching runs through mask and connected medium layer forms through hole, fill in through hole and form metal preparation layers, and be positioned at and remove mask on connected medium layer and metal preparation layers forms metal level, the wherein mask that provides for the application of mask.The interconnection layer adopting this manufacture method to be formed can not produce TiN residue, and then improve the stability of interconnection layer.
The material of above-mentioned semiconductor substrate can be monocrystalline silicon (Si), monocrystalline germanium (Ge), SiGe (GeSi) or carbonization SiC), also can be silicon-on-insulator (SOI), germanium on insulator (GOI), or can also be the III-V such as other material, such as 6 GaAs.Above-mentioned semiconductor substrate at least forms a kind of structure, such as transistor, diode, capacitor, shallow ditch groove structure or interconnection layer etc.Above-mentioned connected medium layer can be Low-K material, such as SiO
2or SiCOH, the technique forming connected medium layer can be chemical vapour deposition (CVD), sputtering etc.
Above-mentioned mask comprises oxide mask 200 and the hard mask 100 of TiN compound.Wherein oxide mask 200 can be the common oxide mask material in this area, is preferably black diamond, SiOC and SiO
2in any one or more, the technique forming oxide mask 200 can be chemical vapour deposition (CVD), sputtering or thermal oxidation etc.The hard mask 100 of TiN compound that the hard mask of TiN compound 100 provides for the application, comprise the first mask layer 111 and the second mask layer 112 of stacked setting, wherein the second mask layer is titanium nitride layer, and the first mask layer 111 can be the common siliceous dielectric material in this area, is preferably SiO
2, SiOC, SiON or SiCN.
Forming above-mentioned first mask layer 111 and titanium nitride technique can be chemical vapour deposition (CVD), sputtering etc.When adopting chemical vapour deposition (CVD) to form TiN, in a kind of optional scheme, with TiCl
4and NH
3for reacting gas, TiCl
4flow be 300 ~ 500sccm, NH
3flow be 150 ~ 250sccm, the pressure in reative cell is 5 ~ 10torr, and depositing temperature is 500 ~ 650 DEG C, and sedimentation time is 20 ~ 90 seconds.
The technique etching above-mentioned mask and connected medium layer is dry etching.In a kind of optional scheme, the process conditions of dry etching are: etching gas is CF
4and CHF
3, sputtering power is 400 ~ 1000 watts, and etching temperature is 25 ~ 60 DEG C, and etch period is 30 ~ 360 seconds.
Above-mentioned metal preparation layers can be metal material conventional in prior art, and such as Cu, Au or Sn are preferably Cu, and the technique forming above-mentioned metal preparation layers includes but not limited to adopt plating or chemical vapour deposition (CVD).When adopting electroplating technology to form Cu, a kind of Alternate embodiments is: with Cu
2p
2o
7for the Cu source in electroplate liquid, the current density in electroplating process is 1 ~ 5A/dm
2, the temperature of electroplate liquid is 5 ~ 80 DEG C.
Mask on removal connected medium layer and the technique of metal preparation layers are chemico-mechanical polishing.The Si0 that the polishing fluid that chemico-mechanical polishing adopts can be well known to those skilled in the art
2polishing fluid can be such as the polishing fluid of the various models of market sale.In a kind of optional scheme, the process conditions of chemico-mechanical polishing are: on grinding head, applied pressure is 200 ~ 300g/cm
2, the rotating speed of grinding head is 50 ~ 100r/min, the flow velocity 100 ~ 300ml/min of polishing fluid, and polish temperature is 20 ~ 45 DEG C, and polishing time is 20 ~ 120 seconds.
The manufacture method that the application provides interconnection layer is further illustrated below in conjunction with embodiment.But these illustrative embodiments can have multiple different form to implement, and should not be interpreted as being only limited to execution mode set forth herein.Should be understood that, provide these execution modes be in order to make the application open thorough and complete, and the design of these illustrative embodiments is fully conveyed to those of ordinary skill in the art.
Embodiment 1
Present embodiments provide a kind of manufacture method of interconnection layer, comprise the following steps:
Form SiO successively on a si substrate
2dielectric layer, SiOC mask layer and by one group of SiO
2the hard mask of TiN compound of/TiN composition, wherein, SiO in the hard mask of TiN compound
2height be 150
the height of TiN is 150
the reaction condition forming TiN is: with TiCl
4and NH
3for reacting gas, TiCl
4flow be 400sccm, NH
3flow be 300sccm, the pressure in reative cell is 5torr, and depositing temperature is 500 DEG C, and sedimentation time is 60 seconds;
The hard mask of etching TiN compound, SiOC mask layer and SiO
2dielectric layer forms through hole, and the process conditions wherein etched are: etching gas is CF
4and CHF
3, sputtering power is 1000 watts, and etching temperature is 60 DEG C, and etch period is 70 seconds;
Form Cu preparation layers in through-holes by electroplating technology, wherein electroplating technique condition is: with Cu
2p
2o
7for the Cu source in electroplate liquid, the current density in electroplating process is 3A/dm
2, the temperature of electroplate liquid is 65 DEG C;
Chemico-mechanical polishing is adopted to remove SiO
2the hard mask of TiN compound, SiOC mask layer and Cu preparation layers on dielectric layer, with at SiO
2form Cu layer in dielectric layer, the process conditions of wherein chemico-mechanical polishing are: on grinding head, applied pressure is 220g/cm
2, the rotating speed of grinding head is 85r/min, the flow velocity 260ml/min of polishing fluid, and polish temperature is 35 DEG C, and polishing time is 35 seconds.
Embodiment 2
Present embodiments provide a kind of manufacture method of interconnection layer, comprise the following steps:
Form SiO successively on a si substrate
2dielectric layer, SiOC mask layer and the hard mask of TiN compound be made up of 2 groups of SiON/TiN, wherein, often organize the height 40 of SiON in SiON/TiN
the height 80 of TiN
forming the reaction condition often organizing TiN is: with TiCl
4and NH
3for reacting gas, TiCl
4flow be 400sccm, NH
3flow be 300sccm, the pressure in reative cell is 5torr, and depositing temperature is 500 DEG C, and sedimentation time is 30 seconds;
The hard mask of etching TiN compound, SiOC mask layer and SiO
2dielectric layer forms through hole, forms Cu preparation layers in through-holes by electroplating technology, and adopts chemico-mechanical polishing to remove SiO
2the hard mask of TiN compound on dielectric layer, SiOC mask layer are identical with embodiment 1 with the step of Cu preparation layers.
Embodiment 3
Present embodiments provide a kind of manufacture method of interconnection layer, comprise the following steps:
Form SiO successively on a si substrate
2dielectric layer, SiOC mask layer and the hard mask of TiN compound be made up of 2 groups of SiOC/TiN, wherein, often organize the height 40 of SiOC in SiOC/TiN
the height 80 of TiN
forming the reaction condition often organizing TiN is: with TiCl
4and NH
3for reacting gas, TiCl
4flow be 400sccm, NH
3flow be 300sccm, the pressure in reative cell is 5torr, and depositing temperature is 500 DEG C, and sedimentation time is 30 seconds;
The hard mask of etching TiN compound, SiOC mask layer and SiO
2dielectric layer forms through hole, forms Cu preparation layers in through-holes by electroplating technology, and adopts chemico-mechanical polishing to remove SiO
2the hard mask of TiN compound on dielectric layer, SiOC mask layer are identical with embodiment 1 with the step of Cu preparation layers.
Embodiment 4
Present embodiments provide a kind of manufacture method of interconnection layer, comprise the following steps: form SiO successively on a si substrate
2dielectric layer, SiOC mask layer and the hard mask of TiN compound be made up of 4 groups of SiCN/TiN, wherein, often organize the height 60 of SiCN in SiCN/TiN
the height 30 of TiN
forming the reaction condition often organizing TiN is: with TiCl
4and NH
3for reacting gas, TiCl
4flow be 400sccm, NH
3flow be 300sccm, the pressure in reative cell is 5torr, and depositing temperature is 500 DEG C, and sedimentation time is 15 seconds;
The hard mask of etching TiN compound, SiOC mask layer and SiO
2dielectric layer forms through hole, forms Cu preparation layers in through-holes by electroplating technology, and adopts chemico-mechanical polishing to remove SiO
2the hard mask of TiN compound on dielectric layer, SiOC mask layer are identical with embodiment 1 with the step of Cu preparation layers.
Comparative example 1
This comparative example provides a kind of manufacture method of interconnection layer, comprises the following steps:
Form SiO successively on a si substrate
2dielectric layer, SiOC mask layer and 300
the hard mask of TiN, the reaction condition wherein forming TiN is: with TiCl
4and NH
3for reacting gas, TiCl
4flow be 400sccm, NH
3flow be 300sccm, the pressure in reative cell is 5torr, and depositing temperature is 500 DEG C, and sedimentation time is 100 seconds;
Etch hard mask, SiOC mask layer and SiO
2dielectric layer forms through hole, forms Cu preparation layers in through-holes by electroplating technology, and adopts chemico-mechanical polishing to remove SiO
2hard mask on dielectric layer, SiOC mask layer are identical with embodiment 1 with the step of Cu preparation layers.
Test: the leakage current in the interconnection layer obtained by testing example 1 to 4 and comparative example 1, to characterize isolation effect and the reliability of interconnection layer.Method of testing is: on interconnection layer, apply test voltage, and test voltage, from 0V to 30V, increases 1V at every turn; Measure the leakage current between interconnection layer simultaneously, and average.Test result asks for an interview table 1.
Table 1.
| Leakage current (mean value/A) | |
| Embodiment 1 | 3.5×10 -9 |
| Embodiment 2 | 3.2×10 -9 |
| Embodiment 3 | 3.3×10 -9 |
| Embodiment 4 | 2.7×10 -9 |
| Comparative example 1 | 7.8×10 -8 |
As can be seen from Table 1, the leakage current of interconnection layer that obtains of embodiment 1 to 4 is 2.7 × 10
-9~ 3.5 × 10
-9between, and the leakage current of the interconnection layer that comparative example 1 obtains is 7.8 × 10
-8a.Visible, the stability of the interconnection layer that the stability of the interconnection layer that embodiment 1 to 4 obtains obtains apparently higher than comparative example 1.
As can be seen from the above description, the application's the above embodiments achieve following technique effect: the application employs titanium nitride layer and the hardness another kind of material layer lower than titanium nitride layer as the hard mask of compound simultaneously.By titanium nitride layer being arranged on top, to improve the hardness of the hard mask of TiN compound, and then be conducive in etching process for semiconductor device provides protection, simultaneously by reducing the thickness of TiN, the quantity of TiN fragment during minimizing polishing, and then reduce TiN residue.Simultaneously, by adopting on the surface of device to be etched the material layer that hardness is lower, improve the processing characteristics of the hard mask of TiN compound, and then when polishing, decrease quantity and the area in space on burnishing surface left after the hard mask of polishing TiN compound, and then decrease the TiN residue that semiconductor device produces, improve the stability of semiconductor device.
The foregoing is only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.
Claims (11)
1. the hard mask of TiN compound, is characterized in that, the hard mask of described TiN compound comprises at least one group of mask assembly, and described mask assembly comprises:
First mask layer, is arranged near device surface to be etched;
Second mask layer, is arranged on the side of described first mask layer away from described device to be etched;
Described second mask layer is titanium nitride layer, and the hardness of described first mask layer is lower than the hardness of the described second hard mask layer.
2. the hard mask of compound according to claim 1, is characterized in that, the hard mask of described TiN compound comprises mask assembly described in 2 ~ 4 groups.
3. the hard mask of compound according to claim 1, is characterized in that, in each described mask assembly, the aspect ratio of the first mask layer and the second mask layer is 1:0.5 ~ 2.
4. the hard mask of compound according to claim 3, is characterized in that, in the described mask assembly of different group, the material of described first mask layer is identical or not identical.
5. the hard mask of compound according to any one of claim 1 to 4, is characterized in that, each described first mask layer is for containing silicon dielectric layer.
6. the hard mask of compound according to claim 5, is characterized in that, each described first mask layer is selected from SiO
2, SiOC, SiON or SiCN.
7. for the formation of a mask for interconnect layer structure, it is characterized in that, described mask comprises and is set in turn in the oxide mask on connected medium layer and the hard mask of TiN compound according to any one of claim 1 to 6.
8. mask according to claim 7, is characterized in that, described oxide mask is selected from black diamond, SiOC and SiO
2in one or more.
9. mask according to claim 8, is characterized in that, described oxide mask comprises towards away from the black diamond that described connected medium layer direction sets gradually and SiO
2.
10. mask according to claim 8, is characterized in that, described mask also comprises and is arranged on the protective layer of the hard mask of described TiN compound away from described connected medium layer side, and preferred described protective layer is SiO
2.
The manufacture method of 11. 1 kinds of interconnection layers, be included on semiconductor substrate and form connected medium layer and mask successively, etching runs through described mask and connected medium layer forms through hole, fill in described through hole and form metal preparation layers, and remove the mask and metal preparation layers formation metal level that are positioned on described connected medium layer, it is characterized in that, form in the step of described mask the mask formed according to any one of claim 7 to 10.
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|---|---|---|---|
| CN201410127662.5A CN104952707B (en) | 2014-03-31 | 2014-03-31 | The compound hard masks of TiN are used to form the hard of interconnection layer structure and cover and the production method of interconnection layer |
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|---|---|---|---|
| CN201410127662.5A CN104952707B (en) | 2014-03-31 | 2014-03-31 | The compound hard masks of TiN are used to form the hard of interconnection layer structure and cover and the production method of interconnection layer |
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|---|---|
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| CN104952707B CN104952707B (en) | 2018-07-20 |
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| CN102779780A (en) * | 2012-07-25 | 2012-11-14 | 上海华力微电子有限公司 | Method for forming non-load-effect large size groove |
| CN103377886A (en) * | 2012-04-13 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Hard mask layer structure, manufacturing method thereof and manufacturing method of semiconductor device |
| CN103489822A (en) * | 2012-06-11 | 2014-01-01 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN103515228A (en) * | 2012-06-18 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
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| CN103377886A (en) * | 2012-04-13 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Hard mask layer structure, manufacturing method thereof and manufacturing method of semiconductor device |
| CN103489822A (en) * | 2012-06-11 | 2014-01-01 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN103515228A (en) * | 2012-06-18 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
| CN102779780A (en) * | 2012-07-25 | 2012-11-14 | 上海华力微电子有限公司 | Method for forming non-load-effect large size groove |
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