CN104951410B - The access method and device of a kind of chip information - Google Patents
The access method and device of a kind of chip information Download PDFInfo
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- CN104951410B CN104951410B CN201410119967.1A CN201410119967A CN104951410B CN 104951410 B CN104951410 B CN 104951410B CN 201410119967 A CN201410119967 A CN 201410119967A CN 104951410 B CN104951410 B CN 104951410B
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Abstract
The invention discloses a kind of access method of chip information and device, to solve the problems, such as that information is capped or wipes in chip.Described method includes：Independent memory space is configured in the chips in advance, and at least two-level memory region is set in the independent memory space；The write instruction to independent memory space write-in data is received, the level identification of user is obtained from said write instruction；The independent memory space is searched using the level identification of the user, determines the storage region of corresponding level；The chip production information obtained in being instructed from said write is written in the storage region of the corresponding level.Ensure that user is only capable of carrying out the storage region of its affiliated rank the write-in of data, prevent the production information of chip capped or erasing, it is ensured that the integrality of chip production information, can be when chip breaks down quickly, accurately positioned.
Description
Technical field
The present invention relates to communication technical field, access method and a kind of chip information more particularly to a kind of chip information
Access mechanism.
Background technology
In the production process of the hardware devices such as chip, production information such as date of production of chip etc. would generally be recorded in core
In piece.But actually because chip is probably just to be finally completed by repeatedly generation, and it may all enter row information in generating every time
Record, therefore the region that its production information is recorded in chip may repeatedly be accessed.
The region of production information is recorded in chip during multiple access, producing that recorded message just has before can
It can be capped or wipe, cause information imperfect.And then cause user can not obtain complete information note when consulting information
Record, particularly when chip breaks down, can not quickly, accurately be positioned.
The content of the invention
Technical problem to be solved of the embodiment of the present invention is to provide a kind of access method of chip information, to solve chip
The problem of middle information is capped or wipes.
Accordingly, the embodiment of the present invention additionally provides a kind of access mechanism of chip information, to ensure the above method
Realize and apply.
In order to solve the above problems, the invention discloses a kind of access method of chip information, including：In advance in the chips
Independent memory space is configured, and at least two-level memory region is set in the independent memory space；Receive and independently deposited to described
The write instruction of space write-in data is stored up, the level identification of user is obtained from said write instruction；Using the level of the user
Independent memory space described in other identifier lookup, determine the storage region of corresponding level；The core obtained in being instructed from said write
Piece production information is written in the storage region of the corresponding level.
Optionally, configure independent memory space in the chips in advance, and at least two are set in the independent memory space
After level storage region, in addition to：The level identification of storage regions at different levels and owning user in the independent memory space is set
Corresponding relation；Access rights and storage of the access instruction of the user to the independent memory space are set, wherein described
Access instruction includes reading instruction and write instruction.
Optionally, the level identification using the user searches the independent memory space, determines corresponding level
Storage region, including：From the corresponding relation of the affiliated rank of identification marking and storage region of each user, search the user's
Level identification corresponds to the rank of storage region.
Optionally, the chip production information obtained in being instructed from said write is written to the memory block of the corresponding level
In domain, including：Obtain the chip production information carried in said write instruction；Said write instruction is searched to the separate storage
The access rights of the access rights in space, wherein write instruction are that the storage region of the level identification corresponding level of user is carried out
Write operation；The chip production information is write to the storage region of the corresponding level according to the access rights of write instruction.
Optionally, in addition to：Receive the reading instruction that data are read to the independent memory space；Refer to according to the reading
User class mark in order determines access rights of the user to the independent memory space；According to the access right for reading instruction
Limit, the information in the storage region for the level identification corresponding level for reading the user, and/or, read higher than the user's
Information in the storage region of level identification corresponding level.
Accordingly, the invention also discloses a kind of access mechanism of chip information, including：Setup module, for existing in advance
Independent memory space is configured in chip, and at least two-level memory region is set in the independent memory space；Receiving module, use
In receiving the write instruction to independent memory space write-in data, the rank mark of user is obtained from said write instruction
Know；Searching modul, for searching the independent memory space using the level identification of the user, determine the storage of corresponding level
Region；Writing module, the chip production information for being obtained in being instructed from said write are written to depositing for the corresponding level
In storage area domain.
Optionally, the setup module, it is additionally operable to set storage regions at different levels and affiliated use in the independent memory space
The corresponding relation of the level identification at family；The access instruction of the user is set to the access rights of the independent memory space and deposited
Storage, wherein the access instruction includes reading instruction and write instruction.
Optionally, the searching modul, closed for the identification marking from each user and the corresponding of the affiliated rank of storage region
In system, the level identification for searching the user corresponds to the rank of storage region.
Optionally, writing module, including：Acquisition submodule, for obtaining the chip production carried in said write instruction
Information；Submodule is searched, for searching access rights of the said write instruction to the independent memory space, wherein write instruction
Access rights be that write operation is carried out to the storage region of the level identification corresponding level of user；Write submodule, for by
The chip production information is write to the storage region of the corresponding level according to the access rights of write instruction.
Optionally, the receiving module, it is additionally operable to receive the reading instruction for reading data to the independent memory space；Institute
Searching modul is stated, is additionally operable to determine the user to the independent memory space according to the user class mark read in instruction
Access rights；Described device also includes：Read module, for according to the access rights for reading instruction, reading the user
Level identification corresponding level storage region in information, and/or, read higher than the user level identification corresponding level
Storage region in information.
Compared with prior art, the embodiment of the present invention includes advantages below：
Configuration includes the independent memory space at least two-level memory region in the chips in advance, is write to independent memory space
Enter to obtain the level identification of user in the write instruction of data, so that it is determined that the storage region of user's corresponding level, corresponding at this
The storage region write-in chip production information of rank, so that it is guaranteed that user is only capable of carrying out data to the storage region of its affiliated rank
Write-in, prevent the production information of chip capped or erasing, it is ensured that the integrality of chip production information, can go out in chip
It is quick during existing failure, accurately positioned.
Brief description of the drawings
Fig. 1 is a kind of step flow chart of the access method embodiment of chip information of the present invention；
Fig. 2 is a kind of step flow chart of the access method alternative embodiment of chip information of the present invention；
Fig. 3 is a kind of structured flowchart of the access mechanism embodiment of chip information of the present invention
Fig. 4 is a kind of structured flowchart of the access mechanism alternative embodiment of chip information of the present invention.
Embodiment
In order to facilitate the understanding of the purposes, features and advantages of the present invention, it is below in conjunction with the accompanying drawings and specific real
Applying mode, the present invention is further detailed explanation.
The embodiment of the present invention provides a kind of access method of chip information, can configure in the chips in advance including at least two
The independent memory space of level storage region, from the rank mark that user is obtained into the write instruction of independent memory space write-in data
Know, so that it is determined that the storage region of user's corresponding level, chip production information is write in the storage region of the corresponding level, so as to
Ensure that user is only capable of carrying out the storage region of its affiliated rank the write-in of data, prevent that the production information of chip is capped or wipes
Remove, it is ensured that the integrality of chip production information, can quickly, accurately be positioned when chip breaks down.
Embodiment one：
Reference picture 1, a kind of step flow chart of the access method embodiment of chip information of the present invention is shown, specifically may be used
To comprise the following steps：
Step 101, configure independent memory space in the chips in advance, and at least two are set in the independent memory space
Level storage region.
It is empty to configure separate storage in order to prevent that production information is capped in chip development or distorts in the chips for the present embodiment
Between, the independent memory space refers to a part of storage region independent in chip-stored space, for according to setting
Access instruction reads and writes operation to the independent memory space.
Due to the process such as chip can be produced by multiple users, be developed, producer such as chip, by chip manufacturing into certain
The manufacturer of one equipment, personnel of the interior exploitation program of chip etc., therefore depositing at least two ranks is set in the separate space
Storage area domain.The information that the storage region of each rank corresponds to the user of appropriate level is stored.Wherein, the use of each rank
The storage region that family is only capable of pair independent memory space corresponding with the user class carries out data write operation, and other class subscribers
The storage region of corresponding independent memory space carries out data read operation.
Step 102, the write instruction to independent memory space write-in data is received, is obtained from said write instruction
The level identification of user.
Write instruction can be sent when user needs and writes data to independent memory space, the write instruction includes knowing
The level identification of other User Priority, and to be written to the chip production information of storage region.
After the write instruction is received, the level identification of user can be obtained from write instruction.Wherein, the level of user
The precedence information for identifying user is not identified, determines the storage region of its corresponding independent memory space.
Step 103, the independent memory space is searched using the level identification of the user, determines the storage of corresponding level
Region.
Step 104, the chip production information obtained in being instructed from said write is written to the storage of the corresponding level
In region.
Level identification according to user determines the priority of user, empty in separate storage according to the priority lookup user
Between middle corresponding level storage region.Chip production information is obtained from write instruction, believes chip production according to write instruction
In breath write-in memory space in the storage region of user's corresponding level.
In summary, configuration includes the independent memory space at least two-level memory region in the chips in advance, to independence
The level identification of user is obtained in the write instruction of memory space write-in data, so that it is determined that the memory block of user's corresponding level
Domain, chip production information is write in the storage region of the corresponding level, so that it is guaranteed that user is only capable of the storage to its affiliated rank
Region carries out the write-in of data, prevents that the production information of chip is capped or wipes, it is ensured that the integrality of chip production information, energy
It is enough quickly, accurately to be positioned when chip breaks down.
Embodiment two：
On the basis of above-described embodiment, read and write access method of the present embodiment continuing with chip information.
Reference picture 2, show a kind of step flow chart of the access method alternative embodiment of chip information of the present invention, tool
Body may include steps of：
Step 201, configure independent memory space in the chips in advance, and at least two are set in the independent memory space
Level storage region.
Step 202, the correspondence of the level identification of storage regions at different levels and owning user in the independent memory space is set
Relation.
Step 203, access rights and storage of the access instruction of the user to the independent memory space are set.
In the present embodiment, the storage region in independent memory space has priority, so as to in independent memory space
Storage region carries out classification storage, in order to which the rank of the storage region accessed user makes a distinction, can independently be deposited described
The storage region of the level identification corresponding level of each user in space is stored up, that is, memory blocks at different levels in the independent memory space are set
The corresponding relation of the level identification of domain and user, the storage region of the corresponding rank of each level identification, such as the level of user
First order level 0 is not identified as, then corresponds to the ID of first order storage region level 0, the level identification of user is the second level
Level 1, then the ID of second level storage region level 1 are corresponded to, the like.
The level identification is set to correspond to access rights of the access instruction to the independent memory space of user again.Wherein institute
Stating read write command includes reading instruction and write instruction.Access rights refer to the separate storage that the access instruction can be accessed
Storage region in space.
Wherein, the access rights of write instruction are to be only capable of writing the storage region of this rank, that is, are only capable of to the use
The level identification at family corresponds to the write-in that storage region carries out data, and the memory block that rank is more high or low than the rank of the storage region
Domain can not write data.
The access claim for reading instruction is the information in reading this rank storage region, and reads and stored higher than the rank
Information in region.
Step 204, the access instruction to be conducted interviews to the independent memory space and detection are received.
The configuration of chip separate storage region and the access consideration of the separate storage region is completed, in chip production, is opened
During hair, independent memory space is conducted interviews using access instruction, then detects the access instruction.
Step 205 is performed when the access instruction is write instruction；When access instruction performs step to read during instruction
209。
Step 205, from the corresponding relation of the affiliated rank of identification marking and storage region of each user, the user is searched
Level identification correspond to the rank of storage region.
The level identification of user is obtained from said write instruction, then searches the level according to the corresponding relation pre-set
Not Biao Shi corresponding to storage region rank, that is, determine the user carry out data write-in corresponding level storage region.
Step 206, the chip production information carried in said write instruction is obtained.
Step 207, access rights of the said write instruction to the independent memory space are searched.
Step 208, the chip production information is write into depositing for the corresponding level according to the access rights of write instruction
Storage area domain.
The chip production information that be written in chip is obtained from write instruction, such as date of manufacture, manufacturer, ProductName
The contents such as whether qualified title, product type, product function introduction, product be.The write instruction is searched again to separate storage region
The access rights of access rights, wherein write instruction are to carry out write-in behaviour to the storage region of the level identification corresponding level of user
Make.Therefore the level identification according to user determines the rank of user, and the storage region of corresponding level, by chip production information
Write in the storage region of the rank.
Step 209, determine the user to the independent memory space according to the user class mark read in instruction
Access rights.
Step 210, the access rights instructed according to reading, the memory block of the level identification corresponding level of the user is read
Information in domain, and/or, read the information in the storage region higher than the level identification corresponding level of the user.
When access instruction is reads instruction, the level identification of user is obtained in being instructed from reading, it is true according to level identification
Determine the storage region of corresponding level, and search the access rights for reading instruction.
According to the access rights, the information in the rank storage region is read, or read higher than in the rank storage region
Information, or read information in the rank storage region simultaneously and higher than the information in the rank storage region.
For example, during chip production, qualified products are independently deposited by the write instruction of setting in designated area write-in
Store up the ID of storage region level 0 in space.The ID of level 0 letters are first read using reading instruction before the users of Level 1 production
Breath, it is qualified products to judge the product, and it is correct to deliver, to detection qualified products using write-in after the users of Level 1 production
Instruction writes information in the ID of storage region level 1, but the ID of storage region level 0 information can not be rewritten.
The users of Level 2 first read the ID's and ID of level 1 of storage region level 0 in production using reading instruction
Information, ensure that product higher level user detects qualified products and produced again.It is qualified to detecting after the completion of the users of Level 2 production
Product write production information using write instruction in the ID of storage region level 2, but can not to the ID of storage region level 0 and
The ID of level 1 information is rewritten.
When the system failure occurs for chipset, ID, the level 1 of storage region level 0 is read respectively by reading instruction
Information in ID and the ID of level 2 carries out product history retrospect, determines whether that the mistake in production process causes, Ke Yi great
The big analysis progress for accelerating failure.
It should be noted that for embodiment of the method, in order to be briefly described, therefore it is all expressed as to a series of action group
Close, but those skilled in the art should know, the embodiment of the present invention is not limited by described sequence of movement, because according to
According to the embodiment of the present invention, some steps can use other orders or carry out simultaneously.Secondly, those skilled in the art also should
Know, embodiment described in this description belongs to preferred embodiment, and the involved action not necessarily present invention is implemented
Necessary to example.
Embodiment three：
On the basis of above-described embodiment, the present embodiment additionally provides a kind of access mechanism of chip information.
Reference picture 3, a kind of structured flowchart of the access mechanism embodiment of chip information of the present invention is shown, can specifically be wrapped
Include following module：
Setup module 301, for configuring independent memory space in the chips in advance, and set in the independent memory space
Put at least two-level memory region.
Receiving module 302, the write instruction of data is write to the independent memory space for receiving, is referred to from said write
The level identification of user is obtained in order.
Searching modul 303, for searching the independent memory space using the level identification of the user, determine respective stages
Other storage region.
Writing module 304, the chip production information for being obtained in being instructed from said write are written to the respective stages
In other storage region.
In summary, configuration includes the independent memory space at least two-level memory region in the chips in advance, to independence
The level identification of user is obtained in the write instruction of memory space write-in data, so that it is determined that the memory block of user's corresponding level
Domain, chip production information is write in the storage region of the corresponding level, so that it is guaranteed that user is only capable of the storage to its affiliated rank
Region carries out the write-in of data, prevents that the production information of chip is capped or wipes, it is ensured that the integrality of chip production information, energy
It is enough quickly, accurately to be positioned when chip breaks down.
Reference picture 4, a kind of structured flowchart of the access mechanism alternative embodiment of chip information of the present invention is shown, specifically may be used
With including following module：
In an alternative embodiment of the invention, the setup module 301, it is additionally operable to set in the independent memory space each
The corresponding relation of the level identification of level storage region and owning user；The access instruction of the user is set to the separate storage
The access rights in space and storage, wherein the access instruction includes reading instruction and write instruction.
In an alternative embodiment of the invention, the searching modul 303, for the identification marking from each user and memory block
In the corresponding relation of the affiliated rank in domain, the level identification for searching the user corresponds to the rank of storage region.
In an alternative embodiment of the invention, said write module 304, including：Acquisition submodule 3041, search submodule
3042 and write-in submodule 3043.
Wherein, acquisition submodule 3041, for obtaining the chip production information carried in said write instruction；Search submodule
Block 3042, for searching access right of the said write instruction to the access rights, wherein write instruction of the independent memory space
It is limited to carry out write operation to the storage region of the level identification corresponding level of user；Submodule 3043 is write, for according to writing
The access rights for entering instruction write the chip production information storage region of the corresponding level.
In an alternative embodiment of the invention, the receiving module 302, it is additionally operable to receive and is read to the independent memory space
The reading instruction for evidence of fetching；The searching modul 303, it is additionally operable to determine to be somebody's turn to do according to the user class mark read in instruction
Access rights of the user to the independent memory space.Described device also includes：Read module 305, for referring to according to reading
The access rights of order, the information in the storage region for the level identification corresponding level for reading the user, and/or, reading is higher than
Information in the storage region of the level identification corresponding level of the user.
For device embodiment, because it is substantially similar to embodiment of the method, so description is fairly simple, it is related
Part illustrates referring to the part of embodiment of the method.
Each embodiment in this specification is described by the way of progressive, what each embodiment stressed be with
The difference of other embodiment, between each embodiment identical similar part mutually referring to.
It should be understood by those skilled in the art that, the embodiment of the embodiment of the present invention can be provided as method, apparatus or calculate
Machine program product.Therefore, the embodiment of the present invention can use complete hardware embodiment, complete software embodiment or combine software and
The form of the embodiment of hardware aspect.Moreover, the embodiment of the present invention can use one or more wherein include computer can
With in the computer-usable storage medium (including but is not limited to magnetic disk storage, CD-ROM, optical memory etc.) of program code
The form of the computer program product of implementation.
The embodiment of the present invention is with reference to method according to embodiments of the present invention, terminal device (system) and computer program
The flow chart and/or block diagram of product describes.It should be understood that can be by computer program instructions implementation process figure and/or block diagram
In each flow and/or square frame and the flow in flow chart and/or block diagram and/or the combination of square frame.These can be provided
Computer program instructions are set to all-purpose computer, special-purpose computer, Embedded Processor or other programmable data processing terminals
Standby processor is to produce a machine so that is held by the processor of computer or other programmable data processing terminal equipments
Capable instruction is produced for realizing in one flow of flow chart or multiple flows and/or one square frame of block diagram or multiple square frames
The device for the function of specifying.
These computer program instructions, which may be alternatively stored in, can guide computer or other programmable data processing terminal equipments
In the computer-readable memory to work in a specific way so that the instruction being stored in the computer-readable memory produces bag
The manufacture of command device is included, the command device is realized in one flow of flow chart or multiple flows and/or one side of block diagram
The function of being specified in frame or multiple square frames.
These computer program instructions can be also loaded into computer or other programmable data processing terminal equipments so that
Series of operation steps is performed on computer or other programmable terminal equipments to produce computer implemented processing, so that
The instruction performed on computer or other programmable terminal equipments is provided for realizing in one flow of flow chart or multiple flows
And/or specified in one square frame of block diagram or multiple square frames function the step of.
Although having been described for the preferred embodiment of the embodiment of the present invention, those skilled in the art once know base
This creative concept, then other change and modification can be made to these embodiments.So appended claims are intended to be construed to
Including preferred embodiment and fall into having altered and changing for range of embodiment of the invention.
Finally, it is to be noted that, in this manual, such as first and second or the like relational terms are only used
By an entity or operation with another entity or operate make a distinction, and not necessarily require or imply these entities or
Any this actual relation or order between operation be present.Moreover, term " comprising ", "comprising" or its any other change
Body is intended to including for nonexcludability, so that process, method, article or terminal device including a series of elements are not
Only include those key elements, but also the other element including being not expressly set out, or also include for this process, method,
Article or the intrinsic key element of terminal device.In the absence of more restrictions, limited by sentence "including a ..."
Key element, it is not excluded that also exist in the process including the key element, method, article or terminal device it is other it is identical will
Element.
Access method to a kind of chip information provided by the present invention and a kind of access mechanism of chip information above, enter
Go and be discussed in detail, specific case has been applied in this specification the principle and embodiment of the present invention are set forth, the above
The explanation of embodiment is only intended to help the method and its core concept for understanding the present invention；Meanwhile for the general skill of this area
Art personnel, according to the thought of the present invention, there will be changes in specific embodiments and applications, in summary, this
Description should not be construed as limiting the invention.
Claims (10)
- A kind of 1. access method of chip information, it is characterised in that including：Independent memory space is configured in the chips in advance, and at least two-level memory region is set in the independent memory space；The write instruction to independent memory space write-in data is received, the rank mark of user is obtained from said write instruction Know；The independent memory space is searched using the level identification of the user, determines the storage region of corresponding level；The chip production information obtained in being instructed from said write is written in the storage region of the corresponding level.
- 2. according to the method for claim 1, it is characterised in that independent memory space is configured in the chips in advance, and in institute State after at least two-level memory region is set in independent memory space, in addition to：The corresponding relation of the level identification of storage regions at different levels and owning user in the independent memory space is set；Access rights and storage of the access instruction of the user to the independent memory space are set, wherein the access instruction Including reading instruction and write instruction.
- 3. according to the method for claim 2, it is characterised in that the level identification using the user is searched described only Vertical memory space, the storage region of corresponding level is determined, including：From the corresponding relation of the affiliated rank of level identification and storage region of each user, the level identification pair of the user is searched Answer the rank of storage region.
- 4. according to the method for claim 3, it is characterised in that the chip production information obtained in being instructed from said write It is written in the storage region of the corresponding level, including：Obtain the chip production information carried in said write instruction；Said write instruction is searched to the access rights of the independent memory space, wherein the access rights of write instruction be to The storage region of the level identification corresponding level at family carries out write operation；The chip production information is write to the storage region of the corresponding level according to the access rights of write instruction.
- 5. according to the method for claim 2, it is characterised in that also include：Receive the reading instruction that data are read to the independent memory space；Access rights of the user to the independent memory space are determined according to the user class mark read in instruction；According to the access rights for reading instruction, the information in the storage region for the level identification corresponding level for reading the user, And/or read the information being higher than in the storage region of the level identification corresponding level of the user.
- A kind of 6. access mechanism of chip information, it is characterised in that including：Setup module, for configuring independent memory space in the chips in advance, and set at least in the independent memory space Two-level memory region；Receiving module, the write instruction of data is write to the independent memory space for receiving, obtained from said write instruction Take the level identification at family；Searching modul, for searching the independent memory space using the level identification of the user, determine depositing for corresponding level Storage area domain；Writing module, the chip production information for being obtained in being instructed from said write are written to the storage of the corresponding level In region.
- 7. device according to claim 6, it is characterised in that：The setup module, it is additionally operable to set the level identification of storage regions at different levels and owning user in the independent memory space Corresponding relation；Access rights and storage of the access instruction of the user to the independent memory space are set, wherein described Access instruction includes reading instruction and write instruction.
- 8. device according to claim 7, it is characterised in that：The searching modul, for from the level identification of each user and the corresponding relation of the affiliated rank of storage region, searching institute The level identification for stating user corresponds to the rank of storage region.
- 9. device according to claim 8, it is characterised in that writing module, including：Acquisition submodule, for obtaining the chip production information carried in said write instruction；Submodule is searched, for searching access rights of the said write instruction to the independent memory space, wherein write instruction Access rights be that write operation is carried out to the storage region of the level identification corresponding level of user；Submodule is write, the chip production information is write into the corresponding level for the access rights according to write instruction Storage region.
- 10. device according to claim 7, it is characterised in that：The receiving module, it is additionally operable to receive the reading instruction for reading data to the independent memory space；The searching modul, it is additionally operable to determine that the user independently deposits to described according to the user class mark read in instruction Store up the access rights in space；Described device also includes：Read module, for according to the access rights instructed are read, reading the rank mark of the user Know the information in the storage region of corresponding level, and/or, read the memory block for being higher than the level identification corresponding level of the user Information in domain.
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| CN108628538B (en) * | 2017-03-17 | 2021-06-08 | 北京兆易创新科技股份有限公司 | Data storage method and device in NAND Flash |
| CN108628752B (en) * | 2017-03-17 | 2021-10-01 | 北京兆易创新科技股份有限公司 | Data storage method and device |
| CN110598412B (en) * | 2018-06-12 | 2021-12-14 | 杨力祥 | Method and computing device for isolating power information and checking power based on power information |
| CN111723115A (en) * | 2020-06-24 | 2020-09-29 | 深圳前海微众银行股份有限公司 | Data statistics method, device, terminal and storage medium based on multi-level cache |
| CN113407196A (en) * | 2021-05-10 | 2021-09-17 | 联合汽车电子有限公司 | ECU data storage method and ECU |
| CN113626487A (en) * | 2021-07-28 | 2021-11-09 | 广州市挖米科技有限责任公司 | SAAS-based high-speed electrocardiogram data transmission and display method and device |
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| CN101169809A (en) * | 2006-10-24 | 2008-04-30 | 展讯通信（上海）有限公司 | Safe JTAG connection identification system and identification method |
| CN101620656A (en) * | 2009-07-29 | 2010-01-06 | 深圳国微技术有限公司 | Safety JTAG module and method for protecting safety of information inside chip |
| CN102567245A (en) * | 2011-12-27 | 2012-07-11 | 深圳国微技术有限公司 | Memory controller for system on chip (SOC) chip system and method for implementing memory controller |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101169809A (en) * | 2006-10-24 | 2008-04-30 | 展讯通信（上海）有限公司 | Safe JTAG connection identification system and identification method |
| CN101620656A (en) * | 2009-07-29 | 2010-01-06 | 深圳国微技术有限公司 | Safety JTAG module and method for protecting safety of information inside chip |
| CN102567245A (en) * | 2011-12-27 | 2012-07-11 | 深圳国微技术有限公司 | Memory controller for system on chip (SOC) chip system and method for implementing memory controller |
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