CN104951374A - Multi-kernel processing device based on multiple operating systems - Google Patents
Multi-kernel processing device based on multiple operating systems Download PDFInfo
- Publication number
- CN104951374A CN104951374A CN201510329217.1A CN201510329217A CN104951374A CN 104951374 A CN104951374 A CN 104951374A CN 201510329217 A CN201510329217 A CN 201510329217A CN 104951374 A CN104951374 A CN 104951374A
- Authority
- CN
- China
- Prior art keywords
- circuit
- core processor
- speed communication
- data
- operating system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
The invention discloses a multi-kernel processing device based on a multiple operating systems. The multi-kernel processing device comprises a power circuit, a multi-kernel processor circuit, a shared memory circuit, a data external storage circuit, a low speed communication circuit, a high speed communication circuit and a debugging and downloading circuit. Operating systems on two kernels undergo cutting customization, so that the two operating systems can control specific hardware resources on the device in an exclusive occupation mode, and any hardware resource on the device can also be operated through the corresponding operating system. Each operating system occupies an independent space in the shared memory circuit and the data external storage circuit and does not interfere with each other in running; and each operating system can only perform data interaction through a shared memory.
Description
Technical field
The invention belongs to the airborne computer technical field in avionics system, particularly based on treating apparatus and the method thereof of multicore architecture.
Background technology
Along with the requirement of avionics system of new generation to handling property and integrated level is more and more higher, the treating apparatus of widespread use in each subsystem must have powerful computing power, multilayer buffer structure, high-speed I/O interface and vector calculus function, with reply as task scheduling, data processing, the characteristic demand of the different subsystem such as graphic plotting.The lightweight of equipment and low power consumption requirement, also propose new challenge to treating apparatus in addition.
Original technology path is by being integrated on single assembly, to reach the performance requirement of system by the treating apparatus of multiple ripe application.But the structure space that the stacking integrated requirement of this simple physics is larger, the lifting of device radiation amount does not simultaneously meet the requirement of low power consumption yet.
Summary of the invention
In order to meet lightweight and the low power consumption requirement of equipment, goal of the invention of the present invention is to provide a kind of many kernel processes based on multiple operating system device, the distribute to different kernel of the peripheral hardware resource of processor according to application demand otherness is controlled, between multiple kernel, carries out data communication by shared drive.This invention, relative to traditional technology path, takes full advantage of processor resource, has doubly changed processing power when power consumption does not have lifting.The different operating system that multiple kernel runs carries out specific customization according to different application occasion, to meet many-sided demand of system.
Goal of the invention of the present invention is achieved through the following technical solutions:
Based on many kernel processes device of multiple operating system, comprise power circuit, multi-core processor circuit, shared drive circuit, data external memory circuit, low-speed communication circuit, high-speed communication circuit, debugging and download circuit.
Described power circuit is multi-core processor circuit, shared drive circuit, data external memory circuit, low-speed communication circuit, high-speed communication circuit, debugging encourage with the corresponding power supply of download circuit adaptation;
Described multi-core processor circuit by high-speed communication circuit and low-speed communication circuit, receives the data message from other devices, to be processed and send by each operating system that multi-core processor circuit runs to data message;
Described shared drive circuit is used for as data temporary storage space, for each operating system that multi-core processor circuit runs provides data interaction bridge;
Described data external memory circuit is used for as nonvolatile space, stores the data message handled by multi-core processor circuit;
Described low-speed communication circuit is used for as the slow channels communicated with the external world, realizes receiving between multi-core processor circuit and other devices or sending low speed data information;
Described high-speed communication circuit is used for as the high-speed channel communicated with the external world, realizes receiving between multi-core processor circuit and other devices or sending high-speed data information;
Described debugging is used for as the configuration end be connected with host computer with download circuit, downloads the configuration item comprising logical code and operating system code, realizes the hardware configuration to many kernel processes device.
According to above-mentioned feature, multi-core processor circuit is integrated with the Memory Controller Hub with shared main memory circuit interface.
Further, described shared drive circuit forms by more than 1 memory chip is stacking, and each memory chip is except shared address signal, and other control signals provide by Memory Controller Hub.
According to above-mentioned feature, multi-core processor circuit is integrated with the eLBC bus controller with data external memory circuit interface.
Further, the bus being provided with more than 1 between described eLBC bus controller and data external memory circuit receives/send out controller, to be connected by receiving bus/sending out controller and to be undertaken by chip selection signal distinguishing the expansion realizing data external memory circuit with the form of daisy chain.
According to above-mentioned feature, multi-core processor circuit is integrated with and the PCIE controller of high-speed communication circuit interface and 10/100/l000M Ethernet controller.
According to above-mentioned feature, multi-core processor circuit is integrated with and the two-way UART controller of low-speed communication circuit interface and general purpose I/0 mouthful.
According to above-mentioned feature, multi-core processor circuit is integrated with and debugs the jtag interface with download circuit interface.
Compared with prior art, effect of the present invention is:
A) owing to have employed polycaryon processor, the present invention compares traditional technology path, have greatly improved in computing power, multilayer buffer memory, high-speed I/O interface and vector calculus, reduce heat and the weight of whole device simultaneously, meet miniaturization and the low power consumption requirement of air environment.
B) again owing to have employed the technology path of multiple operating system, the present invention is when the demand of variety classes application, all hardware resource in device can be made full use of, under different operating system, realize the target of each application, improve the fitness to variety classes application.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of device of many kernel processes based on multiple operating system of the present invention;
Fig. 2 is the functional schematic of a kind of device of many kernel processes based on multiple operating system of the present invention;
Fig. 3 is the structural representation of multi-core processor circuit in embodiment;
Fig. 4 is the structural representation of shared drive circuit in embodiment;
Fig. 5 is the structural representation of data external memory circuit in embodiment;
Fig. 6 is the structural representation of low-speed communication circuit in embodiment;
Fig. 7 is the structural representation of embodiment high speed telecommunication circuit;
Fig. 8 is dual operating systems working mode figure.
Embodiment
Further understand for making to have architectural feature of the present invention and effect of reaching and be familiar with, coordinate in order to preferred embodiment and accompanying drawing and describe in detail, be described as follows:
As shown in Figure 1 based on many kernel processes device of dual operating systems, comprise power circuit, multi-core processor circuit, shared drive circuit, data external memory circuit, low-speed communication circuit, high-speed communication circuit, debugging and download circuit.
Below the example of each circuit is described in detail.
1, multi-core processor circuit
Described multi-core processor circuit is as the process core of many kernel processes device, by high-speed communication circuit and low-speed communication circuit, receive from data messages such as the task control of other devices, data processing and graphic plottings, carry out purposive process and transmission.Now for the P2020NXE2KFC processor of Freescale company, multi-core processor circuit is described in detail.As shown in Figure 3.
P2020NXE2KFC has 2 e500 kernels, be integrated with the Memory Controller Hub with shared main memory circuit interface, be integrated with the eLBC bus controller with data external memory circuit interface, be integrated with and the PCIE controller of high-speed communication circuit interface and 10/100/l000M Ethernet controller, be integrated with and the two-way UART controller of low-speed communication circuit interface and general purpose I/0 mouthful, be integrated with and debug the jtag interface with download circuit interface.P2020NXE2KFC provides appropriate multiple power supplies to encourage by power circuit, after jtag interface configuration, the data message of corresponding interface circuit is received by high speed/low speed bus controller, after two e500 kernel processes, keep in/be permanently stored in internal memory/external memory as required or by internal memory/outer memory controller, or the data after process are sent to corresponding interface circuit by high speed/low speed bus controller.
2, shared drive circuit
In shared drive circuit, internal memory is the temporary storage location of data, receives the temporal data from multi-core processor, and the data of different kernel can be carried out alternately in the particular space of shared drive.The MT41K128M16JT-125AIT DDR3 chip of existing MICRON is that example describes in detail to shared drive circuit.As shown in Figure 4.
Shared drive forms by 4 MT41K128M16JT-125AIT DDR3 are chip-stacked, and every sheet DDR3 memory chip is except shared address signal, and other control signals provide separately by the Memory Controller Hub of 2020NXE2KFC processor.It is the memory headroom of 1GByte that 4 DDR3 memory chips form capacity, for the data interaction between data temporary storage and two kernels.
3, data external memory circuit
In data external memory circuit, external memory chip uses NOR FLASH chip usually, is the permanent location for storing operating system and data.The necessary strict defined basis of external memory chip, to meet the space requirement of multiple operating system.Now for the RC28F00BM29EWH type NOR FLASH memory of Numonyx company exploitation, data external memory circuit is described in detail.As shown in Figure 5.
Data external memory circuit is made up of a slice RC28F00BM29EWH type NOR FLASH memory, controlled by the eLBC bus controller of P2020NXE2KFC processor, because eLBC bus controller supports that multiple device links, therefore can be received/send out controller by bus and expand, the SN74ALVCH32973KR that controller is TIcy company is received/sent out to the bus adopted in this example, all extended chips are connected with the form of daisy chain, are distinguished by chip selection signal.
4, low-speed communication circuit
In low-speed communication circuit, the data-signal from multi-core processor is converted into the signal of communication meeting low-speed communication bus standard by low speed communication protocol chip, and carries out data interaction with far-end low speed bus equipment.Now for the MAX3077E transponder chip of MAXIM company, low-speed communication circuit is described in detail.As shown in Figure 6.
Low-speed communication bus in this example is the UART protocol communication meeting RS-232 communication standard.Data, by the Universal Asynchronous Receive/transmitter (UARTs) of P2020NXE2KFC, under full-duplex operation mode, are delivered to MAX3077E protocol chip through the FIFO of transmitting terminal and receiving end.And carry out data interaction by after MAX3077E switching levels with remote equipment.
5, high-speed communication circuit
In high-speed communication circuit, the data-signal from multi-core processor is converted into the signal of communication meeting high-speed communication bus standard by high-speed communication protocol chip, and carries out data interaction with far-end high-speed bus equipment.Now for the BCM5461SA1IPFG transponder chip of Broadcom company, low-speed communication circuit is described in detail.As shown in Figure 7.
High-speed communication bus in this example meets brief gigabit media independent interface (RGMII) media independent interface and ethernet physical layer standard 100/1000base-T.Data are sent to BCM5461SA1IPFG chip by the 10/100/l000M Ethernet controller of P2020NXE2KFC, be converted to after the signal meeting 100/1000base-T standard through HX1188 network isolation transformer again, carry out data interaction with far-end ethernet device.
6, debugging and download circuit
In debugging with download circuit, host computer is debugged multi-core processor by the debugging interface of standard.In P2020NXE2KFC, chip internal is integrated with debug circuit, and the jtag interface by means of only 10 pin just can complete efficient system debug, saves debug time.Jtag interface such as table 1 defines:
Table 1
7, power circuit
Power circuit as the total feed end of the energy of device, for multi-core processor circuit, shared drive circuit, data external memory circuit, low-speed communication circuit, high-speed communication circuit, debugging encourage with the corresponding power supply of download circuit adaptation.
As shown in Figure 2, during work, a kind of many kernel processes based on multiple operating system of the present invention device have employed multiple operating system and operates in technology path on multiple kernel respectively.According to the demand of variety classes application, carry out cutting out customization to the operating system on multiple kernel, specific hardware resource on the control device making multiple operating system can monopolize formula, also had the operating system of correspondence to manipulate with timer what hardware resource of taking up an official post.Each operating system occupies separate space and non-interference operation in shared drive circuit and data external memory circuit, between each operating system can and only carry out data interaction by shared drive.In all operations system, have and only have sole operation system to have startup higher than other operating systems and reset priority.Instantiation as shown in Figure 8.
The operating system be operated on kernel 0 is responsible for main control function, realizes discrete magnitude, switching value, low-speed interface and high-speed interface data interaction by application software; The operating system be operated on kernel 1 is responsible for figure and real function, realizes graphic plotting and Presentation Function by graphics driver and application software.Different operating system on two kernels carries out data interaction by shared drive.
Be understandable that, for those of ordinary skills, can be equal to according to technical scheme of the present invention and inventive concept thereof and replace or change, and all these change or replace the protection domain that all should belong to the claim appended by the present invention.
Claims (8)
1., based on many kernel processes device of multiple operating system, comprise power circuit, multi-core processor circuit, shared drive circuit, data external memory circuit, low-speed communication circuit, high-speed communication circuit, debugging and download circuit, it is characterized in that:
Described power circuit is multi-core processor circuit, shared drive circuit, data external memory circuit, low-speed communication circuit, high-speed communication circuit, debugging encourage with the corresponding power supply of download circuit adaptation;
Described multi-core processor circuit by high-speed communication circuit and low-speed communication circuit, receives the data message from other devices, to be processed and send by each operating system that multi-core processor circuit runs to data message;
Described shared drive circuit is used for as data temporary storage space, for each operating system that multi-core processor circuit runs provides data interaction bridge;
Described data external memory circuit is used for as nonvolatile space, stores the data message handled by multi-core processor circuit;
Described low-speed communication circuit is used for as the slow channels communicated with the external world, realizes receiving between multi-core processor circuit and other devices or sending low speed data information;
Described high-speed communication circuit is used for as the high-speed channel communicated with the external world, realizes receiving between multi-core processor circuit and other devices or sending high-speed data information;
Described debugging is used for as the configuration end be connected with host computer with download circuit, downloads the configuration item comprising logical code and operating system code, realizes the hardware configuration to many kernel processes device.
2. many kernel processes device according to claim 1, is characterized in that multi-core processor circuit is integrated with the Memory Controller Hub with shared main memory circuit interface.
3. many kernel processes device according to claim 2, it is characterized in that described shared drive circuit forms by more than 1 memory chip is stacking, each memory chip is except shared address signal, and other control signals provide by Memory Controller Hub.
4. many kernel processes device according to claim 1, is characterized in that multi-core processor circuit is integrated with the eLBC bus controller with data external memory circuit interface.
5. many kernel processes device according to claim 4, it is characterized in that the bus being provided with more than 1 between described eLBC bus controller and data external memory circuit receive/send out controller, to be connected with the form of daisy chain by receiving bus/sending out controller and to be undertaken by chip selection signal distinguishing the expansion realizing data external memory circuit.
6. many kernel processes device according to claim 1, is characterized in that multi-core processor circuit is integrated with and the PCIE controller of high-speed communication circuit interface and 10/100/l000M Ethernet controller.
7. many kernel processes device according to claim 1, is characterized in that multi-core processor circuit is integrated with and the two-way UART controller of low-speed communication circuit interface and general purpose I/0 mouthful.
8. many kernel processes device according to claim 1, is characterized in that multi-core processor circuit is integrated with and debugs the jtag interface with download circuit interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510329217.1A CN104951374A (en) | 2015-06-15 | 2015-06-15 | Multi-kernel processing device based on multiple operating systems |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510329217.1A CN104951374A (en) | 2015-06-15 | 2015-06-15 | Multi-kernel processing device based on multiple operating systems |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104951374A true CN104951374A (en) | 2015-09-30 |
Family
ID=54166042
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510329217.1A Pending CN104951374A (en) | 2015-06-15 | 2015-06-15 | Multi-kernel processing device based on multiple operating systems |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104951374A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106648932A (en) * | 2016-12-19 | 2017-05-10 | 四川长虹电器股份有限公司 | Python extended module-based multi-process share system and method |
| CN108845520A (en) * | 2018-06-12 | 2018-11-20 | 西安微电子技术研究所 | A kind of embedded processing module based on P4080 processor |
| CN110502928A (en) * | 2019-08-28 | 2019-11-26 | 上海金卓网络科技有限公司 | Dual operating systems, working state control method, apparatus and storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101216814A (en) * | 2007-12-26 | 2008-07-09 | 杭州华三通信技术有限公司 | Communication method and system of multi-nuclear multi-operating system |
| CN101477511A (en) * | 2008-12-31 | 2009-07-08 | 杭州华三通信技术有限公司 | Method and apparatus for sharing memory medium between multiple operating systems |
| CN101526934A (en) * | 2009-04-21 | 2009-09-09 | 浪潮电子信息产业股份有限公司 | Construction method of GPU and CPU combined processor |
-
2015
- 2015-06-15 CN CN201510329217.1A patent/CN104951374A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101216814A (en) * | 2007-12-26 | 2008-07-09 | 杭州华三通信技术有限公司 | Communication method and system of multi-nuclear multi-operating system |
| CN101477511A (en) * | 2008-12-31 | 2009-07-08 | 杭州华三通信技术有限公司 | Method and apparatus for sharing memory medium between multiple operating systems |
| CN101526934A (en) * | 2009-04-21 | 2009-09-09 | 浪潮电子信息产业股份有限公司 | Construction method of GPU and CPU combined processor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106648932A (en) * | 2016-12-19 | 2017-05-10 | 四川长虹电器股份有限公司 | Python extended module-based multi-process share system and method |
| CN108845520A (en) * | 2018-06-12 | 2018-11-20 | 西安微电子技术研究所 | A kind of embedded processing module based on P4080 processor |
| CN110502928A (en) * | 2019-08-28 | 2019-11-26 | 上海金卓网络科技有限公司 | Dual operating systems, working state control method, apparatus and storage medium |
| CN110502928B (en) * | 2019-08-28 | 2022-03-29 | 上海金卓科技有限公司 | Dual operating system, working state control method, device and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10152441B2 (en) | Host bus access by add-on devices via a network interface controller | |
| US8069293B1 (en) | Flexible server network connection upgrade systems and methods | |
| US9100349B2 (en) | User selectable multiple protocol network interface device | |
| US20140068134A1 (en) | Data transmission apparatus, system, and method | |
| KR101502610B1 (en) | 50 Gb/s ETHERNET USING SERIALIZER/DESERIALIZER LANES | |
| CN101202707B (en) | Method for transmitting message of high speed single board, field programmable gate array and high speed single board | |
| CN101957808B (en) | Communication method among various CPUs (Central Processing Units), system and CPU | |
| CN101902504A (en) | Avionic full-duplex switched-type Ethernet network card and integration method thereof | |
| CN108388532A (en) | The AI operations that configurable hardware calculates power accelerate board and its processing method, server | |
| CN113228567B (en) | Information processing method and device and information processing system | |
| CN105549916A (en) | Peripheral component interconnect express (PCIe) solid state hard disk controller, PCIe based storage system and data read and write method thereof | |
| US20130100812A1 (en) | Packet priority in a network processor | |
| CN102185833A (en) | Fiber channel (FC) input/output (I/O) parallel processing method based on field programmable gate array (FPGA) | |
| CN113645047B (en) | Out-of-band management system and server based on intelligent network card | |
| CN104951374A (en) | Multi-kernel processing device based on multiple operating systems | |
| CN204423250U (en) | A kind of X86 embedded type CPU mainboard with multipath high-speed intelligent CAN | |
| Ruimei et al. | Design of ARM-based embedded Ethernet interface | |
| US9288163B2 (en) | Low-latency packet receive method for networking devices | |
| CN113098955A (en) | Data transmission method, device, equipment and computer readable storage medium | |
| CN204390237U (en) | A kind of encryption and decryption card of Based PC I-E bussing technique | |
| CN116401065A (en) | Server, heterogeneous equipment and data processing device thereof | |
| CN212569751U (en) | Remote debugging platform based on Feiteng 2000+ server | |
| CN103139061B (en) | For the method for aviation special full duplex switched ethernet terminal system | |
| Zang et al. | PROP: Using PCIe-based RDMA to accelerate rack-scale communications in data centers | |
| CN104967526A (en) | Serial port communication server |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150930 |