CN104917784B

CN104917784B - A kind of data migration method, device and computer system

Info

Publication number: CN104917784B
Application number: CN201410086085.XA
Authority: CN
Inventors: 褚力行
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2014-03-10
Filing date: 2014-03-10
Publication date: 2018-06-05
Anticipated expiration: 2034-03-10
Also published as: WO2015135383A1; CN104917784A

Abstract

An embodiment of the present invention provides a kind of data migration method, device and computer system, based on this method, the speed of Data Migration, lifting system performance can be improved.This method includes：In process P0 after logical node i moves to logical node j, according to the data that the process P0 is accessed in the virtual address of logical node i, the physical address of data that the process P0 accesses in the logical node i is determined；According to the data that the P0 is accessed in the physical address of the logical node i, the process P0 data accessed are copied into the caching of the logical node j from the first memory of the logical node i；If it is determined that the data that the process P0 is accessed meet transition condition, the process P0 data accessed are migrated from the caching of the logical node j into the first memory of the logical node j.This method is suitable for field of computer technology.

Description

A kind of data migration method, device and computer system

Technical field

The present invention relates to a kind of field of computer technology more particularly to data migration method, device and computer systems.

Background technology

It is clothes that Non Uniform Memory Access, which accesses (Non Uniform Memory Access Architecture, NUMA) framework, One kind of business device framework, is divided into multiple nodes, each logical node is allocated a center by entire server system in logic Processor (Central Processing Unit, CPU) and one section of corresponding physical memory, each logical node can access This node memory source (local memory) can also access the memory source (remote memory) of other nodes, but access local money The speed in source significantly faster than accesses remote memory, and generally under NUMA architecture, the delay for accessing remote memory is accessed in local 3-20 times deposited.

NUMA architecture has the advantages of being easily managed, expandability is good, still, in existing operating system (Operating System, OS) in mechanism, it will usually load balancing is carried out according to the state of CPU, so as to by one in the CPU of heavier loads Or multiple thread/process migrations are on other CPU.Such as when the load of CPU is very high, OS will line up from the task of the CPU In, select specific process/thread, being moved to other CPU of the task is lined up.But when operating system is by the process After moving to other logical nodes, the data which accesses usually will not also be moved to the memory of other logical nodes. In this way, the data accessed due to the process are still in the memory of original logical node, so when the process accesses data, Cross-node is needed to access, so as to cause a large amount of remote access, access delay is increased, reduces system performance.

In the prior art, following solution is proposed regarding to the issue above：When OS is by the process/thread of source logical node After moving to purpose logical node, when the data that the process accesses meet the condition of Data Migration, number which is accessed Purpose logical node is moved to according to from source logical node.But directly the data that the process accesses are migrated from source logical node Time to purpose logical node is longer, and the expense brought is larger, and it is still very undesirable to improve system performance.

The content of the invention

The embodiment provides a kind of data migration method, device and computer systems, can improve data and move The speed of shifting, it is achieved thereby that the raising of systematic entirety energy.

In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that：

In a first aspect, an embodiment of the present invention provides a kind of data migration methods, NUMA architecture is by multiple physical nodes, section Point control chip and NUMA managers are formed, wherein, each physical node is divided into one or more logical nodes, each patrols It collects node and is assigned first processor, the first memory, first processor cache memory and caching；The node control Chip carries out the duplication of data between described two physical nodes for connecting two physical nodes；The NUMA managers, by Bus, the second processor being connected with bus and the second memory being connected with bus composition, wherein, the second processor and institute There is the physical node to be connected, for being managed to the physical node, second memory is used to store described second The instruction that processor needs call, this method are applied to the NUMA managers, and this method includes：

In process P0 after logical node i moves to logical node j, the data accessed according to the process P0 are in logic section The virtual address of point i determines physical address of the data in the logical node i of the process P0 access；

According to the data that the P0 is accessed in the physical address of the logical node i, the data that the process P0 is accessed The caching of the logical node j is copied to from the first memory of the logical node i；

If it is determined that the data that the process P0 is accessed meet transition condition, the process P0 data accessed are patrolled from described The caching for collecting node j is migrated into the first memory of the logical node j.

In the first possible embodiment, with reference to first aspect, described moved in process P0 from logical node i is patrolled During volume node j, according to the data that the process P0 is accessed in the virtual address of logical node i, determine what the process P0 was accessed After the physical address of the logical node i, this method further includes data：

Judge the logical node i and the logical node j whether in same physical node；

If the logical node i and the logical node j in same physical node, are not sent to the node control chip Notification message, the notification message include the data of process P0 access in the physical address of the logical node i, the section Point control chip is connected respectively with the physical node where the logical node i and the physical node where the logical node j, So that the node control chip copies to the data that the process P0 is accessed from the first memory of the logical node i The caching of the logical node j；

If in same physical node, the process P0 data accessed are answered by the logical node i and logical node j Make the caching of the logical node j.

In second of possible embodiment, with reference to first aspect or the first possible embodiment, it is described into Journey P0 from logical node i move to logical node j when, according to the process P0 access data in logical node i virtually Location determines the data of the process P0 access after the physical address of the logical node i, and this method further includes：

If the logical node i and the logical node j in same physical node, do not send to node control chip and notify Message, in the notification message comprising the data that the process P0 is accessed the logical node i physical address so that institute State node control chip by the process P0 access in the first processor cache memory of the logical node i Data copy to the first processing of the logical node j from the first processor cache memory of the logical node i In device cache memory；

If the logical node i and logical node j is patrolled in same physical node, the process P0 access described The data in the first processor cache memory of node i are collected, from the first processor speed buffering of the logical node i It is copied in memory in the first processor cache memory of the logical node j；

The first notification message is sent to all logical nodes, first notification message is used to that the process P0 to be notified to access The data in the first processor cache memory of the logical node i be copied to the of the logical node j In one processor high speed buffer storage.

In the third possible embodiment, with reference to first aspect, the first possible embodiment or second can Any one of embodiment of energy, it is described if it is determined that the data that the process P0 is accessed meet transition condition, by the process After the data that P0 is accessed are migrated from the caching of the logical node j into the first memory of the logical node j, this method is also wrapped It includes：

The data that the process P0 is accessed are established to close in the virtual address of the logical node j and the mapping of physical address System.

Second aspect, an embodiment of the present invention provides a kind of data migration device, which includes：Determination unit, duplication Unit and migration units；

The determination unit, in process P0 after logical node i moves to logical node j, according to the process P0 The data of access determine the physics of data that the process P0 accesses in the logical node i in the virtual address of logical node i Address；

The copied cells, for according to the data that the P0 is accessed the logical node i physical address, will described in The data that process P0 is accessed copy to the caching of the logical node j from the memory of the logical node i；

The migration units, for if it is determined that the data that the process P0 is accessed meet transition condition, by the process P0 The data of access are migrated from the caching of the logical node j into the memory of the logical node j.

In the first possible embodiment, with reference to second aspect, which further includes：Judging unit；

The judging unit, for judging the logical node i and the logical node j whether in same physical node；

The copied cells is specifically used for：

If the logical node i and the logical node j in same physical node, do not send to node control chip and notify Message, the notification message include the data of process P0 access in the physical address of the logical node i, the node control Coremaking piece is connected respectively with the physical node where the logical node i and the physical node where the logical node j, so that It obtains the node control chip and the data that the process P0 is accessed is copied into the logic from the memory of the logical node i The caching of node j；

In second of possible embodiment, with reference to second aspect or the first possible embodiment, optionally, institute Copied cells is stated to be additionally operable to：

If the logical node i and the logical node j in same physical node, do not send to node control chip and notify Message, in the notification message comprising the data that the process P0 is accessed the logical node i physical address so that institute State the number in the processor high speed buffer storage of the logical node i that node control chip accesses the process P0 According to the processor high speed that the logical node j is copied to from the processor high speed buffer storage of the logical node i buffers In memory；

If the logical node i and logical node j is patrolled in same physical node, the process P0 access described The data in the processor high speed buffer storage of node i are collected, from the processor high speed buffer storage of the logical node i It copies in the processor high speed buffer storage of the logical node j；

Specifically, the device further includes：Transmitting element；

The transmitting element, for sending the first notification message to all logical nodes, first notification message is used for Data in the processor high speed buffer storage of the logical node i that the process P0 is accessed is notified to be copied to described In the processor high speed buffer storage of logical node j.

In the third possible embodiment, with reference to second aspect, the first possible embodiment or second can Any one of embodiment of energy, which further includes：Establish unit；

It is described to establish unit, for establish data that the process P0 accesses the logical node j virtual address with The mapping relations of physical address.

The third aspect, an embodiment of the present invention provides a kind of computer system, including：

Multiple physical nodes, wherein, each physical node is divided into one or more logical nodes, each logical node It is assigned first processor, the first memory, first processor cache memory and caching；

Node control chip for connecting two physical nodes, carries out the duplication of data between described two physical nodes；

NUMA managers, by bus, the second processor being connected with bus and the second memory being connected with bus composition, In, the second processor is connected with all physical nodes, for being managed to the physical node, described second Memory is used to store the instruction that the second processor needs call；

The second processor calls executing instruction in second memory by the bus, for：In process P0 after logical node i moves to logical node j, according to the process P0 access data logical node i virtual address, Determine physical address of the data in the logical node i of the process P0 access；

In the first possible embodiment, with reference to the third aspect, the processor is specifically used for：

In second of possible embodiment, with reference to the third aspect or the first possible embodiment, the processing Device is additionally operable to：

In the third possible embodiment, with reference to the third aspect, the first possible embodiment or second can Any one of embodiment of energy, the processor is additionally operable to：

An embodiment of the present invention provides a kind of data migration method, device and computer system, this method includes：In process P0 from logical node i move to logical node j when, according to the process P0 access data logical node i virtual address, Determine physical address of the data in the logical node i of the process P0 access；The data accessed according to the P0 are described The process P0 data accessed are copied to institute by the physical address of logical node i from the first memory of the logical node i State the caching of logical node j；If it is determined that the data that the process P0 is accessed meet transition condition, the number that the process P0 is accessed It is migrated according to from the caching of the logical node j into the first memory of the logical node j.Based on technical scheme, Can in process after source logical node is migrated to purpose logical node, the process access data meet transition condition it Before, first the data that the process accesses are copied in the caching of purpose logical node, once the data satisfaction that the process accesses is moved The data that the process accesses quickly can be moved to the purpose logical node by shifting condition from the caching of purpose logical node In memory, so as to improve the speed of the migration for the data that the process accesses, and then systematic entirety energy is improved.

Description of the drawings

It in order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this Some embodiments of invention, for those of ordinary skill in the art, without creative efforts, can be with Other attached drawings are obtained according to these attached drawings.

Fig. 1 a are a kind of NUMA architecture schematic diagram；

Fig. 1 b are another NUMA architecture schematic diagram；

Fig. 2 is another NUMA architecture schematic diagram；

Fig. 3 is a kind of data migration method flow chart；

Fig. 4 is another NUMA architecture schematic diagram；

Fig. 5 is another data migration method flow chart；

Fig. 6 is another data migration method flow chart；

Fig. 7 is a kind of data migration device schematic diagram；

Fig. 8 is another data migration device schematic diagram；

Fig. 9 is another data migration device schematic diagram；

Figure 10 is another data migration device schematic diagram；

Figure 11 is a kind of computer system schematic diagram.

Specific embodiment

Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on Embodiment in the present invention, those of ordinary skill in the art are obtained every other without making creative work Embodiment belongs to the scope of protection of the invention.

NUMA architecture is a kind of multi node server framework, by multiple physical nodes, node control chip and NUMA management Device three parts are formed, specifically：

First portion：Multiple physical nodes.In actual hardware configuration, in each physical node there are one or multiple places Device is managed, each processor corresponds to one section of physical memory and the corresponding cache memory of each processor.

With reference to Fig. 1 a, when, only there are one during processor, can only the physical node being divided into one in a physical node A logical node, the logical node are assigned processor, memory and processor high speed buffer storage.

When there are multiple processors in the physical node, the physical node can be divided according to the physical memory For multiple logical nodes.In this way, there are two kinds of situations, the first situation is to be allocated that there are one processors in a logical node And the corresponding one section of physical memory of the processor, the second situation are to be assigned two or more places in a logical node Manage device and the corresponding physical memory of each processor.

It should be noted that in the latter case, for example, if being allocated in a logical node, there are two processing Device, wherein, each processor has corresponding physical memory.At this point, one of processor is accessed in its corresponding physical memory The delay of the data stored in the delay of the data of storage physical memory corresponding with accessing another processor is the same.One A process/thread will not be generated from one of processor migration to another described processor access delay become larger ask Topic, therefore, in the present invention it is possible to regard the two processors as same processor, the two processors are corresponding Physical memory 2 regards same section of physical memory as.With reference to Fig. 1 b, a physical node is divided into two or more logical nodes.

Second portion：Node control chip.Specifically：In the multi node server of NUMA architecture, when the object of server Managing number of nodes increases, if each physical node can be confined to the number of ports or limited of node by way of cable direct interconnection It is formed on interconnected communication agreement, for example, when four physical nodes need to interconnect two-by-two, each physical node needs three and connects Mouthful, when N number of physical node needs to interconnect two-by-two, each physical node needs N-1 interface, therefore, when using cable straight When connecing interconnection, the number of ports of physical node can limit the connection of physical node.

Since chip can have multiple interfaces, each node server can be interconnected by node control chip Get up, i.e. two adjacent physical nodes are connected by a node control chip, and the node control chip is mainly used for object The high speed interconnection between node is managed, such as the interconnection that communicates between processor and processor, the duplication of data between physical node, and It can realize the functions such as buffer consistency inspection, message forwarding.

It should be noted that with reference to Fig. 2, a node control chip can only connect two physical nodes, can also be same When connect multiple physical nodes, realize the interconnection two-by-two of physical node, it is not limited in the embodiment of the present invention.

Certainly, whether for being connected between two physical nodes using node control chip, the present invention does not limit.

Part III：NUMA managers.The NUMA managers are made of processor, memory and bus, the NUMA pipes Processor in reason device is connected with all physical nodes in the first portion, for being carried out to all physical nodes Management.

When the operating system of NUMA architecture is according to distributing to the non-load balanced case of each logical node processor by logic After one process P0 of node i moves to logical node j, the data for accessing the process when general different are simultaneously from logical node The internal memory migration of i is into the memory of the logical node j, to avoid unnecessary expense.If for example, the process P0 is migrated It does not visit again and is had moved to the data of the process P0 access of destination node memory or the process P0 after to logical node j After being migrated to logical node j, operating system moves the P0 according to the non-load balanced case of the processor of each logical node It is moved back to logical node i or moves to other logical nodes except logical node i and logical node j, at this point, the process P0 is moved While moving on to logical node j, by the data that the P0 is accessed from the internal memory migration of logical node i to the logical node j's In memory, unnecessary expense can be caused, reduces the performance of system.But if the process P0 is moved to from logical node i After logical node j, Data Migration P0 not accessed, when process P0 accesses the data of oneself, will result in logical node j Cross-node accesses, that is, remote access, at this point, the delay that P0 accesses the data of oneself is very big, reduces the performance of system.

Therefore, after process P0 is migrated to logical node j from logical node i, when the data that the process P0 is accessed expire During the condition migrated enough, the process P0 data accessed just can be moved to logical node j by operating system from logical node i, But in the prior art, the data that process P0 is accessed directly are moved to the speed of logical node j from logical node i cross-nodes Degree it is slower, the expense of Data Migration may balance out the effect of Data Migration, for example, when process P0 by operating system from After logical node i is moved on logical node j, the data that P0 accesses logical node i need 3s, access the data of logical node j 1s is needed, but the data that P0 is accessed may be 3s from the logical node i times for moving to logical node j by operating system, in this way, These data are being accessed after memory of the P0 wait operating systems by the Data Migration that P0 is accessed to logical node j, when total Between for 4s, the data delay than directly accessing logical node i is also long, and the expense of migration counteracts the effect of migration.

For this problem, the present invention proposes a kind of data migration method, can be in a process P0 quilt based on this method After operating system moves to logical node j from logical node i, and the data of process P0 access meet the condition of migration, Accelerate the migration of data.With reference to Fig. 3, this method is applied to the NUMA managers, and this method includes：

301st, in process P0 after logical node i moves to logical node j, patrolled according to the process P0 data accessed The virtual address of node i is collected, determines physical address of the data in the logical node i of the process P0 access.

After a process P0 is established, operating system can establish the virtual addresses of the data that P0 is accessed with physically The process P0 when operating system is according to the principle of load balancing, is moved to logic section by the mapping relations of location from logical node i After point j, the operating system can be accessed according to the virtual address and the process P0 of the process P0 data accessed The virtual address of data and the mapping relations of physical address, determine data that the process P0 is accessed in the logical node i Physical address.

Specifically, most of systems using virtual memory are all using a kind of mechanism for being known as paging (paging).It is empty Intend the space that address space is divided into referred to as page (page), and corresponding physical address space is also carried out dividing, unit is page Frame (frame).In the machine of 32 bit address, it can virtually form the Virtual Space of 4G, virtual address range from 0~ 0xFFFFFFFF, therefore he can run the program of 4G.And this machine only has the memory headroom of 256M, so more than 256M's Program cannot disposably call in memory operation.This machine must there are one can store the external memory more than 256M programs (such as disk or flash memory FLASH), to ensure that usability of program fragments can be called in memory when needed.In this example In, the size of page is 4K, and page hardwood size is identical with page --- this point must assure that, because between memory and peripheral storage Transmission always in units of page.The virtual address of corresponding 4G and the physical storage of 256M, they contain 1M respectively Page and 64K page frame.

Page table embodies the virtual address of data and the mapping relations of physical address that a process accesses, and realizes from page Number, i.e. the mapping of virtual address to page frame, i.e. physical address.Operating system safeguards a page table to each process, and page table is given The position of the page frame in process corresponding to every page is gone out.

Based on this, operating system can pass through according to the data that the process P0 is accessed in the virtual address of logical node i Page table is inquired about, determines physical address of the data in logical node i of the process P0 access.

Specifically, the virtual address of process and the mapping relations of physical address can be the forms of page table, it can also It is other forms, it is not limited in the embodiment of the present invention.

302nd, according to the P0 access data the logical node i physical address, by the process P0 access Data copy to the caching of the logical node j from the memory of the logical node i.

Due in the prior art, when the data that the process P0 is accessed meet the condition of migration, directly will described in into The time that the data that journey P0 is accessed are moved to from the logical node i used in logical node j is longer, and the expense of migration is larger, can It can balance out the effect of migration.For this problem, the embodiment of the present invention is in the server system of the NUMA architecture Increase a caching in each logical node, specifically, the caching can be a part for the memory of the logical node j, Or a part for the processor high speed buffer storage of the logical node j, as shown in figure 4, can also be one solely Vertical buffer memory device, it is not limited in the embodiment of the present invention.

Specifically, since most of systems using virtual memory are all known as paging (paging) mechanism using a kind of, The data that the P0 is accessed are stored in multiple pages of the logical node i, therefore, the operating system it is described into Journey P0 is after the logical node i moves to logical node j, and the data that the process P0 is accessed are from the logical node i Page, copy to the hardware cache of the logical node j, i.e., in the page of described caching.

Specifically, for example, for example described process P0 accesses some data in data, the logical node i's Virtual address is page m, the logical node i physical address for page n, when the operating system is by the process After the data for the page n that P0 is accessed are copied in the page k of the caching, the operating system is for process P0 visits The data asked are between the address of the virtual address of the logical node i, physical address and caching in the logical node j Correspondence, establish a following mapping table：

Table one

The virtual address of logical node i	The physical address of logical node i	The address of the caching of logical node j
			Page m	Page n	Page k

Specifically, the correspondence between described address can be the form such as above table, for example, page table or Other forms, it is not limited in the embodiment of the present invention.

Further, such as the process P0 accesses some data, is page in the virtual address of the logical node i M+1, it is corresponding, it is page n+1 in the physical address of the logical node i, also, when the data in the page n+1 After being copied in the caching of the logical node j, it is stored in the page k+1 of the logical node j.The operation system System in such a manner, by the process P0 access data the virtual address of the logical node i, physical address and The address of the logical node j corresponds.

After the process P0 moves to logical node j by operating system from the logical node i, the operating system will The data that the process P0 is accessed copy to the caching of the logical node j from the memory of the logical node i, in this way, working as When the data that the process P0 is accessed meet the condition of migration, the operating system can be by inquiring about page as shown in Table 1 The caching of the data that the P0 is accessed from the logical node j are directly moved in the memory of the logical node j, carried by table The high speed of migration, and then improve the overall performance of system.

It should be noted that the data in the process accessed the process P0 when the operating system are from the logic After the memory of node i copies to the caching of the logical node j, data that the process P0 is accessed meet transition condition it Before, since the delay that the process P0 accesses the caching of the logical node j is longer, under normal conditions the P0 still by across Node visit, to access the data of the access of logical node P0 described in the memory of the logical node i.Therefore, it is described at this time to patrol Still retain the data that the process P0 is accessed in the memory of volume node i, and cannot by the data that the process P0 is accessed from After the memory of the logical node i copies to the caching of the logical node j, the process P0 data accessed are patrolled described The occupied memory of node i is collected to discharge.

303rd, if it is determined that the data that the process P0 is accessed meet transition condition, the data that the process P0 is accessed are from institute The caching for stating logical node j is migrated into the memory of the logical node j.

Specifically, in different systems, judge data whether meet migration condition it is different.For example, exist In linux system, when turn-on data shift function, when each clock interrupt arrives, system processing clock interrupt, which can check, works as Whether the non-load balanced case and differentiation process of preceding system have remote memory access.During inspection, patrolled when first time finds one When collecting the data in the page in node memory by process remote access, which can be marked；At subsequent clock interruption During reason, when finding there is the page to be marked with remote access, the data in the page will be migrated.

Certainly, it is the known technology of those skilled in the art to judge condition that whether data in memory meet migration, this Inventive embodiments repeat no more this.

When the memory of the data from the logical node i that access the process P0 copy to the slow of the logical node j After depositing, operating system judges whether the data that the process P0 is accessed meet the condition of Data Migration, if satisfied, by the process The data that P0 is accessed are migrated from the caching of the logical node j into the memory of the logical node j, and afterwards, the P0 is accessed The data of oneself are local IP access, and delay is smaller, and then the performance of lifting system.

It is migrated when by caching of the data that the process P0 is accessed from the logical node j to the logical node j After depositing, the operating system can discharge the data that the process P0 in the memory of the logical node i is accessed, and And the operating system re-establish data that the process P0 accesses the logical node j virtual address with physically The mapping relations of location.

An embodiment of the present invention provides a kind of data migration method, this method includes：It is migrated in process P0 from logical node i During to logical node j, according to the data that the process P0 is accessed in the virtual address of logical node i, determine that the process P0 is visited The data asked are in the physical address of the logical node i；According to the P0 access data in the logical node i physically The process P0 data accessed are copied to the caching of the logical node j by location from the memory of the logical node i；If Determine that the data that the process P0 is accessed meet transition condition, the data that the process P0 is accessed are from the logical node j's Caching is migrated into the memory of the logical node j.Based on the present invention, can be migrated in a process from source logical node After purpose logical node, when the data that the process accesses meet transition condition, quickly by the data that the process accesses from mesh The caching of logical node move in the memory of the purpose logical node, so as to promote the speed of Data Migration, Jin Erti High systematic entirety energy.

Further, the embodiment of the present invention additionally provides a kind of data migration method, and this method is to above-described embodiment It is described in detail, with reference to Fig. 5, this method is applied to NUMA managers, and this method includes：

501st, when process P0 moves to logical node j from logical node i, patrolled according to the process P0 data accessed The virtual address of node i is collected, determines physical address of the data in the logical node i of the process P0 access.

Specifically, the detailed implementation process of step 501 refer to the step 301 in above-described embodiment, the embodiment of the present invention This is repeated no more.

502nd, judge the logical node i and the logical node j whether in same physical node.

With reference to Fig. 1 a, Fig. 1 b and Fig. 2, in the server system of NUMA architecture, in a physical node may there are one Logical node, it is also possible to there are two or multiple logical nodes, based on this, when operating system is according to the processor of each logical node Non-load balanced case by the process P0 from logical node i move to logical node j when, the logical node i and institute Stating logical node j may be in same physical node, it is also possible in different physical nodes.In both cases, the operation The memory of the data that the process P0 is accessed from the logical node i are copied to the side of the caching of the logical node j by system Method is different, and therefore, memory of the operating system in the data from the logical node i that access the process P0 copies to institute The caching of logical node j is stated before, it is necessary to judge the logical node i and the logical node j whether in same physical node.

If the 503rd, the logical node i and logical node j is sent not in same physical node to node control chip Notification message, the notification message include the data of process P0 access in the physical address of the logical node i, the section Point control chip is connected respectively with the physical node where the logical node i and the physical node where the logical node j, So that the node control chip data that the process P0 is accessed are copied to from the memory of the logical node i it is described The caching of logical node j.

With reference to Fig. 1 a, Fig. 1 b, if the logical node i and the logical node j be not in same physical node, the logic It is connected between the physical node where physical node and the logical node j where node i by a node control chip, institute Stating operating system can not directly copy to the memory of process P0 data from the logical node i accessed across physical node The caching of the logical node j, but the operating system can pass through the physical node where the connection logical node i and institute The node control chip of the physical node where logical node j is stated by the data that the process P0 is accessed from the logical node i Internal memory migration to the caching of the logical node j, detailed process is：

The operating system judges the logical node i and the logical node j not after same physical node, Xiang Lian The node control chip for tying the physical node where the logical node i and the physical node where logical node j sends notice Message, the notification message include physical address of the data in the logical node i of process P0 access.It is at this point, described Node control chip according to the data that the process P0 is accessed the logical node i physical address, by the process P0 visit The memory of the data asked from the logical node i copy to the caching of the logical node j.

It should be noted that according to the Process Migration Mechanism of existing operating system, the operating system is according to each patrolling The process P0 is moved to logical node j by the non-load balanced case for collecting the processor in node from logical node i, if described patrol Node i and the logical node j are collected not in same physical node, the process P0 is needed by connecting the logical node i institutes Physical node and logical node j where physical node node control chip or cable carry out remote access logical node i Described in process P0 data, based on this, when the process is moved to described patrol by the operating system from the logical node i When collecting node j, the physical node where physical node and the logical node j where the logical node i must have section Two physical nodes that point control chip or cable are connected, otherwise when the process P0 moves to logic from the logical node i After node j, the process P0 can not access the data of the P0 of the logical node i, and process is caused to access the mistake of data It loses.

If the 504th, the logical node i and logical node j is in same physical node, the number that the process P0 is accessed According to the caching for copying to the logical node j.

If the logical node i and logical node j is in same physical node, by the process P0 from the logic section After point i moves to the logical node j, the process P0 accesses the delay of the data of the P0 of the logical node i, is less than When the logical node i and the logical node j be not in same physical node, across the physical node access data of process P0 Delay, but be still more than the delay that the process P0 accesses the memory of logical node where it, the performance of system can be reduced. Using data migration method provided by the present invention, can be improved when the process P0 data accessed meet transition condition The speed of Data Migration, and then the overall performance of lifting system.

If specifically, the logical node i and logical node j is in same physical node, the operating system can be with The memory of process P0 data from the logical node i accessed is directly copied to the caching of the logical node j.

505th, if it is determined that the data that the process P0 is accessed meet transition condition, the data that the process P0 is accessed are from institute The caching for stating logical node j is migrated into the memory of the logical node j.

Specifically, the detailed process of step 505 can be found in the step 303 in above-described embodiment, the embodiment of the present invention is no longer It repeats.

It, can be in a process from source logic based on this method an embodiment of the present invention provides a kind of data migration method After node is migrated to purpose logical node, when the data that the process accesses meet the condition of Data Migration, quickly by institute The data of process access are stated from the memory that the caching of purpose logical node moves to the destination node, are moved so as to promote data The speed of shifting, and then improve systematic entirety energy.

Further, when the data for accessing the process P0 are from the internal memory migration of the logical node i to the logic After in the caching of node j, to reduce the remote access of the process P0, the embodiment of the present invention additionally provides a kind of Data Migration side Method, with reference to Fig. 6, this method is applied to NUMA managers, and this method includes：

601st, when process P0 moves to logical node j from logical node i, patrolled according to the process P0 data accessed The virtual address of node i is collected, determines physical address of the data in the logical node i of the process P0 access.

602nd, judge the logical node i and the logical node j whether in same physical node.

The detailed implementation process of step 601- steps 602 can be found in step 301 and step 302 in above-described embodiment, this Inventive embodiments repeat no more this.

If the 603rd, the logical node i and logical node j is sent not in same physical node to node control chip Notification message, in the notification message comprising the data that the process P0 is accessed the logical node i physical address so that The node control chip by the process P0 access in the processor high speed buffer storage of the logical node i Data, the processor high speed that the logical node j is copied to from the processor high speed buffer storage of the logical node i delay It rushes in memory.

When the memory of the data that the process P0 is accessed from the logical node i are copied to described patrol by the operating system After collecting in the caching of node j, before the data of P0 access meet transition condition, the P0 needs to continue cross-node access It is larger to access delay for the data of process P0 described in the memory of the logical node i.To reduce the distal end of the process P0 to the greatest extent The data that the process P0 is accessed are copied to logical node j's by access times in the operating system from the logical node i Meanwhile the data in the processor high speed buffer storage of the logical node i that can simultaneously access the process P0, The processor high speed buffer storage of the logical node j is copied to from the processor high speed buffer storage of logical node i.

The data in the processor high speed buffer storage of the logical node i that the process P0 is accessed be it is described into Some higher data of journey P0 access frequencys, when the operating system by the process P0 access the logical node i's After data in processor high speed buffer storage are copied in the processor high speed buffer storage of the logical node j, institute When the process P0 of stating will access these data again, this in the processor high speed buffer storage of the node j can be directly accessed A little data, it is local IP access that the process P0, which accesses the data of oneself, at this time, and delay is smaller.

If not in same physical node, the operating system is needed to connection by the logical node i and the logical node j The node control chip of the physical node where physical node and logical node j where the logical node i sends notice and disappears It ceases, the data comprising process P0 access in the notification message are in the physical address of the logical node i, the node control Coremaking piece can determine that the processor high speed of the node i delays according to the process P0 in the physical address of the logical node i Rush in memory the data that process P0 is accessed described in storage in which page, the node control chip by these data from The processor high speed buffer storage of the logical node i copies to the processor high speed buffer storage of the logical node j.

If the 604, the logical node i and logical node j is in same physical node, the process P0 access in institute The data in the processor high speed buffer storage of logical node i are stated, from the processor high speed buffer-stored of the logical node i It is copied in device in the processor high speed buffer storage of the logical node j.

Specifically, when the logical node i and the logical node j are in same physical node, the operation system The data in the processor high speed buffer storage of the logical node i that system can directly access the process P0, from The processor high speed buffer storage of the logical node i copies to the processor high speed buffer-stored of the logical node j Device.

605th, the first notification message is sent to all logical nodes, first notification message is used to notify the process P0 The data in the processor high speed buffer storage of the logical node i accessed are copied to the place of the logical node j It manages in device cache memory.

Specifically, when the number in the processor high speed buffer storage of the logical node i of process P0 access After being copied in the processor high speed buffer storage of the logical node j, to make the process P0 and other and institute Other processes that the process P0 of stating shares partial data are able to access that in the processor high speed buffer storage of the logical node j Data, the operating system are operated by buffer consistency, send the first notification message to all logical nodes, described first is logical Message is known for notifying the data quilt in the processor high speed buffer storage of the logical node i of the process P0 access It copies in the processor high speed buffer storage of the logical node j.

Specifically, when the logical node i and the logical node j be not in same physical node, the operating system It can be by connecting the node control core of the physical node where the logical node i and the physical node where logical node j Piece, all logical nodes into the server system of the NUMA architecture issue first notification message；

When the logical node i and the logical node j are in same physical node, the operating system can directly to All logical nodes issue first notification message.

Specifically, buffer consistency operation be those skilled in the art known technology, the embodiment of the present invention to this no longer It repeats.

It, can be in a process from source logic based on this method an embodiment of the present invention provides a kind of data migration method After node is migrated to purpose logical node, when the data that the process accesses meet transition condition, quickly by the process The data of access are moved to from the caching of the purpose logical node in the memory of the purpose logical node, so as to promote data The speed of migration, and then improve systematic entirety energy.

An embodiment of the present invention provides a kind of data migration devices, and with reference to Fig. 7, which includes：Determination unit 701 is answered Unit 702 processed and migration units 703；

The determination unit 701, for when process P0 moves to logical node j from logical node i, according to the process The data that P0 is accessed determine the object of data that the process P0 accesses in the logical node i in the virtual address of logical node i Manage address；

The copied cells 702, for according to the data that the P0 is accessed the logical node i physical address, will The data that the process P0 is accessed copy to the caching of the logical node j from the memory of the logical node i；

The migration units 703, for if it is determined that the data that the process P0 is accessed meet transition condition, by the process The data that P0 is accessed are migrated from the caching of the logical node j into the memory of the logical node j.

Specifically, with reference to Fig. 8, which further includes：Judging unit 704；

The judging unit 704, for judging the logical node i and logical node j whether in same physics section Point；

The copied cells 702 is specifically used for：

Optionally, the copied cells 702 is additionally operable to：

If the logical node i and logical node j is patrolled in same physical node, the process P0 access described The data in the processor high speed buffer storage of node i are collected, from the processor high speed buffer storage of the logical node i It copies in the processor high speed buffer storage of the logical node j.

Optionally, with reference to Fig. 9, which further includes：Transmitting element 705, the transmitting element 705, for being patrolled to all Volume node sends the first notification message, first notification message be used to the process P0 be notified to access in the logical node Data in the processor high speed buffer storage of i are copied in the processor high speed buffer storage of the logical node j.

Specifically, with reference to Figure 10, which further includes：Establish unit 706；

It is described to establish unit 706, for establishing virtual address of the data in the logical node j of the process P0 access With the mapping relations of physical address.

An embodiment of the present invention provides a kind of data migration device, which includes：Determination unit, copied cells and migration Unit；The determination unit is when process P0 moves to logical node j from logical node i, according to the number of process P0 access According to the virtual address in logical node i, the physical address of data that the process P0 accesses in the logical node i is determined；Institute Copied cells is stated according to the data that the P0 is accessed in the physical address of the logical node i, the number that the process P0 is accessed It is copied to according to from the memory of the logical node i in the caching of the logical node j；The migration units are in the process P0 When the data of access meet transition condition, the caching of process P0 data from the logical node j accessed is migrated to institute In the memory for stating logical node j.Based on the present invention, purpose logical node can be migrated to from source logical node in a process Afterwards, when the data that the process accesses meet transition condition, quickly by the data that the process accesses from the purpose logic The caching of node is moved in the memory of the purpose logical node, so as to improve the speed of Data Migration, and then improves system Overall performance.

An embodiment of the present invention provides a kind of computer system, with reference to Figure 11, including：

Multiple physical nodes 1101, wherein, each physical node is divided into one or more logical nodes, each logic Node is assigned first processor 1102, the first memory 1103, first processor cache memory 1104 and caching 1105；

Node control chip 1106 for connecting two physical nodes, carries out data between described two physical nodes It replicates；

NUMA managers 1107, by bus 1108, the second processor 1109 being connected with bus and be connected with bus Two memories 1110 form, wherein, the second processor 1109 is connected with all physical nodes, for the physics Node is managed, and second memory 1110 is used to store the instruction that the needs of second processor 1109 call, described total Line 1108 is used to implement the connection communication between the second processor 1109 and second memory 1110.

Specifically, the bus 1108 can be industry standard architecture (Industry Standard Architecture, referred to as ISA) bus, external equipment interconnection (Peripheral Component, referred to as PCI) bus Or extended industry-standard architecture (Extended Industry Standard Architecture, referred to as EISA) is total Line etc..The bus 1108 can be divided into address bus, data/address bus, controlling bus etc..For ease of representing, only with one in Figure 11 Thick line represents, it is not intended that an only bus or a type of bus.

For second memory 1110 for storing executable program code, which includes computer-managed instruction. Second memory 1110 may include high-speed RAM memory, it is also possible to further include nonvolatile memory (non-volatile Memory), a for example, at least magnetic disk storage.

Specifically, the first processor 1102 and second processor 1109 may be a central processing unit (Central Processing Unit, referred to as CPU) or specific integrated circuit (Application Specific Integrated Circuit, referred to as ASIC) or be arranged to implement the embodiment of the present invention one or more integrated circuits.

Specifically, the second processor 1109 is used for：

When process P0 moves to logical node j from logical node i, the data accessed according to the process P0 are in logic section The virtual address of point i determines physical address of the data in the logical node i of the process P0 access；

According to the data that the P0 is accessed in the physical address of the logical node i, the data that the process P0 is accessed The caching 1105 of the logical node j is copied to from the first memory 1103 of the logical node i；

If it is determined that the data that the process P0 is accessed meet transition condition, the process P0 data accessed are patrolled from described The caching 1105 for collecting node j is migrated into the first memory 1103 of the logical node j.

Specifically, the second processor 1109 is additionally operable to：

If the logical node i and the logical node j are sent not in same physical node to node control chip 1106 Notification message, the notification message include the data of process P0 access in the physical address of the logical node i, the section Point control chip 1106 respectively with the physical node where the logical node i and the physical node where the logical node j Be connected so that the node control chip by the data that the process P0 is accessed from the first memory of the logical node i The caching 1105 of the logical node j is copied in 1103；

If in same physical node, the process P0 data accessed are answered by the logical node i and logical node j Make the caching 1105 of the logical node j.

Optionally, the second processor 1109 is additionally operable to whether judge the logical node i and logical node j In same physical node；

If the logical node i and the logical node j are sent not in same physical node to node control chip 1106 Notification message, in the notification message comprising the data that the process P0 is accessed the logical node i physical address so that Obtain the processor high speed buffer storage 1104 in the logical node i that the node control chip accesses the process P0 In data, the processing of the logical node j is copied to from the processor high speed buffer storage 1104 of the logical node i In device cache memory 1104；

If the logical node i and logical node j is patrolled in same physical node, the process P0 access described The data in the processor high speed buffer storage 1104 of node i are collected, from the processor high speed buffer-stored of the logical node i It is copied in device 1104 in the processor high speed buffer storage 1104 of the logical node j；

The first notification message is sent to all logical nodes, first notification message is used to that the process P0 to be notified to access The data in the processor high speed buffer storage 1104 of the logical node i be copied to the place of the logical node j It manages in device cache memory 1104.

Specifically, the second processor 1109 is additionally operable to：The data of the process P0 access are established in the logic section The virtual address of point j and the mapping relations of physical address.

It, can be in a process from source based on the computer system an embodiment of the present invention provides a kind of computer system After logical node is migrated to purpose logical node, when the data that the process accesses meet transition condition, quickly by described in The data that process accesses promote the speed of Data Migration from the memory that the caching of the destination node moves to the destination node Degree, and then improve systematic entirety energy.

The above description is merely a specific embodiment, but protection scope of the present invention is not limited thereto, any Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in change or replacement, should all contain Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.

Claims

1. a kind of data migration method, which is characterized in that NUMA architecture is by multiple physical nodes, node control chip and NUMA pipes Device is managed to form, wherein, each physical node is divided into one or more logical nodes, and each logical node is assigned first Processor, the first memory, first processor cache memory and caching；The node control chip is for two objects of connection Node is managed, carries out the duplication of data between described two physical nodes；The NUMA managers by bus, are connected with bus Second processor and the second memory composition being connected with bus, wherein, the second processor and all physical node phases Connection, for being managed to the physical node, second memory is used to store what the second processor needs called Instruction, this method are applied to the NUMA managers, and this method includes：

In process P0 after logical node i moves to logical node j, the data accessed according to the process P0 are in logical node i Virtual address, determine the physical address of data that the process P0 accesses in the logical node i；

According to the data that the P0 is accessed in the physical address of the logical node i, the data that the process P0 is accessed are from institute State the caching that the logical node j is copied in the first memory of logical node i；

If the data that the process P0 is accessed meet transition condition, by the data that the process P0 is accessed from the logical node j Caching migrate into the first memory of the logical node j.

2. according to the method described in claim 1, it is characterized in that, described move to logic section in process P0 from logical node i During point j, according to the data that the process P0 is accessed in the virtual address of logical node i, the data that the process P0 is accessed are determined After the physical address of the logical node i, this method further includes：

If the logical node i and the logical node j in same physical node, do not send to the node control chip and notify Message, the notification message include the data of process P0 access in the physical address of the logical node i, the node control Coremaking piece is connected respectively with the physical node where the logical node i and the physical node where the logical node j, so that Described in the node control chip copies to from the first memory of the logical node i data that the process P0 is accessed The caching of logical node j；

If in same physical node, the process P0 data accessed are copied to by the logical node i and logical node j The caching of the logical node j.

3. according to the method described in claim 1, it is characterized in that, described move to logic section in process P0 from logical node i During point j, according to the data that the process P0 is accessed in the virtual address of logical node i, the data that the process P0 is accessed are determined After the physical address of the logical node i, this method further includes：

If the logical node i and the logical node j in same physical node, do not send notice to node control chip and disappear It ceases, physical address of the data in the logical node i of process P0 access is included in the notification message, so that described The number in the first processor cache memory of the logical node i that node control chip accesses the process P0 According to copying to the first processor of the logical node j from the first processor cache memory of the logical node i In cache memory；

If the logical node i and logical node j in same physical node, the process P0 access in the logic section Data in the first processor cache memory of point i, from the first processor caches of the logical node i It is copied in device in the first processor cache memory of the logical node j；

Send the first notification message to all logical nodes, first notification message be used to the process P0 be notified to access Data in the first processor cache memory of the logical node i are copied at the first of the logical node j It manages in device cache memory.

4. according to claim 1-3 any one of them methods, which is characterized in that described if it is determined that the number that the process P0 is accessed According to transition condition is met, the caching of process P0 data from the logical node j accessed is migrated to the logical node j The first memory in after, this method further includes：

The data of the process P0 access are established in the virtual address of the logical node j and the mapping relations of physical address.

5. a kind of data migration device, which is characterized in that the device includes：Determination unit, copied cells and migration units；

The determination unit, for after logical node i moves to logical node j, being accessed in process P0 according to the process P0 Data in the virtual address of logical node i, determine data that the process P0 is accessed in the logical node i physically Location；

The copied cells, for according to the data that the P0 is accessed the logical node i physical address, by the process The data that P0 is accessed copy to the caching of the logical node j from the memory of the logical node i；

The migration units, if meeting transition condition for the process P0 data accessed, the number that the process P0 is accessed It is migrated according to from the caching of the logical node j into the memory of the logical node j.

6. device according to claim 5, which is characterized in that the device further includes：Judging unit；

The copied cells is specifically used for：

If the logical node i and the logical node j in same physical node, do not send notice to node control chip and disappear Breath, the notification message include the data of process P0 access in the physical address of the logical node i, the node control Chip is connected respectively with the physical node where the logical node i and the physical node where the logical node j, so that The data that the process P0 is accessed are copied to the logic section by the node control chip from the memory of the logical node i The caching of point j；

7. device according to claim 5, which is characterized in that the copied cells is additionally operable to：

If the logical node i and the logical node j in same physical node, do not send notice to node control chip and disappear It ceases, physical address of the data in the logical node i of process P0 access is included in the notification message, so that described The data in the processor high speed buffer storage of the logical node i that node control chip accesses the process P0, The processor high speed buffering that the logical node j is copied to from the processor high speed buffer storage of the logical node i is deposited In reservoir；

If the logical node i and logical node j in same physical node, the process P0 access in the logic section Data in the processor high speed buffer storage of point i are replicated from the processor high speed buffer storage of the logical node i Into the processor high speed buffer storage of the logical node j；

The device further includes：Transmitting element；

The transmitting element, for sending the first notification message to all logical nodes, first notification message is used to notify The data in the processor high speed buffer storage of the logical node i that the process P0 is accessed are copied to the logic In the processor high speed buffer storage of node j.

8. according to claim 5-7 any one of them devices, which is characterized in that the device further includes：Establish unit；

It is described to establish unit, for establishing virtual address and physics of the data in the logical node j of the process P0 access The mapping relations of address.

9. a kind of computer system, which is characterized in that including：

Multiple physical nodes, wherein, each physical node is divided into one or more logical nodes, and each logical node is divided Equipped with first processor, the first memory, first processor cache memory and caching；

NUMA managers, by bus, the second processor being connected with bus and the second memory being connected with bus composition, wherein, The second processor is connected with all physical nodes, for being managed to the physical node, in described second It deposits to store the instruction that the second processor needs call；

The second processor calls executing instruction in second memory by the bus, for：

If it is determined that the data that the process P0 is accessed meet transition condition, by the data that the process P0 is accessed from the logic section The caching of point j is migrated into the first memory of the logical node j.

10. computer system according to claim 9, which is characterized in that move to logic from logical node i in process P0 During node j, according to the data that the process P0 is accessed in the virtual address of logical node i, the number that the process P0 is accessed is determined According to after the physical address of the logical node i, the second processor is called by the bus in second memory Instruction, is specifically used for：

11. computer system according to claim 9, which is characterized in that move to logic from logical node i in process P0 During node j, according to the data that the process P0 is accessed in the virtual address of logical node i, the number that the process P0 is accessed is determined According to after the physical address of the logical node i, the second processor is called by the bus in second memory It executes instruction, for：

12. according to claim 9-11 any one of them computer systems, which is characterized in that described if it is determined that the process P0 The data of access meet transition condition, and the caching of process P0 data from the logical node j accessed is migrated to described After in the first memory of logical node j, the second processor calls executing instruction in second memory, for：