CN104902560A - Method and device for downlink timing synchronization - Google Patents
Method and device for downlink timing synchronization Download PDFInfo
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- CN104902560A CN104902560A CN201410081625.5A CN201410081625A CN104902560A CN 104902560 A CN104902560 A CN 104902560A CN 201410081625 A CN201410081625 A CN 201410081625A CN 104902560 A CN104902560 A CN 104902560A
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Abstract
The invention discloses a method and a device for downlink timing synchronization, which are used for reducing computational complexity for PSS (Primary Synchronous Signal) detection in a downlink timing synchronization process so as to reduce hardware implementation complexity and save cost. The method comprises the following steps of dividing a downlink signal into a plurality of sub-signals, wherein the lengths of the sub-signals are not smaller than twice of the length of a primary synchronous signal PSS sequence included in each half frame of the downlink signal, every two adjacent sub-signals are overlapped with each other, and the length of the signals at an overlapping portion is equal to the length of the PSS sequence included in each half frame of the downlink signal; after converting each sub-signal to a frequency domain, carrying out conjugate point multiplication on the converted sub-signal and a preset PSS sequence of the frequency domain, converting each result sequence obtained through point multiplication to a time domain and recombining the result sequences into a time domain sequence; and determining a correlation peak value position of each time domain sequence, determining a timing synchronization position according to the correlation peak value position and carrying out timing synchronization.
Description
Technical field
The present invention relates to communication technical field, particularly relate to a kind of descending time synchronization method and device.
Background technology
Adopt OFDM (OFDM) as downlink transmission scheme in Long Term Evolution (LTE) system, OFDM is as Multicarrier Transmission Technology, parallel transmission message data on orthogonal subcarriers, the only orthogonality of guaranteed subcarrier, OFDM can play its advantage, when orthogonality can not get fully ensureing, systematic function can decline because of intersymbol interference (ISI) and inter-carrier interference (ICI).
Be provided with master sync signal (PSS) in the frame structure of LTE system, PSS signal not only for time and Frequency Synchronization, and provides sequence number in the group of physical-layer cell for subscriber equipment (UE).The first step work of UE down-going synchronous is exactly obtain Timing Synchronization point by PSS Sequence Detection.
In Frequency Division Duplexing (FDD) (FDD) community, PSS is positioned at last OFDM symbol of the 1st and the 11st time slot of radio frames; In TDD cell, PSS is positioned on the 3rd of radio frames and the 13rd time slot.Visible, every half radio frames (hereinafter referred to as field) just has a PSS sequence.
For additive white Gaussian noise (AWGN) channel circumstance, the process utilizing PSS to carry out timing estimation is described below.
Suppose that Received signal strength is expressed as: r (t)=s (t)+w (t), wherein, s (t) expression transmits, and r (t) represents Received signal strength, and w (t) represents additive white Gaussian noise.
First, sample to received signal in the k moment, obtain: r (k)=s (k)+w (k);
Then, filtering is carried out and down-sampling obtains x (k) to the Received signal strength after sampling;
Secondly, carry out computing cross-correlation by 3 the time domain PSS signals preserved with this locality and obtain timing synchronization position, the concrete formula of computing cross-correlation is:
Wherein,
represent the u(u=0 that UE receiver is preserved in advance, 1,2) time domain waveform of individual PSS signal, τ represents the side-play amount of Received signal strength, and K represents the sequence length (namely participating in the data length of related operation) of PSS signal.Pass through
with the computing cross-correlation of Received signal strength sequence x (k+ τ), find the peak Pos that the value of each u is corresponding
u, be expressed as Pos
u1, Pos
u2and Pos
u3.Then compare the size of these three peak values, PSS burst corresponding to maximum is the PSS burst that Received signal strength carries, and the value according to the u of PSS burst corresponding to maximum can determine sequence number in cell set.Meanwhile, the side-play amount τ that maximum is corresponding is the initial timing synchronization position detected.
As can be seen from computing cross-correlation formula, for certain u value, each deviation post will be the related operation of K corresponding to a length.In the initial cell search stage, must carry out computing cross-correlation in the time span of field (5 milliseconds) and just can guarantee to find PSS sequence, namely the length of deviation post reaches the data length of field.Although can be reduced the data length in field by down-sampling, amount of calculation is still very huge, and this just makes, and actual hardware system complexity is high, detection time is long.
Such as, suppose the down-sampling rate of employing 16 times, PSS data length K=128, sample later half frame data length H=9600, namely needs to carry out 9600 computing cross-correlations.Corresponding 128*9600=1,228,800 complex multiplication operations, amount of calculation is very huge.
For this problem, in existing innovatory algorithm, field time-domain received signal after down-sampling is transformed to frequency domain by leaf transformation (DFT) in H point discrete Fourier, then the frequency domain PSS sequence conjugate dot product prestored with this locality, by leaf inverse transformation (IDFT) in H point discrete Fourier, conjugation dot product result is switched back to time domain again, complete cross-correlation calculation.But still need the DFT/IDFT computing of counting greatly, very large to hardware implementing expense.Such as, suppose that the Received signal strength after the down-sampling rate of employing 16 times carries out PSS detection, still need the DFT/IDFT arithmetic element of 9600.
As can be seen here, the computation complexity of existing PSS Sequence Detection is high, and hardware implementing is complicated, cost is high.
Summary of the invention
The invention provides a kind of descending time synchronization method and device, for reducing the computation complexity that PSS in descending timing synchronization procedure detects, reduce hardware implementing complexity and cost-saving.
The concrete technical scheme that the embodiment of the present invention provides is as follows:
A kind of descending time synchronization method, comprising:
Downstream signal is divided into multiple subsignal, the length of described subsignal is not less than the twice of the master sync signal PSS sequence length comprised in downstream signal described in every field, and often adjacent two subsignals are overlapped, lap signal length equals the described PSS sequence length comprised in downstream signal described in every field;
After each described subsignal is transformed into frequency domain, respectively with the frequency domain PSS sequence conjugate dot product preset, each result sequence obtained after dot product is transformed into time domain and is reassembled as time domain sequences;
Determine the correlation peak location of each described time domain sequences, carry out Timing Synchronization according to described correlation peak location determination timing synchronization position.
A kind of descending timing synchronization device, comprising:
Segment processing module, for downstream signal is divided into multiple subsignal, the length of described subsignal is not less than the twice of the master sync signal PSS sequence length comprised in downstream signal described in every field, and often adjacent two subsignals are overlapped, lap signal length equals the described PSS sequence length comprised in downstream signal described in every field;
Time-frequency domain modular converter, after each described subsignal for described segment processing module being obtained being transformed into frequency domain, respectively with described default frequency domain PSS sequence conjugate dot product, being transformed into time domain by each result sequence obtained after dot product and being reassembled as time domain sequences;
Determination module, for determining the correlation peak location of each described time domain sequences, carries out Timing Synchronization according to described correlation peak location determination timing synchronization position.
Based on technique scheme, in the embodiment of the present invention, by downstream signal is divided into multiple subsignal, after each subsignal is transformed into frequency domain, respectively with the frequency domain PSS sequence conjugate dot product preset, the each result sequence obtained after dot product is transformed into time domain and is reassembled as time domain sequences, calculate the correlation peak location of each described time domain sequences, Timing Synchronization is carried out according to correlation peak location determination timing synchronization position, to reduce in PSS Sequence Detection process counting of computing in time-frequency domain transfer process, reduce computation complexity, reduce hardware implementing complexity, be conducive to hardware implementing, save hardware implementation cost.
Accompanying drawing explanation
Fig. 1 is the method flow schematic diagram of descending Timing Synchronization in the embodiment of the present invention;
Fig. 2 is the method flow diagram of descending Timing Synchronization in the specific embodiment of the invention;
Fig. 3 is downstream signal segmentation process schematic diagram in the embodiment of the present invention;
Fig. 4 is the structural representation of descending timing synchronization device in the embodiment of the present invention;
Fig. 5 is the structural representation of the FFT/IFFT module of the multiplexing OFDM demodulation of descending timing synchronization device in the embodiment of the present invention.
Embodiment
In order to reduce the computation complexity that PSS in descending timing synchronization procedure detects, reducing hardware implementing complexity and cost-saving, embodiments providing a kind of descending time synchronization method and device.
Below in conjunction with accompanying drawing, the preferred embodiment of the present invention is described in detail.
In following examples, be example for the descending timing synchronization procedure in LTE system, not as limit in practical application, for other by carrying the system that PSS sequence carries out Timing Synchronization in downstream signal, the method that the embodiment of the present invention provides also can be adopted.
As shown in Figure 1, in the embodiment of the present invention, the method detailed flow process of carrying out descending Timing Synchronization is as follows:
Step 101: downstream signal is divided into multiple subsignal, the length of subsignal is not less than the twice of the master sync signal PSS sequence length comprised in every field downstream signal, and often adjacent two subsignals are overlapped, lap signal length equals the described PSS sequence length comprised in every field downstream signal.
Preferably, according to the sequence length of the frequency domain master sync signal PSS preserved in advance, downstream signal is divided into multiple subsignal, the sequence length of subsignal equals the sequence length of frequency domain master sync signal PSS.
Preferably, if last subsignal sequence length is less than the sequence length of frequency domain master sync signal PSS, the sequence length of last subsignal is made to equal the sequence length of frequency domain master sync signal PSS by zero padding.
Preferably, before downstream signal is divided into each subsignal, carry out filtering to received signal and down-sampling obtains downstream signal.
Particularly, PSS is positioned at 6 Resource Block (RB) positions at frequency domain center, removes out-of-band noise by carrying out filtering to received signal.
Wherein, carry out down-sampling process to filtered signal, reduce intraframe data length, to reach the object reducing integral operation amount, in the embodiment of the present invention, the signal indication after down-sampling process is x (k).
In the embodiment of the present invention, the downstream signal in step 101 is obtained after carrying out down-sampling process, this downstream signal comprises signal section except PSS and PSS part, wherein suppose that the sequence length of signal section is H, the sequence length of PSS part is P, when downstream signal is divided into subsignal, the sequence length of subsignal is not less than 2P, and the sequence length of the lap of adjacent two subsignals equals P.
Step 102: after each subsignal is transformed into frequency domain, respectively with the frequency domain PSS sequence conjugate dot product preset, is transformed into time domain by each result sequence obtained after dot product and is reassembled as time domain sequences.
Particularly, for the frequency domain PSS sequence preset arbitrarily, will obtain after each result sequence is transformed into time domain after dot product, the sequencing occurred in downstream signal according to each subsignal be reassembled as time domain sequences.
Preferably, adopt fast Fourier transform FFT that subsignal is transformed into frequency domain; And adopt inverse fast Fourier transform IFFT, the result sequence obtained after being transformed into the signal after frequency domain and the frequency domain PSS sequence conjugate dot product preset is transformed into time domain.In the embodiment of the present invention, time-domain and frequency-domain transfer algorithm is not limited in FFT/IFFT, and also may be used for of the present invention for other time-domain and frequency-domain transfer algorithm, the present invention is also included.
Step 103: the correlation peak location determining each time domain sequences, carries out Timing Synchronization according to this correlation peak location determination timing synchronization position.
In a specific implementation, calculate and compare the correlation peak location square determining this time domain sequences of the mould of each element in time domain sequences, select to make the sequence number of PSS corresponding to square correlation peak location maximum in each time domain sequences of the mould of corresponding element, that comprise in time domain sequences as sequence number in cell set, this correlation peak location of selection is timing synchronization position.
Shown in Fig. 2, carry out complete detailed description by the process of a specific embodiment to the descending Timing Synchronization that the embodiment of the present invention provides.
Step 201: carry out filtering to received signal.
Particularly, PSS is positioned at the position of 6 Resource Block (RB) at frequency domain center, removes out-of-band noise by filtering.
Step 202: down-sampling process is carried out to filtered Received signal strength and obtains downstream signal.
Wherein, the downstream signal obtained after supposing down-sampling is x (k), intraframe data length is reduced by down-sampling, reach the object reducing integral operation amount, suppose the length of the signal section except PSS comprised in down-sampled rear every field downstream signal be H, PSS part sequence length be P.
Step 203: carry out time-frequency domain conversation process after segment processing is carried out to downstream signal.
S2031: carrying out segment processing to downstream signal is multiple subsignal.
In a specific implementation, the downstream signal segment processing being (H+P) by every half frame length is multiple subsignal, as shown in Figure 3, suppose that the sequence length of every cross-talk signal is L, then L is more than or equal to 2P, wherein the value of L is converted to principle to be suitable for time-domain and frequency-domain, supposes to adopt fast Fourier transform FFT and inverse fast Fourier transform IFFT to carry out time-domain and frequency-domain conversion, then the value of L is embodied as principle to be suitable for FFT/IFFT.Often there is overlapping part between adjacent two cross-talk signals, then the sequence length of overlapping part equals P, corresponding final stage subsignal, if the sequence length of this cross-talk signal is less than L, then by making the sequence length of this subsignal reach length L in this segment signal trailing zero.Suppose that the subsignal after segmentation is expressed as x
s(k), wherein s=1,2 ... S, S are the number of the subsignal that the segmentation of every field downstream signal obtains.
S2032: by L point FFT respectively by the subsignal x after segmentation
sk () transforms to frequency domain.
Be formulated as: x
s, freq(i)=fft (x
s(k)), wherein, fft (x
s(k)) represent sub-signal x
sk () carries out FFT computing, x
s, freqi () represents the subsignal after transforming to frequency domain.
S2033: u the length prestored with this locality is respectively that the frequency domain PSS sequence conjugate dot product of L obtains each result sequence.
Be formulated as:
Wherein
represent that u length is the frequency domain PSS sequence of L.
S2034: convert respectively by L point IFFT, returns the result sequence transformation that dot product obtains to time domain.
Be formulated as:
Wherein,
represent and IFFT computing is carried out to result sequence.
S2035: by S section time domain
the data recombination time domain sequences that to be every half frame length be (H+P).
Be expressed as:
Step 204: calculate restructuring obtain each time domain sequences mould square.
Formula is expressed as:
Step 205: determine correlation peak location, obtains sequence number in timing synchronization position and cell set.
Particularly, calculate u=0 respectively, 1, correlation peak location Pos when 2
u, computing formula is:
Wherein, 3
in u corresponding to maximum be sequence number in cell set, the Pos corresponding to this maximum
ube Timing Synchronization point position.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of descending timing synchronization device, and as shown in Figure 4, the concrete enforcement of this device can see the description of said method part, and this device mainly comprises:
Segment processing module 401, for downstream signal is divided into multiple subsignal, the length of subsignal is not less than the twice of the master sync signal PSS sequence length comprised in every field downstream signal, and often adjacent two subsignals are overlapped, lap signal length equals the PSS sequence length comprised in every field downstream signal;
Time-frequency domain modular converter 402, after each described subsignal for segment processing module being obtained being transformed into frequency domain, respectively with the frequency domain PSS sequence conjugate dot product preset, being transformed into time domain by each result sequence obtained after dot product and being reassembled as time domain sequences;
Determination module 403, for determining the correlation peak location of each described time domain sequences, carries out Timing Synchronization according to correlation peak location determination timing synchronization position.
Preferably, segment processing module 401 specifically for:
According to the sequence length of the frequency domain master sync signal PSS preserved in advance, downstream signal is divided into multiple subsignal, the sequence length of described subsignal equals the sequence length of described frequency domain master sync signal PSS.
Preferably, segment processing module 401 specifically for:
If last subsignal sequence length is less than the sequence length of described frequency domain master sync signal PSS, the sequence length of last subsignal described is made to equal the sequence length of described frequency domain master sync signal PSS by zero padding.
Preferably, also comprise interconnective filtration module 404 and down sample module 405, described down sample module is connected with described segment processing module;
Described filtration module, for carrying out filtering to received signal;
Described down sample module, obtains described downstream signal for carrying out down-sampling to the filtered signal of described filtration module.
Preferably, time-frequency domain modular converter 402 specifically for:
To obtain after each result sequence is transformed into time domain after dot product, the sequencing occurred in described downstream signal according to the described subsignal of correspondence be reassembled as time domain sequences.
Preferably, time-frequency domain modular converter 402 comprises fast Fourier transform FFT/ inverse fast Fourier transform IFFT submodule 4021 and multiplication submodule 4022;
FFT/IFFT submodule 4021, is transformed into frequency domain for adopting fft algorithm by each described subsignal that described segment processing Module Division obtains; And the described result sequence adopting IFFT algorithm to be obtained by described multiplication submodule is transformed into time domain;
Multiplication submodule 4022, is transformed into the subsignal after frequency domain and described default frequency domain PSS sequence conjugate dot product for what exported by described FFT/IFFT submodule, obtains described result sequence and export to described FFT/IFFT submodule.
Preferably, determination module 403 comprises sequence number acquisition submodule 4033 in modulus value square calculating sub module 4031, Timing Synchronization acquisition submodule 4032 and cell set;
Wherein, modulus value square calculating sub module 4031, for calculate time-frequency domain modular converter 402 export each time domain sequences in each element mould square, determine the correlation peak location of each time domain sequences;
Timing Synchronization obtains submodule 4032, makes square correlation peak location maximum in each time domain sequences of the mould of corresponding element as timing synchronization position for selecting;
In cell set, sequence number obtains submodule 4033, makes the sequence number of PSS corresponding to square correlation peak location maximum in each time domain sequences of the mould of corresponding element, that comprise in time domain sequences as sequence number in cell set for selecting.
Preferably, as shown in Figure 5, FFT/IFFT submodule 4021 is the FFT/IFFT module for OFDM demodulation comprised in OFDM receiver.Particularly, segment processing module 401, multiplication submodule 4022 and determination module 403 are connected to the FFT/IFFT module comprised in receiver respectively through multidiameter option switch 406.
In the descending OFDM receiver of LTE, the maximum number of points that the FFT/IFFT module for OFDM demodulation of main data path can carry out FFT/IFFT computing is 2048 points, in PSS detection method of the prior art, the minimum DFT/IDFT computing needing employing 9600, cannot for the FFT/IFFT module of OFDM demodulation in multiplexing OFDM receiver.
In the embodiment of the present invention, reduce counting of FFT/IFFT computing.Such as, after the down-sampling rate of employing 16 times carries out down-sampling, as long as minimum 256 points of FFT/IFFT computing, this just provides possibility for realizing with the FFT/IFFT module reuse for OFDM demodulation in main data path.The FFT/IFFT module being used for OFDM demodulation in main data path is used for the device that the embodiment of the present invention provides, can for reduce hardware spending further, cost-saving.
Based on technique scheme, in the embodiment of the present invention, by downstream signal is divided into multiple subsignal, for the frequency domain PSS sequence preset arbitrarily, after each subsignal is transformed into frequency domain, respectively with the frequency domain PSS sequence conjugate dot product preset, the each result sequence obtained after dot product is transformed into time domain and is reassembled as time domain sequences, calculate the correlation peak location of each described time domain sequences, Timing Synchronization is carried out according to correlation peak location determination timing synchronization position, to reduce in PSS Sequence Detection process counting of computing in time-frequency domain transfer process, reduce computation complexity, reduce hardware implementing complexity, be conducive to hardware implementing, save hardware implementation cost.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (13)
1. a descending time synchronization method, is characterized in that, comprising:
Downstream signal is divided into multiple subsignal, the length of described subsignal is not less than the twice of the master sync signal PSS sequence length comprised in downstream signal described in every field, and often adjacent two subsignals are overlapped, lap signal length equals the described PSS sequence length comprised in downstream signal described in every field;
After each described subsignal is transformed into frequency domain, respectively with the frequency domain PSS sequence conjugate dot product preset, each result sequence obtained after dot product is transformed into time domain and is reassembled as time domain sequences;
Determine the correlation peak location of each described time domain sequences, carry out Timing Synchronization according to described correlation peak location determination timing synchronization position.
2. the method for claim 1, is characterized in that, downstream signal is divided into multiple subsignal, comprises:
According to the sequence length of the frequency domain master sync signal PSS preserved in advance, downstream signal is divided into multiple subsignal, the sequence length of described subsignal equals the sequence length of described frequency domain master sync signal PSS.
3. method as claimed in claim 2, is characterized in that, according to the sequence length of the frequency domain master sync signal PSS preserved in advance, downstream signal is divided into multiple subsignal, comprises:
If last subsignal sequence length is less than the sequence length of described frequency domain master sync signal PSS, the sequence length of last subsignal described is made to equal the sequence length of described frequency domain master sync signal PSS by zero padding.
4. the method as described in claim 1,2 or 3, is characterized in that, before downstream signal is divided into each subsignal, also comprises:
Carry out filtering to received signal and down-sampling obtains described downstream signal.
5. method as claimed in claim 4, is characterized in that, each result sequence obtained is transformed into time domain and is reassembled as time domain sequences, comprising after dot product:
To obtain after each result sequence is transformed into time domain after dot product, the sequencing occurred in described downstream signal according to each subsignal be reassembled as time domain sequences.
6. a descending timing synchronization device, is characterized in that, comprising:
Segment processing module, for downstream signal is divided into multiple subsignal, the length of described subsignal is not less than the twice of the master sync signal PSS sequence length comprised in downstream signal described in every field, and often adjacent two subsignals are overlapped, lap signal length equals the described PSS sequence length comprised in downstream signal described in every field;
Time-frequency domain modular converter, after each described subsignal for described segment processing module being obtained being transformed into frequency domain, respectively with the frequency domain PSS sequence conjugate dot product preset, being transformed into time domain by each result sequence obtained after dot product and being reassembled as time domain sequences;
Determination module, for determining the correlation peak location of each described time domain sequences, carries out Timing Synchronization according to described correlation peak location determination timing synchronization position.
7. device as claimed in claim 6, is characterized in that, described segment processing module specifically for:
According to the sequence length of the frequency domain master sync signal PSS preserved in advance, downstream signal is divided into multiple subsignal, the sequence length of described subsignal equals the sequence length of described frequency domain master sync signal PSS.
8. device as claimed in claim 7, is characterized in that, described segment processing module specifically for:
If last subsignal sequence length is less than the sequence length of described frequency domain master sync signal PSS, the sequence length of last subsignal described is made to equal the sequence length of described frequency domain master sync signal PSS by zero padding.
9. the device as described in claim 6,7 or 8, is characterized in that, also comprises interconnective filtration module and down sample module, and described down sample module is connected with described segment processing module;
Described filtration module, for carrying out filtering to received signal;
Described down sample module, obtains described downstream signal for carrying out down-sampling to the filtered signal of described filtration module.
10. device as claimed in claim 9, is characterized in that, described time-frequency domain modular converter specifically for:
To obtain after each result sequence is transformed into time domain after dot product, the sequencing occurred in described downstream signal according to the described subsignal of correspondence be reassembled as time domain sequences.
11. devices as claimed in claim 10, it is characterized in that, described time-frequency domain modular converter comprises fast Fourier transform FFT/ inverse fast Fourier transform IFFT submodule and multiplication submodule;
Described FFT/IFFT submodule, is transformed into frequency domain for each described subsignal described segment processing Module Division obtained; And the described result sequence that described multiplication submodule obtains is transformed into time domain;
Described multiplication submodule, is transformed into the subsignal after frequency domain and described default frequency domain PSS sequence conjugate dot product for what exported by described FFT/IFFT submodule, obtains described result sequence and export to described FFT/IFFT submodule.
12. devices as claimed in claim 11, is characterized in that, described FFT/IFFT submodule is the FFT/IFFT module for OFDM demodulation comprised in OFDM receiver.
13. devices as claimed in claim 12, is characterized in that, described segment processing module, described multiplication submodule and described determination module are connected to the described FFT/IFFT module comprised in described receiver respectively through multidiameter option switch.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107105497A (en) * | 2017-06-07 | 2017-08-29 | 重庆重邮汇测通信技术有限公司 | Master sync signal detection method in a kind of LTE system |
| CN107592668A (en) * | 2016-07-07 | 2018-01-16 | 华为技术有限公司 | The method and apparatus of transmission signal |
| CN108173798A (en) * | 2016-12-07 | 2018-06-15 | 上海朗帛通信技术有限公司 | A kind of method and apparatus in wireless communication |
| WO2018141231A1 (en) * | 2017-01-31 | 2018-08-09 | 上海朗帛通信技术有限公司 | Ue and base station method and apparatus for wireless communication |
| CN110677364A (en) * | 2019-09-17 | 2020-01-10 | 广州粒子微电子有限公司 | Method and device for detecting main synchronization signal |
| CN110881012A (en) * | 2019-11-18 | 2020-03-13 | 展讯通信（上海）有限公司 | Time estimation method and device for OFDM modulation signal |
| CN112597432A (en) * | 2020-12-28 | 2021-04-02 | 华力智芯(成都)集成电路有限公司 | Method and system for realizing acceleration of complex sequence cross-correlation on FPGA (field programmable Gate array) based on FFT (fast Fourier transform) algorithm |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102158249A (en) * | 2010-02-11 | 2011-08-17 | 富士通株式会社 | Method and device for detecting a master synchronization sequence |
| CN102231893A (en) * | 2011-06-21 | 2011-11-02 | 北京交通大学 | LTE (long term evolution) synchronization signal detection method |
-
2014
- 2014-03-06 CN CN201410081625.5A patent/CN104902560B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102158249A (en) * | 2010-02-11 | 2011-08-17 | 富士通株式会社 | Method and device for detecting a master synchronization sequence |
| CN102231893A (en) * | 2011-06-21 | 2011-11-02 | 北京交通大学 | LTE (long term evolution) synchronization signal detection method |
Non-Patent Citations (1)
| Title |
|---|
| 漆飞: "《LTE系统中一种低复杂度的PSS定时同步算法》", 《太赫兹科学与电子信息学报》 * |
Cited By (14)
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| CN108173798A (en) * | 2016-12-07 | 2018-06-15 | 上海朗帛通信技术有限公司 | A kind of method and apparatus in wireless communication |
| CN108173798B (en) * | 2016-12-07 | 2020-07-31 | 上海朗帛通信技术有限公司 | Method and device in wireless communication |
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| US11032050B2 (en) | 2017-01-31 | 2021-06-08 | Shanghai Langbo Communication Technology Company Limited | Method and device for grant-free transmission in UE and base station for wireless communication |
| CN107105497B (en) * | 2017-06-07 | 2019-11-29 | 重庆重邮汇测通信技术有限公司 | Primary synchronization signal detection method in a kind of LTE system |
| CN107105497A (en) * | 2017-06-07 | 2017-08-29 | 重庆重邮汇测通信技术有限公司 | Master sync signal detection method in a kind of LTE system |
| CN110677364A (en) * | 2019-09-17 | 2020-01-10 | 广州粒子微电子有限公司 | Method and device for detecting main synchronization signal |
| CN110881012A (en) * | 2019-11-18 | 2020-03-13 | 展讯通信（上海）有限公司 | Time estimation method and device for OFDM modulation signal |
| CN110881012B (en) * | 2019-11-18 | 2022-05-31 | 展讯通信（上海）有限公司 | Time estimation method and device for OFDM modulation signal |
| CN112597432A (en) * | 2020-12-28 | 2021-04-02 | 华力智芯(成都)集成电路有限公司 | Method and system for realizing acceleration of complex sequence cross-correlation on FPGA (field programmable Gate array) based on FFT (fast Fourier transform) algorithm |
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