CN104901556B - Synchronous rectification control method capable of programming dead time and synchronous rectification controller - Google Patents

Abstract

A synchronous rectification control method with programmable dead time and a synchronous rectification controller. An embodiment provides a synchronous rectification control method, comprising: providing a synchronous rectification controller having a first pin; sampling a pin voltage on the first pin to generate a sampling voltage; after generating the sampling voltage, providing a detection current, which flows out of the first pin from the synchronous rectification controller; generating a plurality of digital dead time control signals according to the sampling voltage and the pin voltage, and controlling a rectification switch according to the dead time control signals to determine a dead time of the rectification switch.

Description

Synchronous rectification control method with programmable dead time and synchronous rectification controller

technical field

The present invention generally relates to a control method and a controller for synchronous rectification of a power supply.

Background technique

In addition to requiring precise output voltage or output current for power supplies, power conversion efficiency (power conversion efficiency) is often one of the specifications that the industry cares about most.

FIG. 1 shows a known flyback switch mode power supply 10 as an example of a switch mode power supply. When the pulse width modulation controller 14 turns on the power switch 20, the input power supply V _IN and the input ground 26 enable the transformer 18 to store energy; when the power switch 20 is turned off, the transformer 18 releases energy to the output capacitor 17 and the load 16 through the rectifier diode 12, To establish an output power supply OUT (having an output voltage V _OUT ) and an output ground 28 . With an appropriate feedback path, the PWM controller 14 can adjust the duty cycle of the power switch 20 to make the output power OUT meet the desired specification.

All the secondary side current I _SEC output from the transformer 18 to the output capacitor 17 and the load 16 must pass through the rectifier diode 12 . The rectifier diode 12 is forward biased at approximately 1V, dissipating energy at a constant rate. In order to reduce the energy loss of the rectifier diode 12 and increase the energy conversion efficiency, in the known technology, a rectifier switch 24 has been developed to replace the rectifier diode 12 as shown in FIG. 2 . Such a technique is called synchronous rectification (synchronous rectification, SR). The rectifier switch 24 in the switching mode power supply 30 needs to be properly controlled to mimic the action of the rectifier diode 12 in FIG. 1 . When the power switch 20 is turned on and the transformer 18 is storing energy, the rectifier switch 24 is turned off. When the transformer 18 is in a discharge state and discharges energy, the rectifier switch 24 is turned on, providing a low-resistance and low-energy discharge path, allowing the transformer 18 to charge the output capacitor 17 . When the transformer 18 is fully discharged, the rectifier switch 24 also needs to be closed to prevent the output power OUT from storing energy on the transformer 18 .

Generally speaking, before the transformer 18 is fully discharged, the rectifier switch 24 needs to be closed, which can prevent the machine from blowing up. In this specification, the period from the closing of the rectifier switch 24 to the complete discharge of the transformer 18 is called dead time T _DEAD . The dead time T _DEAD needs to be controlled very carefully. If the stagnation time is too long, the benefit of reducing energy consumption will not be obtained. If the dead time becomes a negative value, it means that if the rectifier switch 24 is still on, the power switch 20 is turned on, and the switch mode power supply 30 is in danger of blowing up. Depending on the system, the requirements for the dead time T _DEAD are often different. Therefore, the dead time T _DEAD is preferably set by the system manufacturer and can be programmed.

When a synchronous rectifier controller controlling the rectifier switch 24 is presented as an integrated circuit, how to minimize the number of pins of the synchronous rectifier controller while providing an appropriate programmable dead time is a subject of great effort in the industry.

Contents of the invention

The embodiment provides a synchronous rectification control method, including: providing a synchronous rectification controller having a first pin; sampling a pin voltage on the first pin to generate a sampling voltage; generating the After the voltage is sampled, a detection current is provided to flow out of the first pin from the synchronous rectification controller; several digital dead time control signals are generated according to the sampled voltage and the pin voltage, and are controlled according to the dead time signal to control a rectifier switch to determine a dead time of the rectifier switch.

The embodiment provides a synchronous rectification controller for controlling a rectification switch. The synchronous rectification controller includes a first pin, a current source, a sampling circuit, an error amplifier, and an analog-to-digital converter. The current source can selectively provide a detection current to flow out of the first pin. The sampling circuit is connected to the first pin for sampling a pin voltage on the first pin to generate a sampling voltage. The error amplifier structure is used to generate an analog error signal according to the pin voltage and the sampling voltage when the detection current is provided. The ADC architecture is used to convert the error signal into a number of digital dead-time control signals. The dead time control signals can determine a dead time of the rectifier switch.

Description of drawings

FIG. 1 is a known flyback switching power supply.

FIG. 2 is a known synchronous rectification power supply.

FIG. 3 is a flyback switching power supply according to an embodiment of the present invention.

FIG. 4 illustrates part of the circuit and the resistors 90 and 92 in the synchronous rectification controller 42 in FIG. 3 .

FIG. 5 is a signal waveform diagram related to some signals in FIG. 4 .

FIG. 6 shows a control method implemented according to the present invention.

FIG. 7 shows the turn-on time control circuit of the rectifier switch 24 in the synchronous rectifier controller 42 .

FIG. 8 is a timing diagram of some signals in FIG. 7 .

【Symbol Description】

10 Switch Mode Power Supplies

12 rectifier diode

14 Pulse Width Modulation Controller

16 load

17 Output capacitance

18 Transformers

20 power switch

24 rectifier switch

26 input ground

28 output ground

30 Switch Mode Power Supplies

37 body diode

39 sense resistor

40 Switch Mode Power Supplies

42 synchronous rectification controller

44 Timing providing device

46 Discharge time recorder

47 Updating the device

48 _a , 48 _b switch

50 _A capacitance

50 _b recording capacitor

52 capacitance

53 switch

56 Voltage to Current Converter

58 launcher

60 logic circuits

62 comparators

90, 92 resistors

102 current source

104 switch

105 switch

106 sampling circuit

108 Comparators

110 operational amplifier

112 Analog to Digital Converter

114 variable resistor

140, 142, 144, 146, 148, 150, 152 steps

DB0, DB1, DB2 digital signal

DRV pin

DTB0, DTB1, DTB2 dead time control signals

EN/DT pin

GND pin

I _CHG charging current

I _SEC secondary side current

_ISET detection current

OUT output power

S _BIAS signal

S _DRV gate signal

S _EN-BIAS enabling signal

S _INI start signal

S _NB forward bias signal

S _SAMPLE signal

S _UPD update signal

SYN pin

t _START start time

t ₀ , t ₁ , t ₂ , t ₄ , t ₅ , t ₆ time points

T _DEAD dead time

T _DIS discharge time

T _SAMPLE sampling period

T _SET setting period

VCC pin

V _DS-NO-SYNC reference signal

_VENDT pin voltage

V _{ENDT_SEN} error signal

V _QUESS estimated time signal

V _IN input power supply

V _OUT output voltage

V _RAISED voltage

V _REAL current time signal

V _REF reference voltage

V _SEC Secondary side voltage

V _SPL sampling voltage

V _SYN voltage

detailed description

In this specification, there are some same symbols, which represent elements with the same or similar structure, function, and principle, and those skilled in the art can infer based on the teaching of this specification. For the sake of brevity in the description, elements with the same symbols will not be repeated.

Although this description takes a flyback switching power supply as an example, the present invention is not limited thereto. For example, the present invention can also be implemented in a buck power supply, a booster power supply, or a buck-booster power supply.

FIG. 3 shows a flyback switching power supply 40 according to an embodiment of the present invention, which has a synchronous rectification controller 42 controlling the rectification switch 24 . In this embodiment, the synchronous rectification controller 42 is a packaged integrated circuit with pins SYN, DRV, VCC, EN/DT and GND. In FIG. 3 , which does not limit the invention, the rectifier switch 24 is exemplified by a PMOS transistor with a parasitic body diode 37 . The body diode 37 is connected between the body and the drain of the rectifier switch 24 . The pin VCC of the synchronous rectification controller 42 is connected to the output power OUT rectified by the rectification switch 24 , which is also the source of the rectification switch 24 . The pin SYN of the synchronous rectification controller 42 is connected to the drain of the rectification switch 24 through the sense resistor 39 . The source of the rectifier switch 24 is shorted to the body. The pin GND of the synchronous rectification controller 42 is connected to the output ground 28 .

The pin EN/DT of the synchronous rectification controller 42 is a multi-function pin, which can provide two functions of enabling and dead time setting. The resistors 90 and 92 are connected in series between the output voltage V _OUT and the output ground 28 , and the pin EN/DT is the connecting point between the resistors 90 and 92 . Properly selecting the resistance values of the resistors 90 and 92 can approximately set the enabling condition and dead time of the synchronous rectification controller 42 .

FIG. 4 illustrates part of the circuit and the resistors 90 and 92 in the synchronous rectification controller 42 in FIG. 3 .

The comparator 108 compares the pin voltage V _ENDT on the pin EN/DT with a reference voltage V _REF to provide the enable signal S _EN-BIAS . When the pin voltage V _ENDT exceeds the reference signal V _REF , the enable signal S _EN-BIAS is enabled, and the synchronous rectification controller 42 starts to operate the internal circuit to provide proper timing. For example, after the enabling signal S _EN-BIAS is enabled, the synchronous rectification controller 42 first sets the internal dead time T _DEAD before starting to switch the synchronous rectification switch 24 .

The current source 102 provides a detection current I _SET . When the signal S _BIAS is enabled and the switch 104 is turned on, the detection current I _SET can flow out of the pin EN/DT to become the current I _B , which pulls up the pin voltage V _ENDT .

When the sampling circuit 106 is disabled with the signal S _BIAS and the switch 105 is closed, the sampling voltage V _SPL may be a sampling result of the pin voltage V _ENDT .

The operational amplifier 110 and surrounding resistors can form an error amplifier. _The difference between the sampling voltage V _SPL and the pin voltage VENDT- will be proportionally amplified to generate an analog error signal VENDT_SEN.

The analog-to-digital converter 112 can convert the error signal VENDT_SEN into a plurality of digital signals DB0 , DB1 and DB2 . Several latch circuits can latch the digital signals DB0, DB1 and DB2 to generate digital dead-time control signals DTB0, DTB1 and DTB2. In one embodiment, after the dead time control signal is generated, the detection current I _SET can be stopped. In one embodiment, after the setting of the internal dead time T _DEAD is completed, the dead time control signals DTB0 , DTB1 and DTB2 remain unchanged.

The resistance value of the variable resistor 114 is determined by the dead time control signals DTB0 , DTB1 and DTB2 , as shown in FIG. 4 .

FIG. 5 is a signal waveform diagram related to some signals in FIG. 4 .

At the start time t _START , as the output voltage V _OUT rises, the pin voltage V _ENDT exceeds the reference voltage V _REF , so the enable signal S _EN-BIAS becomes enabled. The synchronous rectification controller 42 is enabled, so the sampling period T _SAMPLE and the setting period T _SET are sequentially generated.

During the sampling period T _SAMPLE , the signal S _SAMPLE is enabled, the signal S _BIAS is disabled, and the detection current I _SET cannot flow out of the pin EN/DT. At this time, the pin voltage _VENDT is approximately proportional to the output voltage _VOUT , and the sampling voltage VSPL is approximately equal to the pin voltage VENDT. Therefore, the error signal VENDT_SEN is about 0. For example, the pin voltage V _ENDT =V _OUT *R ₉₂ /(R ₉₀ +R ₉₂ ), where R ₉₀ and R ₉₂ are the resistance values of the resistors 90 and 92 respectively.

During the set period T _SET , the signal S _SAMPLE is disabled and the signal S _BIAS is enabled. At this time, the detection current I _SET flows out of the pin EN/DT, so the pin voltage V _ENDT is approximately equal to V _OUT *R ₉₂ /(R ₉₀ +R ₉₂ )+I _SET *(R ₉₂ ||R ₉₀ ), where , R ₉₂ ||R ₉₀ represents the resistance value of resistors 90 and 92 connected in parallel. Because the signal S _SAMPLE is disabled, the sampling voltage V _SPL is approximately unchanged, which is equal to V _OUT *R ₉₂ /(R ₉₀ +R ₉₂ ). The error signal V _{ENDT_SEN} is approximately equal to I _SET *(R ₉₂ ||R ₉₀ )*K, where K is the voltage gain of the error amplifier formed by the operational amplifier 110 and the surrounding resistors. At this time, the digital signals DB0, DB1, and DB2 will reflect the analog-to-digital conversion result of the error signal VENDT_SEN, but due to the blocking of the latch circuit, the dead time control signals DTB0, DTB1, and DTB2 maintain the same state as in the sampling period T _SAMPLE .

After the set period T _SET , the signal S _SAMPLE is enabled and the signal S _BIAS is disabled. Therefore, the sense current I _SET stops flowing out of the pin EN/DT. The pin voltage V _ENDT is approximately proportional to the output voltage V _OUT , and the sampling voltage V _SPL is approximately equal to the pin voltage V _ENDT . The rising edge of the signal S _SAMPLE makes the latch circuit latch the digital signals DB0 , DB1 and DB2 to generate dead time control signals DTB0 , DTB1 and DTB2 . In one embodiment, after the dead time control signal is generated, the detection current I _SET can be stopped. As shown in Figure 5. The dead time control signals DTB0 , DTB1 and DTB2 determine the resistance value of the variable resistor 114 . After the set period T _SET , if the output voltage V _OUT is lower than the reference signal V _REF , the comparator 108 can disable the synchronous rectification controller 42 accordingly.

After the set period T _SET , the synchronous rectification controller 42 controls the synchronous rectification switch 24 according to the variable resistor 114 . The variable resistor 114 determines the on time (On time) of the synchronous rectification switch 24 , and also determines the dead time T _DEAD of the synchronous rectification switch 24 . Therefore, the dead time T _DEAD is roughly related to I _SET *(R ₉₂ ||R ₉₀ )*K. System manufacturers can select appropriate resistors 90 and 92 to set the dead time T _DEAD .

According to the above analysis, the pin EN/DT is a multi-function pin. As long as the resistors 90 and 92 are selected properly, the timing of the output voltage V _OUT enabling the synchronous rectification controller 42 and the desired value of the dead time T _DEAD can be determined.

FIG. 6 shows a control method implemented according to the present invention, and please refer to FIG. 4 and FIG. 5 for description.

Step 140 confirms that the pin voltage V _ENDT exceeds the reference signal V _REF , so the synchronous rectification controller 42 is enabled.

In step 142, the pin voltage _VENDT is sampled, so that a sampled voltage _VSPL is generated.

Step 144 provides a sense current I _SET to flow out of pin EN/DT. Therefore, the pin voltage V _ENDT will be pulled high and become different from the sampling voltage V _SPL .

Step 146 generates an error signal _{VENDT_SEN} according to the difference between the pin voltage _VENDT and the sampling voltage _VSPL . The digital conversion result of the error signal _{VENDT_SEN} is latched in step 148 to generate dead time control signals DTB0 , DTB1 and DTB2 .

Step 150 stops the detection current I _SET from flowing out of the pin EN/DT.

Step 152 determines the resistance value of the variable resistor 114 according to the dead time control signals DTB0, DTB1 and DTB2, so the on time (On time) of the synchronous rectification switch 24 is determined, and the dead time T _DEAD of the synchronous rectification switch 24 is also determined at the same time .

FIG. 7 shows the turn-on time control circuit of the rectifier switch 24 in the synchronous rectification controller 42 , as an example, how the variable resistor 114 affects the dead time T _DEAD .

The timing providing device 44 provides the forward bias signal S _NB , the start signal S _INI , and the update signal S _UPD according to the output voltage V _OUT on the pin VCC and the voltage V _SYN on the pin SYN . The discharge time recorder 46 provides the current time signal V _REAL , which approximately represents the time when the body diode 37 is in forward bias, which is approximately the time when the secondary side current I _SEC is greater than zero, and may also be approximately the time when the transformer 18 is connected to the output capacitor 17 The discharge time T _DIS . The recording capacitor _{50b provides the estimated time signal V QUESS .} The updating device 47 updates the estimated time signal V _QUESS according to the current time signal V _REAL at a preset time (to be explained later) after the discharge time T _DIS so as to approach the current time signal V _REAL . The comparator 62 and the logic circuit 60 can be regarded as a switch controller. According to the estimated time signal V _QUESS and the voltage V _RAISED , the gate signal S _DRV is generated at the pin DRV to control the rectifier switch 24 .

The estimated time signal V _QUESS represents a guess value of the discharge time T _DIS of the body diode 37 during the switching cycle. It will be explained later that in this embodiment, the estimated time signal V _QUESS will be used to determine the time point at which the rectifier switch 24 is turned off, and the estimated time signal V _QUESS will quickly discharge toward the real one as the switching period increases. Time T _DIS approaches.

FIG. 8 is a timing diagram of some signals in FIG. 7 to explain some possible operations in FIG. 7 . Please also refer to the switch mode power supply 40 in FIG. 3 .

The uppermost waveform of FIG. 8 represents the voltage difference of the output voltage V _OUT to the secondary side voltage V _SEC . At time point t ₀ , because the power switch 20 in FIG. 3 is turned off, the secondary side voltage V _SEC starts to be higher than the output voltage V _OUT , and the timing providing device 44 provides a pulse as the start signal S _INI . When the secondary side voltage V _SEC is greater than the output voltage V _OUT , the body diode 37 is in the forward bias, and the forward bias signal S _NB is logic 1; on the contrary, when the body diode 37 is in the reverse bias, the forward bias Signal S _NB is logically zero. The period during which the forward bias signal S _NB is 1 may be referred to as the discharge time T _DIS , as shown in FIG. 8 . In FIG. 8 , at the time point t ₄ , the body diode 37 becomes reverse biased, so the forward bias signal S _NB turns to logic 0, declaring the end of the discharge time T _DIS . At a time point t ₅ after the time point t ₄ , the timing providing device 44 provides another pulse as the update signal S _UPD .

At time t ₀ , the switch 53 resets the current time signal V _REAL to 0V due to the pulse of the start signal S _INI . At time t ₁ , the pulse of start signal S _INI ends. The period between the time point _t0 and _t1 may be called an initial time (initial time).

At time point t ₁ , the voltage-to-current converter 56 generates a charging current I _CHG according to the pin voltage V _ENDT , and starts to charge the capacitor 52 through the variable resistor 114 , and generates a current time signal V _REAL at one end of the capacitor 52 . The current time signal V _REAL will rise as the discharge time T _DIS increases until the discharge time T _DIS ends. Therefore, the current time signal V _REAL can be regarded as a ramp signal. After the time point _t4 , the current time signal V _REAL maintains its peak value, which represents the time period when the body diode 37 is in the forward bias state during the switching cycle, that is, the discharge time T _DIS .

As shown in FIG. 7 , the voltage V _RAISED and the current time signal V _REAL respectively represent the voltages at both ends of the variable resistor 114 . When the forward bias signal S _NB is logic 1, the voltage V _RAISED is greater than the current time signal V _REAL because the charging current I _CHG flows through the variable resistor 114 , as shown in FIG. 8 . Relative to the current time signal V _REAL , the voltage V _RAISED can be regarded as a boosted signal. The variable resistor 114 can be regarded as a bias voltage provider, respectively providing a bias voltage (offset voltage) to the current time signal V _REAL to generate the voltage V _RAISED . The magnitude of the bias voltage is controlled by the dead time control signals DTB0, DTB1 and DTB2.

At time point _t1 , since the pulse of the start signal S _INI ends, the initiator 58 can set (set) the SR flip-flop in the logic circuit 60, so that the gate signal S _DRV starts to be logic 1, as shown in FIG. 8 Show. In this embodiment, since the rectifier switch 24 is a PMOS transistor, when the gate signal S _DRV is logic 1, the gate signal S _DRV is a relatively low voltage, and the rectifier switch 24 is turned on; When S _DRV is logic 0, the gate signal S _DRV is a relatively high voltage, and the rectifier switch 24 is turned off. Turning on the rectifier switch 24 will cause the difference between the output voltage V _OUT and the secondary side voltage V _SEC to suddenly decrease. FIG. 5 also shows the reference signal V _DS-NO-SYNC , which represents the difference between the output voltage V _OUT and the secondary side voltage V _SEC when the rectifier switch 24 is not turned on.

At time t ₂ , the voltage V _RAISED exceeds the estimated time signal V _QUESS , so the comparator 62 resets the SR flip-flop in the logic circuit 60 to make the gate signal S _DRV a logic 0, and the rectifier switch 24 off. The difference between the output voltage V _OUT and the secondary side voltage V _SEC returns to be the same as the reference signal V _DS-NO-SYNC at this time. In simple terms, when the difference between the estimated time signal V _QUESS and the current time signal V _REAL is lower than the bias voltage provided by the variable resistor 114 , the rectifier switch 24 is turned off.

The period between time t ₂ and time t ₄ , as marked in FIG. 8 , is the dead time T _DEAD .

At time point t ₅ , the pulse of the update signal S _UPD first turns off the switch 48 _a , and then turns on the switch 48 _b . Therefore, when the switch 48 _a is turned off, the capacitor 50 _a can memorize the current time signal V _REAL in advance. When the switch 48 _b is turned on, since the capacitors 50 _a and 50 _b are shorted to each other, charge sharing occurs, and the estimated time signal V _QUESS is updated accordingly. For example, if the capacitance values of the capacitors 50 _a and 50 _b are approximately equal. The updated estimated time signal V _QUESS is approximately equal to the average of the pre-updated estimated time signal V _QUESS and the current time signal V _REAL , as shown in FIG. 8 . In simple terms, V _QUESS =w ^* V _QUESS +(1-w)*V _REAL , wherein w is a proportional value between 0 and 1, which is determined by the capacitance values of the capacitors 50 _a and 50 _b .

At time point t ₆ , the power switch 20 in FIG. 3 is turned off again, so the pulse of the start signal S _INI appears, and the forward bias signal S _NB turns to logic 1. The period before the time point t ₀ to t ₆ can be regarded as a switching period. In the switching cycle after the time point _{t6, the estimated time signal V QUESS is} also updated, and continues to approach the current time signal V _REAL , as shown in FIG. 8 .

It can be seen from the description of the circuit operation above that the estimated time signal V _QUESS may approach the peak value of the current time signal V _REAL by way of charge sharing every time a switching cycle passes. Such an approximation method will make the estimated time signal V _QUESS very close to the current time signal V _REAL very quickly. The bias voltage provided by the variable resistor 114 can enable the gate signal S _DRV to close the synchronous rectification switch 24 before the body diode 37 becomes reverse biased, thereby increasing the energy conversion efficiency of the synchronous rectification. Therefore, the variable resistor 114 determines the end point of the turn-on time of the synchronous rectification switch 24 , thus also determines the dead time T _DEAD . The bias voltage provided by the variable resistor 114 is relatively unaffected by process, temperature and other changes. The resistance of variable resistor 114 is programmable via resistors 90 and 92 as previously described.

In a steady state (the load 16 does not change for a long time), the length of the dead time T _DEAD is determined by the resistance value of the variable resistor 114 .

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (12)

1. a kind of synchronous rectification control method, includes：

A synchronous rectifying controller is provided, it has one first pin；

The pin voltage sampled on first pin, to produce a sampled voltage；

There is provided a detection electric current after the sampled voltage is produced, from the synchronous rectifying controller, first pin is flowed out；

According to the sampled voltage and the pin voltage, several digital dead time control signals are produced；And

According to the dead time control signal, a rectifier switch is controlled, to determine a dead time of the rectifier switch.

2. synchronous rectification control method as claimed in claim 1, wherein, first pin is a multifunctional pin, the control Method also includes：

Before the detection electric current is provided, when the pin voltage is more than a reference voltage, the enable synchronous rectifying controller.

3. synchronous rectification control method as claimed in claim 1, includes：

Compare the sampled voltage and the pin voltage, to produce the error signal of a simulation；

The error signal is converted into several data signals；And

The data signal is latched, to produce the dead time control signal.

4. synchronous rectification control method as claimed in claim 1, includes：

According to the dead time control signal, a variable resistor is controlled；

Wherein, the variable resistor is determined the dead time by framework.

5. synchronous rectification control method as claimed in claim 4, includes：

One charging current is provided, the variable resistor is flowed through, an electric capacity is charged, one is produced respectively with the two ends in the variable resistor Ramp signal and a boost signal；

When the rectifier switch is closed, an estimated time signal is updated with the ramp signal；And

An opening time of the rectifier switch is determined according to the estimated time signal and the boost signal, thus determines that this stops The stagnant time.

6. synchronous rectification control method as claimed in claim 1, wherein, when the detection electric current stops, the pin voltage with An output voltage after the rectifier switch rectification is proportional.

7. synchronous rectification control method as claimed in claim 1, wherein, when the digital dead time control signal is produced Afterwards, the detection electric current is stopped.

8. a kind of synchronous rectifying controller, to control a rectifier switch, includes：

One first pin；

One current source, optionally provides one and detects electric current, flow out first pin；

One sample circuit, is connected to first pin, to the pin voltage sampled on first pin, to produce a sampling Voltage；

One error amplifier, framework is come when the detection electric current is provided, according to the pin voltage and sampled voltage, produces one The error signal of simulation；And

The error signal is converted into several digital dead time control signals by one analog-digital converter, framework；

Wherein, the dead time control signal may decide that one of rectifier switch dead time.

9. synchronous rectifying controller as claimed in claim 8, wherein, the error signal is converted into by the analog-digital converter Several data signals, and the data signal is latched, to produce the dead time control signal.

10. synchronous rectifying controller as claimed in claim 8, order includes：

One variable resistor, is controlled by the dead time control signal.

11. synchronous rectifying controller as claimed in claim 8, includes：

One opening time controller, framework produces a ramp signal and a boost signal, includes a variable resistor, controlled In the dead time control signal；

Wherein, the variable resistor can determine the difference between the ramp signal and the boost signal.

12. synchronous rectifying controller as claimed in claim 11, wherein, the opening time controller includes：

One charging current source and an electric capacity, the variable resistor are connected between the charging current source and the electric capacity, and this can power transformation The two ends of resistance provide the ramp signal and the boost signal respectively；

One more novel circuit, when the rectifier switch is closed, an estimated time signal is updated with the ramp signal；And

One comparator, compares the estimated time signal and the ramp signal, to determine an opening time of the rectifier switch, because And determine the dead time of the rectifier switch.